14184 lines
1.6 MiB
14184 lines
1.6 MiB
; --------------------------------------------------------------------------------
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; @Title: M451 On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-08 JDU
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; 2023-11-08 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; M451_v1_fixed.svd (Ver. 1.0)
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; @Core: Cortex-M4F
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; @Chip: M451LC3AE, M451LD3AE, M451LE6AE, M451LG6AE, M451MLC3AE, M451MLD3AE,
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; M451MLE6AE, M451MLG6AE, M451MSC3AE, M451MSD3AE, M451RC3AE, M451RD3AE,
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; M451RE6AE, M451RG6AE, M451VE6AE, M451VG6AE, M452LC3AE, M452LD3AE,
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; M452LE6AE, M452LG6AE, M452RD3AE, M452RE6AE, M452RG6AE, M452VE6AE,
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; M452VG6AE, M453LC3AE, M453LD3AE, M453LE6AE, M453LG6AE, M453RD3AE,
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; M453RE6AE, M453RG6AE, M453VD3AE, M453VE6AE, M453VG6AE
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm451.per 16971 2023-11-09 16:09:22Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ACMP (Analog Comparator Controller)"
|
|
base ad:0x40045000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x0 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x0 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is unfiltered..,1: Comparator 0 output to ACMP0_O pin is from.."
|
|
bitfld.long 0x0 8.--9. "INTPOL,Interrupt Condition Polarity Selection. ACMPIF0 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,?,?"
|
|
bitfld.long 0x0 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
|
|
bitfld.long 0x0 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 0 hysteresis Disabled,1: Comparator 0 hysteresis Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled. If WKEN.."
|
|
bitfld.long 0x0 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
|
|
line.long 0x4 "ACMP_CTL1,Analog Comparator 1 Control Register"
|
|
bitfld.long 0x4 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x4 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is unfiltered..,1: Comparator 1 output to ACMP1_O pin is from.."
|
|
bitfld.long 0x4 8.--9. "INTPOL,Interrupt Condition Polarity Selection. ACMPIF1 will be set to 1 when comparator output edge condition is detected." "0: Rising edge or falling edge,1: Rising edge,?,?"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,?,?"
|
|
bitfld.long 0x4 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),?,?"
|
|
newline
|
|
bitfld.long 0x4 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
|
|
bitfld.long 0x4 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 1 hysteresis Disabled,1: Comparator 1 hysteresis Enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled. If WKEN.."
|
|
bitfld.long 0x4 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
|
|
line.long 0x8 "ACMP_STATUS,Analog Comparator Status Register"
|
|
bitfld.long 0x8 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag. This bit will be set to 1 when ACMP1 wake-up interrupt event occurs.. Note: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
bitfld.long 0x8 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag. This bit will be set to 1 when ACMP0 wake-up interrupt event occurs.. Note: Write 1 to clear this bit to 0." "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
newline
|
|
bitfld.long 0x8 5. "ACMPO1,Comparator 1 Output. Synchronized to the PCLK to allow reading by software. Cleared when the comparator 1 is disabled i.e. ACMPEN (ACMP_CTL1[0]) is cleared to 0." "0,1"
|
|
bitfld.long 0x8 4. "ACMPO0,Comparator 0 Output. Synchronized to the PCLK to allow reading by software. Cleared when the comparator 0 is disabled i.e. ACMPEN (ACMP_CTL0[0]) is cleared to 0." "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ACMPIF1,Comparator 1 Interrupt Flag. This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output. This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1.. Note: Write 1 to clear.." "0,1"
|
|
bitfld.long 0x8 0. "ACMPIF0,Comparator 0 Interrupt Flag. This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output. This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1.. Note: Write 1 to clear.." "0,1"
|
|
line.long 0xC "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
|
|
bitfld.long 0xC 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV source voltage,1: The reference voltage defined by SYS_VREFCTL.."
|
|
hexmask.long.byte 0xC 0.--3. 1. "CRVCTL,Comparator Reference Voltage Setting"
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x400A0000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CAN_CON,Control Register"
|
|
bitfld.long 0x0 7. "Test,Test Mode Enable Bit" "0: Normal Operation,1: Test Mode"
|
|
bitfld.long 0x0 6. "CCE,Configuration Change Enable Bit" "0: No write access to the Bit Timing Register,1: Write access to the Bit Timing Register.."
|
|
newline
|
|
bitfld.long 0x0 5. "DAR,Automatic Re-transmission Disable Bit" "0: Automatic Retransmission of disturbed messages..,1: Automatic Retransmission Disabled"
|
|
bitfld.long 0x0 3. "EIE,Error Interrupt Enable Bit" "0: Disabled - No Error Status Interrupt will be..,1: Enabled - A change in the bits BOff.."
|
|
newline
|
|
bitfld.long 0x0 2. "SIE,Status Change Interrupt Enable Bit" "0: Disabled - No Status Change Interrupt will be..,1: Enabled - An interrupt will be generated when a.."
|
|
bitfld.long 0x0 1. "IE,Module Interrupt Enable Bit" "0: Module Interrupt Disabled,1: Module Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "Init,Init Initialization" "0: Normal Operation,1: Initialization is started"
|
|
line.long 0x4 "CAN_STATUS,Status Register"
|
|
rbitfld.long 0x4 7. "BOff,Bus-off Status (Read Only)" "0: The CAN module is not in bus-off state,1: The CAN module is in bus-off state"
|
|
rbitfld.long 0x4 6. "EWarn,Error Warning Status (Read Only)" "0: Both error counters are below the error warning..,1: At least one of the error counters in the EML.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EPass,Error Passive (Read Only)" "0: The CAN Core is error active,1: The CAN Core is in the error passive state as.."
|
|
bitfld.long 0x4 4. "RxOK,Received a Message Successfully" "0: No message has been successfully received since..,1: A message has been successfully received since.."
|
|
newline
|
|
bitfld.long 0x4 3. "TxOK,Transmitted a Message Successfully" "0: Since this bit was reset by the CPU no message..,1: Since this bit was last reset by the CPU a.."
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code (Type of the Last Error to Occur on the CAN Bus). The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or.." "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "CAN_ERR,Error Counter Register"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter. Actual state of the Receive Error Counter. Values between 0 and 127."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter. Actual state of the Transmit Error Counter. Values between 0 and 255."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CAN_BTIME,Bit Timing Register"
|
|
bitfld.long 0x0 12.--14. "TSeg2,Time Segment After Sample Point . 0x0-0x7: Valid values for TSeg2 are [0...7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "?,?,?,?,?,?,?,7: Valid values for TSeg2 are [0"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TSeg1,Time Segment Before the Sample Point Minus Sync_Seg. 0x01-0x0F: valid values for TSeg1 are [1...15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "SJW,(Re)Synchronization Jump Width. 0x0-0x3: Valid programmed values are [0...3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used." "?,?,?,3: Valid programmed values are [0"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BRP,Baud Rate Prescaler . 0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [0...63]. The actual.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "CAN_IIDR,Interrupt Identifier Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "IntId,Interrupt Identifier (Indicates the Source of the Interrupt). If several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest priority disregarding their chronological order. An interrupt remains.."
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "CAN_TEST,Test Register (Register Map Note 1)"
|
|
rbitfld.long 0x0 7. "Rx,Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)" "0: The CAN bus is dominant (CAN_RX = '0'),1: The CAN bus is recessive (CAN_RX = '1')"
|
|
bitfld.long 0x0 5.--6. "Tx,Tx Control of CAN_TX Pin" "0: Reset value CAN_TX pin is controlled by the CAN..,1: Sample Point can be monitored at CAN_TX pin,?,?"
|
|
newline
|
|
bitfld.long 0x0 4. "LBack,Loop Back Mode Enable Bit" "0: Loop Back Mode is Disabled,1: Loop Back Mode is Enabled"
|
|
bitfld.long 0x0 3. "Silent,Silent Mode" "0: Normal operation,1: The module is in Silent Mode"
|
|
newline
|
|
bitfld.long 0x0 2. "Basic,Basic Mode" "0: Basic Mode Disabled,1: IF1 Registers used as Tx Buffer IF2 Registers.."
|
|
line.long 0x4 "CAN_BRPE,Baud Rate Prescaler Extension Register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "BRPE,BRPE: Baud Rate Prescaler Extension. 0x00-0x0F: By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs).."
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|
group.long 0x20++0x3
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|
line.long 0x0 "CAN_IF1_CREQ,IFn (Register Map Note 2) Command Request Registers"
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bitfld.long 0x0 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register is.."
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|
hexmask.long.byte 0x0 0.--5. 1. "MessageNumber,Message Number. 0x01-0x20: Valid Message Number the Message Object in the Message. RAM is selected for data transfer.. 0x00: Not a valid Message Number interpreted as 0x20.. 0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F."
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group.long 0x80++0x3
|
|
line.long 0x0 "CAN_IF2_CREQ,IFn (Register Map Note 2) Command Request Registers"
|
|
bitfld.long 0x0 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register is.."
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|
hexmask.long.byte 0x0 0.--5. 1. "MessageNumber,Message Number. 0x01-0x20: Valid Message Number the Message Object in the Message. RAM is selected for data transfer.. 0x00: Not a valid Message Number interpreted as 0x20.. 0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F."
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|
group.long 0x24++0x3
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|
line.long 0x0 "CAN_IF1_CMASK,IFn Command Mask Registers"
|
|
bitfld.long 0x0 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected Message.."
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bitfld.long 0x0 6. "Mask,Access Mask Bits. Write Operation:" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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|
newline
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bitfld.long 0x0 5. "Arb,Access Arbitration Bits. Write Operation:" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]) +.."
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bitfld.long 0x0 4. "Control,Control Access Control Bits. Write Operation:" "0: Control Bits unchanged,1: Transfer Control Bits to Message Object.."
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|
newline
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bitfld.long 0x0 3. "ClrIntPnd,Clear Interrupt Pending Bit. Write Operation:. When writing to a Message Object this bit is ignored.. Read Operation:" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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|
bitfld.long 0x0 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation. Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register.." "0: TxRqst bit unchanged.. NewDat bit remains..,1: Set TxRqst bit.. Clear NewDat bit in the Message.."
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newline
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bitfld.long 0x0 1. "DAT_A,Access Data Bytes [3:0]. Write Operation:" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message Object.."
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bitfld.long 0x0 0. "DAT_B,Access Data Bytes [7:4]. Write Operation:" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message Object.."
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|
group.long 0x84++0x3
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|
line.long 0x0 "CAN_IF2_CMASK,IFn Command Mask Registers"
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|
bitfld.long 0x0 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected Message.."
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|
bitfld.long 0x0 6. "Mask,Access Mask Bits. Write Operation:" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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|
newline
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bitfld.long 0x0 5. "Arb,Access Arbitration Bits. Write Operation:" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]) +.."
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bitfld.long 0x0 4. "Control,Control Access Control Bits. Write Operation:" "0: Control Bits unchanged,1: Transfer Control Bits to Message Object.."
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newline
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bitfld.long 0x0 3. "ClrIntPnd,Clear Interrupt Pending Bit. Write Operation:. When writing to a Message Object this bit is ignored.. Read Operation:" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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|
bitfld.long 0x0 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation. Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register.." "0: TxRqst bit unchanged.. NewDat bit remains..,1: Set TxRqst bit.. Clear NewDat bit in the Message.."
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newline
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bitfld.long 0x0 1. "DAT_A,Access Data Bytes [3:0]. Write Operation:" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message Object.."
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|
bitfld.long 0x0 0. "DAT_B,Access Data Bytes [7:4]. Write Operation:" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message Object.."
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|
group.long 0x28++0x3
|
|
line.long 0x0 "CAN_IF1_MASK1,IFn Mask 1 Registers"
|
|
hexmask.long.word 0x0 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x88++0x3
|
|
line.long 0x0 "CAN_IF2_MASK1,IFn Mask 1 Registers"
|
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hexmask.long.word 0x0 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x2C++0x3
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|
line.long 0x0 "CAN_IF1_MASK2,IFn Mask 2 Registers"
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|
bitfld.long 0x0 15. "MXtd,Mask Extended Identifier. Note: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering only these bits.." "0: The extended identifier bit (IDE) has no effect..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x0 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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newline
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hexmask.long.word 0x0 0.--12. 1. "Msk,Identifier Mask 28-16"
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group.long 0x8C++0x3
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|
line.long 0x0 "CAN_IF2_MASK2,IFn Mask 2 Registers"
|
|
bitfld.long 0x0 15. "MXtd,Mask Extended Identifier. Note: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering only these bits.." "0: The extended identifier bit (IDE) has no effect..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x0 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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newline
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hexmask.long.word 0x0 0.--12. 1. "Msk,Identifier Mask 28-16"
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|
group.long 0x30++0x3
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|
line.long 0x0 "CAN_IF1_ARB1,IFn Arbitration 1 Registers"
|
|
hexmask.long.word 0x0 0.--15. 1. "ID,Message Identifier 15-0. ID28 - ID0 29-bit Identifier ('Extended Frame').. ID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x90++0x3
|
|
line.long 0x0 "CAN_IF2_ARB1,IFn Arbitration 1 Registers"
|
|
hexmask.long.word 0x0 0.--15. 1. "ID,Message Identifier 15-0. ID28 - ID0 29-bit Identifier ('Extended Frame').. ID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x34++0x3
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|
line.long 0x0 "CAN_IF1_ARB2,IFn Arbitration 2 Registers"
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|
bitfld.long 0x0 15. "MsgVal,Message Valid. Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2) the.." "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should be.."
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|
bitfld.long 0x0 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be used..,1: The 29-bit ('extended') Identifier will be used.."
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newline
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bitfld.long 0x0 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
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|
hexmask.long.word 0x0 0.--12. 1. "ID,Message Identifier 28-16. ID28 - ID0 29-bit Identifier ('Extended Frame').. ID28 - ID18 11-bit Identifier ('Standard Frame')"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "CAN_IF2_ARB2,IFn Arbitration 2 Registers"
|
|
bitfld.long 0x0 15. "MsgVal,Message Valid. Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2) the.." "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should be.."
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|
bitfld.long 0x0 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be used..,1: The 29-bit ('extended') Identifier will be used.."
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newline
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bitfld.long 0x0 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
|
|
hexmask.long.word 0x0 0.--12. 1. "ID,Message Identifier 28-16. ID28 - ID0 29-bit Identifier ('Extended Frame').. ID28 - ID18 11-bit Identifier ('Standard Frame')"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "CAN_IF1_MCON,IFn Message Control Registers"
|
|
bitfld.long 0x0 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application software.."
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|
bitfld.long 0x0 14. "MsgLst," "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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newline
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bitfld.long 0x0 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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|
bitfld.long 0x0 12. "UMask,Use Acceptance Mask. Note: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one." "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for acceptance.."
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newline
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bitfld.long 0x0 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left unchanged..,1: IntPnd will be set after a successful.."
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|
bitfld.long 0x0 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left unchanged..,1: IntPnd will be set after a successful reception.."
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newline
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bitfld.long 0x0 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is set"
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bitfld.long 0x0 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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newline
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bitfld.long 0x0 7. "EoB,End of Buffer. Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to one." "0: Message Object belongs to a FIFO Buffer and is..,1: Single Message Object or last Message Object of.."
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|
hexmask.long.byte 0x0 0.--3. 1. "DLC,Data Length Code. 0-8: Data Frame has 0-8 data bytes.. 9-15: Data Frame has 8 data bytes. Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the.."
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group.long 0x98++0x3
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line.long 0x0 "CAN_IF2_MCON,IFn Message Control Registers"
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|
bitfld.long 0x0 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application software.."
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bitfld.long 0x0 14. "MsgLst," "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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newline
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bitfld.long 0x0 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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bitfld.long 0x0 12. "UMask,Use Acceptance Mask. Note: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one." "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for acceptance.."
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newline
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bitfld.long 0x0 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left unchanged..,1: IntPnd will be set after a successful.."
|
|
bitfld.long 0x0 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left unchanged..,1: IntPnd will be set after a successful reception.."
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newline
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bitfld.long 0x0 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is set"
|
|
bitfld.long 0x0 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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newline
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bitfld.long 0x0 7. "EoB,End of Buffer. Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to one." "0: Message Object belongs to a FIFO Buffer and is..,1: Single Message Object or last Message Object of.."
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|
hexmask.long.byte 0x0 0.--3. 1. "DLC,Data Length Code. 0-8: Data Frame has 0-8 data bytes.. 9-15: Data Frame has 8 data bytes. Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the.."
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group.long 0x3C++0x3
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line.long 0x0 "CAN_IF1_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x0 8.--15. 1. "Data_1,Data Byte 1. 2nd data byte of a CAN Data Frame"
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hexmask.long.byte 0x0 0.--7. 1. "Data_0,Data Byte 0. 1st data byte of a CAN Data Frame"
|
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group.long 0x9C++0x3
|
|
line.long 0x0 "CAN_IF2_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_1,Data Byte 1. 2nd data byte of a CAN Data Frame"
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|
hexmask.long.byte 0x0 0.--7. 1. "Data_0,Data Byte 0. 1st data byte of a CAN Data Frame"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CAN_IF1_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x0 8.--15. 1. "Data_3,Data Byte 3. 4th data byte of CAN Data Frame"
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hexmask.long.byte 0x0 0.--7. 1. "Data_2,Data Byte 2. 3rd data byte of CAN Data Frame"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "CAN_IF2_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_3,Data Byte 3. 4th data byte of CAN Data Frame"
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hexmask.long.byte 0x0 0.--7. 1. "Data_2,Data Byte 2. 3rd data byte of CAN Data Frame"
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "CAN_IF1_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_5,Data Byte 5. 6th data byte of CAN Data Frame"
|
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hexmask.long.byte 0x0 0.--7. 1. "Data_4,Data Byte 4. 5th data byte of CAN Data Frame"
|
|
group.long 0xA4++0x3
|
|
line.long 0x0 "CAN_IF2_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_5,Data Byte 5. 6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x0 0.--7. 1. "Data_4,Data Byte 4. 5th data byte of CAN Data Frame"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "CAN_IF1_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_7,Data Byte 7. 8th data byte of CAN Data Frame."
|
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hexmask.long.byte 0x0 0.--7. 1. "Data_6,Data Byte 6. 7th data byte of CAN Data Frame."
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|
group.long 0xA8++0x3
|
|
line.long 0x0 "CAN_IF2_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Data_7,Data Byte 7. 8th data byte of CAN Data Frame."
|
|
hexmask.long.byte 0x0 0.--7. 1. "Data_6,Data Byte 6. 7th data byte of CAN Data Frame."
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|
rgroup.long 0x100++0x7
|
|
line.long 0x0 "CAN_TXREQ1,Transmission Request Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "TxRqst16_1,Transmission Request Bits 16-1 (of All Message Objects). These bits are read only."
|
|
line.long 0x4 "CAN_TXREQ2,Transmission Request Register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxRqst32_17,Transmission Request Bits 32-17 (of All Message Objects). These bits are read only."
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x0 "CAN_NDAT1,New Data Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "NewData16_1,New Data Bits 16-1 (of All Message Objects)"
|
|
line.long 0x4 "CAN_NDAT2,New Data Register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "NewData32_17,New Data Bits 32-17 (of All Message Objects)"
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|
rgroup.long 0x140++0x7
|
|
line.long 0x0 "CAN_IPND1,Interrupt Pending Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "IntPnd16_1,Interrupt Pending Bits 16-1 (of All Message Objects)"
|
|
line.long 0x4 "CAN_IPND2,Interrupt Pending Register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "IntPnd32_17,Interrupt Pending Bits 32-17 (of All Message Objects)"
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|
rgroup.long 0x160++0x7
|
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line.long 0x0 "CAN_MVLD1,Message Valid Register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "MsgVal16_1,Message Valid Bits 16-1 (of All Message Objects) (Read Only). Ex. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set message object No.1 is configured."
|
|
line.long 0x4 "CAN_MVLD2,Message Valid Register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. "MsgVal32_17,Message Valid Bits 32-17 (of All Message Objects) (Read Only). Ex.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set message object No.32 is configured."
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|
group.long 0x168++0x7
|
|
line.long 0x0 "CAN_WU_EN,Wake-up Enable Control Register"
|
|
bitfld.long 0x0 0. "WAKUP_EN,Wake-up Enable Bit. Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.." "0: The wake-up function Disabled,1: The wake-up function Enabled"
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|
line.long 0x4 "CAN_WU_STATUS,Wake-up Status Register"
|
|
bitfld.long 0x4 0. "WAKUP_STS,Wake-up Status . Note: This bit can be cleared by writing '0'." "0: No wake-up event occurred,1: Wake-up event occurred"
|
|
tree.end
|
|
tree "CLK (Clock Controller)"
|
|
base ad:0x40000200
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x0 10.--11. "HXTGAIN,HXT Gain Control Bit (Write Protect). This is a protected register. Please refer to open lock sequence to program it.. Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal.." "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?"
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bitfld.long 0x0 8. "PDWTCPU,this Bit Control the Power-down Entry Condition (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Chip enters Power-down mode when the PDEN bit is..,1: Chip enters Power-down mode when the both.."
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newline
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bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect). When this bit is set to 1 Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.. (a) If the PDWTCPU is 0 then the chip enters Power-down mode immediately after the PDEN.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instant or wait CPU.."
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|
bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status. Set by 'Power-down wake-up event' it indicates that resume from Power-down mode' . The flag is set if the EINT0~5 GPIO USBH USBD OTG UART0~3 WDT CAN0 ACMP01 BOD RTC TMR0~3 I2C0~1.. Note1:.." "?,1: Write 1 to clear the bit to 0"
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newline
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bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect). Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.. Note2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
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|
bitfld.long 0x0 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect). When the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.. The delayed clock cycle is 4096 clock cycles when chip works at 4~20.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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newline
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bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
|
|
bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
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|
newline
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bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal (LXT)..,1: 32.768 kHz external low speed crystal (LXT).."
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|
bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect). The bit default value is set by flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from HXT this bit is set to 1 automatically.. Note: This bit is write protected. Refer.." "0: 4~20 MHz xxternal high speed crystal (HXT)..,1: 4~20 MHz external high speed crystal (HXT) Enabled"
|
|
line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC peripheral clock Disabled when chip..,1: FMC peripheral clock Enabled when chip operating.."
|
|
bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
|
|
newline
|
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bitfld.long 0x4 4. "USBHCKEN,USB HOST Controller Clock Enable Bit (M45xG/M45xE Only)" "0: USB HOST peripheral clock Disabled,1: USB HOST peripheral clock Enabled"
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bitfld.long 0x4 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
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bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
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line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x8 28. "EADCCKEN,Enhanced Analog-digital-converter (EADC) Clock Enable Bit" "0: EADC clock Disabled,1: EADC clock Enabled"
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bitfld.long 0x8 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled"
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bitfld.long 0x8 26. "OTGCKEN,USB OTG Clock Enable Bit (M45xG/M45xE Only)" "0: USB OTG clock Disabled,1: USB OTG clock Enabled"
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bitfld.long 0x8 24. "CAN0CKEN,CAN0 Clock Enable Bit" "0: CAN0 clock Disabled,1: CAN0 clock Enabled"
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bitfld.long 0x8 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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bitfld.long 0x8 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x8 14. "SPI2CKEN,SPI2 Clock Enable Bit (M45xG/M45xE Only)" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
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bitfld.long 0x8 13. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
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bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x8 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
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bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
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bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
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bitfld.long 0x8 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit. This bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 10 kHz.." "0: RTC APB clock Disabled,1: RTC APB clock Enabled"
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bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
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line.long 0xC "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0xC 17. "PWM1CKEN,PWM1 Clock Enable Bit" "0: PWM1 clock Disabled,1: PWM1 clock Enabled"
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bitfld.long 0xC 16. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
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bitfld.long 0xC 12. "DACCKEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled"
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bitfld.long 0xC 0. "SC0CKEN,SC0 Clock Enable Bit" "0: SC0 clock Disabled,1: SC0 clock Enabled"
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line.long 0x10 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x10 7. "PCLK1SEL,PCLK1 Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB1 bus clock source from HCLK,1: APB1 bus clock source from HCLK/2"
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bitfld.long 0x10 6. "PCLK0SEL,PCLK0 Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB0 bus clock source from HCLK,1: APB0 bus clock source from HCLK/2"
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bitfld.long 0x10 3.--5. "STCLKSEL,Cortex-M4 SysTick Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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bitfld.long 0x10 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect). Before clock switching the related clock sources (both pre-select and new-select) must be turned on.. The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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line.long 0x14 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x14 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "?,?,?,?"
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bitfld.long 0x14 28.--29. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?"
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bitfld.long 0x14 24.--25. "UARTSEL,UART Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x14 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x14 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Reserved.,1: Clock source from 32.768 kHz external low speed..,?,?"
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line.long 0x18 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x18 6.--7. "SPI2SEL,SPI2 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x18 4.--5. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x18 2.--3. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x18 1. "PWM1SEL,PWM1 Clock Source Selection. The peripheral clock source of PWM1 is defined by PWM1SEL." "0: Clock source from PLL,1: Clock source from PCLK1"
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bitfld.long 0x18 0. "PWM0SEL,PWM0 Clock Source Selection. The peripheral clock source of PWM0 is defined by PWM0SEL." "0: Clock source from PLL,1: Clock source from PCLK0"
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line.long 0x1C "CLK_CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x1C 8. "RTCSEL,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low speed..,1: Clock source from 10 kHz internal low speed RC.."
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bitfld.long 0x1C 0.--1. "SC0SEL,SC0 Clock Source Selection" "0: Clock source from 4~20 MHz external high speed..,1: Clock source from PLL,?,?"
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line.long 0x20 "CLK_CLKDIV0,Clock Divider Number Register 0"
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hexmask.long.byte 0x20 16.--23. 1. "EADCDIV,EADC Clock Divide Number From EADC Clock Source"
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hexmask.long.byte 0x20 8.--11. 1. "UARTDIV,UART Clock Divide Number From UART Clock Source"
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hexmask.long.byte 0x20 4.--7. 1. "USBDIV,USB Clock Divide Number From PLL Clock"
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hexmask.long.byte 0x20 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source"
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line.long 0x24 "CLK_CLKDIV1,Clock Divider Number Register 1"
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hexmask.long.byte 0x24 0.--7. 1. "SC0DIV,SC0 Clock Divide Number From SC0 Clock Source"
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group.long 0x40++0x3
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line.long 0x0 "CLK_PLLCTL,PLL Control Register"
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bitfld.long 0x0 23. "STBSEL,PLL Stable Counter Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 12288 PLL source clock.."
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bitfld.long 0x0 19. "PLLSRC,PLL Source Clock Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL source clock from 4~20 MHz external..,1: PLL source clock from 22.1184 MHz internal.."
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bitfld.long 0x0 18. "OE,PLL OE (FOUT Enable) Pin Control (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x0 17. "BP,PLL Bypass Control (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x0 16. "PD,Power-down Mode (Write Protect). If set the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
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bitfld.long 0x0 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect). Refer to the formulas below the table.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0,1,2,3"
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hexmask.long.byte 0x0 9.--13. 1. "INDIV,PLL Input Divider Control (Write Protect). Refer to the formulas below the table.. Note: This bit is write protected. Refer to the SYS_REGLCTL register."
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hexmask.long.word 0x0 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect). Refer to the formulas below the table.. Note: This bit is write protected. Refer to the SYS_REGLCTL register."
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rgroup.long 0x50++0x3
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line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
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bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) . This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.. Note: Write 1.." "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
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group.long 0x60++0x3
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line.long 0x0 "CLK_CLKOCTL,Clock Output Control Register"
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bitfld.long 0x0 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
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bitfld.long 0x0 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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newline
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bitfld.long 0x0 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "FREQSEL,Clock Output Frequency Selection. The formula of output frequency is. Fin is the input clock frequency.. Fout is the frequency of divider output clock.. N is the 4-bit value of FREQSEL[3:0]."
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group.long 0x70++0xF
|
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line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register"
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bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
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bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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newline
|
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bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
|
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bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
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line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register"
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bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag. Note: Write 1 to clear the bit to 0." "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
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bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag. Note: Write 1 to clear the bit to 0." "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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|
newline
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bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag. Note: Write 1 to clear the bit to 0." "0: 4~20 MHz external high speed crystal oscillator..,1: 4~20 MHz external high speed crystal oscillator.."
|
|
line.long 0x8 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary. The bits define the high value of frequency monitor window.. When HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1."
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|
line.long 0xC "CLK_CDLOWB,Clock Frequency Detector Lower Boundary Register"
|
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hexmask.long.word 0xC 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Lower Boundary. The bits define the low value of frequency monitor window.. When HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will set to 1."
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40031000
|
|
group.long 0x0++0xB
|
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line.long 0x0 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode. This field indicates the CRC operation polynomial mode." "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,?,?"
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bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length. This field indicates the write data length.. Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.. Data length is..,?,?"
|
|
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|
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bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement. This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register." "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement. This bit is used to enable the 1's complement function for write data value in CRC_DAT register." "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
|
|
newline
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bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse. This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.. Note: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB." "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse. This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.. Note: If the write data is 0xAABBCCDD the bit order reverse for CRC write data is 0x55DD33BB." "0: Bit order reversed for CRC write data in Disabled,1: Bit order reversed for CRC write data in Enabled.."
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|
newline
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bitfld.long 0x0 1. "CRCRST,CRC Engine Reset. Note1: This bit will be cleared automatically.. Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial vale." "0: No effect,1: This bit will be cleared automatically"
|
|
bitfld.long 0x0 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
line.long 0x4 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits. User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.. Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if.."
|
|
line.long 0x8 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value. This field indicates the CRC seed value."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results. This field indicates the CRC checksum result."
|
|
tree.end
|
|
tree "DAC (Digital to Analog Controller)"
|
|
base ad:0x40047000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DAC_CTL,DAC Control Register"
|
|
bitfld.long 0x0 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,?,?"
|
|
bitfld.long 0x0 10. "LALIGN,DAC Data Left-aligned Enabled Control" "0: Right alignment,1: Left alignment"
|
|
bitfld.long 0x0 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
newline
|
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bitfld.long 0x0 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin STDAC trigger,?,?,?,?,?,?"
|
|
bitfld.long 0x0 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
bitfld.long 0x0 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA underrun interrupt Disabled,1: DMA underrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
bitfld.long 0x0 1. "DACIEN,DAC Interrupt Enable Bit" "0: Interrupt is Disabled,1: Interrupt is Enabled"
|
|
bitfld.long 0x0 0. "DACEN,DAC Enable Bit" "0: DAC is Disabled,1: DAC is Enabled"
|
|
line.long 0x4 "DAC_SWTRG,DAC Software Trigger Control Register"
|
|
bitfld.long 0x4 0. "SWTRG,Software Trigger. User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0." "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
line.long 0x8 "DAC_DAT,DAC Data Holding Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "DAC_DAT,DAC 12-bit Holding Data. These bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller.."
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DAC_DATOUT,DAC Data Output Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "DATOUT,DAC 12-bit Output Data. These bits are current digital data for DAC output conversion.. It is loaded from DAC_DAT register and user cannot write it directly."
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "DAC_STATUS,DAC Status Register"
|
|
rbitfld.long 0x0 8. "BUSY,DAC Busy Flag (Read Only). This is read only bit." "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x0 1. "DMAUDR,DMA Under Run Interrupt Flag. User writes 1 to clear this bit." "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
bitfld.long 0x0 0. "FINISH,DAC Conversion Complete Finish Flag. This bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0." "0: DAC is in conversion state,1: DAC conversion finish"
|
|
line.long 0x4 "DAC_TCTL,DAC Timing Control Register"
|
|
hexmask.long.word 0x4 0.--9. 1. "SETTLET,DAC Output Settling Time. User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.. For example DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us .."
|
|
tree.end
|
|
tree "EADC (Enhanced 12-bit Analog to Digital Converter)"
|
|
base ad:0x40043000
|
|
rgroup.long 0x0++0x4F
|
|
line.long 0x0 "EADC_DAT0,A/D Data Register 0 for Sample Module 0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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|
bitfld.long 0x0 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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|
newline
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hexmask.long.word 0x0 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x4 "EADC_DAT1,A/D Data Register 1 for Sample Module 1"
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bitfld.long 0x4 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x4 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x4 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x8 "EADC_DAT2,A/D Data Register 2 for Sample Module 2"
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bitfld.long 0x8 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x8 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x8 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0xC "EADC_DAT3,A/D Data Register 3 for Sample Module 3"
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bitfld.long 0xC 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0xC 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0xC 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x10 "EADC_DAT4,A/D Data Register 4 for Sample Module 4"
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bitfld.long 0x10 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x10 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x10 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x14 "EADC_DAT5,A/D Data Register 5 for Sample Module 5"
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bitfld.long 0x14 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x14 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x14 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x18 "EADC_DAT6,A/D Data Register 6 for Sample Module 6"
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bitfld.long 0x18 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x18 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x18 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x1C "EADC_DAT7,A/D Data Register 7 for Sample Module 7"
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bitfld.long 0x1C 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x1C 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x1C 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x20 "EADC_DAT8,A/D Data Register 8 for Sample Module 8"
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bitfld.long 0x20 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x20 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x20 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x24 "EADC_DAT9,A/D Data Register 9 for Sample Module 9"
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bitfld.long 0x24 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x24 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x24 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x28 "EADC_DAT10,A/D Data Register 10 for Sample Module 10"
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bitfld.long 0x28 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x28 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x28 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x2C "EADC_DAT11,A/D Data Register 11 for Sample Module 11"
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bitfld.long 0x2C 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x2C 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x2C 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x30 "EADC_DAT12,A/D Data Register 12 for Sample Module 12"
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bitfld.long 0x30 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x30 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x30 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x34 "EADC_DAT13,A/D Data Register 13 for Sample Module 13"
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bitfld.long 0x34 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x34 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x34 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x38 "EADC_DAT14,A/D Data Register 14 for Sample Module 14"
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bitfld.long 0x38 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x38 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x38 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x3C "EADC_DAT15,A/D Data Register 15 for Sample Module 15"
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bitfld.long 0x3C 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x3C 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x3C 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x40 "EADC_DAT16,A/D Data Register 16 for Sample Module 16"
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bitfld.long 0x40 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x40 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x40 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x44 "EADC_DAT17,A/D Data Register 17 for Sample Module 17"
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bitfld.long 0x44 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x44 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x44 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x48 "EADC_DAT18,A/D Data Register 18 for Sample Module 18"
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bitfld.long 0x48 17. "VALID,Valid Flag. This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x48 16. "OV,Overrun Flag. If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.. Note: It is cleared by hardware after EADC_DAT register is read." "0: Data in RESULT[11:0] is recent conversion result,1: Data in RESULT[11:0] is overwrite"
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hexmask.long.word 0x48 0.--15. 1. "RESULT,A/D Conversion Result. This field contains 12 bits conversion result.. When DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].. When DMOF.."
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line.long 0x4C "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x4C 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register. This is a read only register.. NOTE: After PDMA read this register the VAILD of the shadow EADC_DAT register will be automatically cleared."
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group.long 0x50++0x3
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line.long 0x0 "EADC_CTL,A/D Control Register"
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bitfld.long 0x0 16.--18. "SMPTSEL,ADC Internal Sampling Time Selection" "0: 1 ADC clock sampling time,1: 2 ADC clock sampling time,?,?,?,?,?,?"
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bitfld.long 0x0 11. "PDMAEN,PDMA Transfer Enable Bit. When A/D conversion is completed the converted data is loaded into EADC_DATn (n: 0 ~ 18) register user can enable this bit to generate a PDMA data transfer request." "0: PDMA data transfer Disabled,1: PDMA data transfer Enabled"
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bitfld.long 0x0 9. "DMOF,ADC Differential Input Mode Output Format. Note: This bit must be set to 0 in single-end analog input mode." "0: A/D conversion result will be filled in RESULT..,1: A/D conversion result will be filled in RESULT.."
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bitfld.long 0x0 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x0 5. "ADCIEN3,Specific Sample Module A/D ADINT3 Interrupt Enable Bit. The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion. If ADCIEN3 bit is set then conversion end interrupt request ADINT3.." "0: Specific sample module A/D ADINT3 interrupt..,1: Specific sample module A/D ADINT3 interrupt.."
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bitfld.long 0x0 4. "ADCIEN2,Specific Sample Module A/D ADINT2 Interrupt Enable Bit. The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion. If ADCIEN2 bit is set then conversion end interrupt request ADINT2.." "0: Specific sample module A/D ADINT2 interrupt..,1: Specific sample module A/D ADINT2 interrupt.."
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bitfld.long 0x0 3. "ADCIEN1,Specific Sample Module A/D ADINT1 Interrupt Enable Bit. The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion. If ADCIEN1 bit is set then conversion end interrupt request ADINT1.." "0: Specific sample module A/D ADINT1 interrupt..,1: Specific sample module A/D ADINT1 interrupt.."
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bitfld.long 0x0 2. "ADCIEN0,Specific Sample Module A/D ADINT0 Interrupt Enable Bit. The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion. If ADCIEN0 bit is set then conversion end interrupt request ADINT0.." "0: Specific sample module A/D ADINT0 interrupt..,1: Specific sample module A/D ADINT0 interrupt.."
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bitfld.long 0x0 1. "ADCRST,ADC A/D Converter Control Circuits Reset. Note: ADCRST bit remains 1 during ADC reset when ADC reset end the ADCRST bit is automatically cleared to 0." "0: No effect,1: Cause ADC control circuits reset to initial.."
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bitfld.long 0x0 0. "ADCEN,A/D Converter Enable Bit. Note: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption." "0: ADC Disabled,1: ADC Enabled"
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wgroup.long 0x54++0x3
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line.long 0x0 "EADC_SWTRG,A/D Sample Module Software Start Register"
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hexmask.long.tbyte 0x0 0.--18. 1. "SWTRG,A/D Sample Module 0~18 Software Force to Start ADC Conversion. Note: After write this register to start ADC conversion the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample.."
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group.long 0x58++0x7
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line.long 0x0 "EADC_PENDSTS,A/D Start of Conversion Pending Flag Register"
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hexmask.long.tbyte 0x0 0.--18. 1. "STPF,A/D Sample Module 0~18 Start of Conversion Pending Flag. Read:"
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line.long 0x4 "EADC_OVSTS,A/D Sample Module Start of Conversion Overrun Flag Register"
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hexmask.long.tbyte 0x4 0.--18. 1. "SPOVF,A/D SAMPLE0~18 Overrun Flag. Note: This bit is cleared by writing 1 to it."
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group.long 0x80++0x4B
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line.long 0x0 "EADC_SCTL0,A/D Sample Module 0 Control Register"
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hexmask.long.byte 0x0 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x0 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register. (default),1: Sample has two sample result registers"
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bitfld.long 0x0 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x0 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x0 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x0 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x0 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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bitfld.long 0x0 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x0 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x4 "EADC_SCTL1,A/D Sample Module 1 Control Register"
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hexmask.long.byte 0x4 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x4 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register. (default),1: Sample has two sample result registers"
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bitfld.long 0x4 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x4 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x4 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x4 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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newline
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bitfld.long 0x4 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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bitfld.long 0x4 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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newline
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hexmask.long.byte 0x4 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x8 "EADC_SCTL2,A/D Sample Module 2 Control Register"
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hexmask.long.byte 0x8 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x8 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register. (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x8 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x8 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x8 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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newline
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bitfld.long 0x8 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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bitfld.long 0x8 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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newline
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hexmask.long.byte 0x8 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0xC "EADC_SCTL3,A/D Sample Module 3 Control Register"
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hexmask.long.byte 0xC 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0xC 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register. (default),1: Sample has two sample result registers"
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bitfld.long 0xC 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0xC 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0xC 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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newline
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bitfld.long 0xC 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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bitfld.long 0xC 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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newline
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hexmask.long.byte 0xC 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x10 "EADC_SCTL4,A/D Sample Module 4 Control Register"
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hexmask.long.byte 0x10 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x10 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x10 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x10 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x10 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x10 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x10 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x10 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x14 "EADC_SCTL5,A/D Sample Module 5 Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x14 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x14 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x14 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x14 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x14 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x14 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x14 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x18 "EADC_SCTL6,A/D Sample Module 6 Control Register"
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hexmask.long.byte 0x18 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x18 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x18 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x18 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x18 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x18 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x18 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x18 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x1C "EADC_SCTL7,A/D Sample Module 7 Control Register"
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hexmask.long.byte 0x1C 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x1C 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x1C 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x1C 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x1C 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x1C 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x1C 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x1C 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x20 "EADC_SCTL8,A/D Sample Module 8 Control Register"
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hexmask.long.byte 0x20 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x20 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x20 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x20 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x20 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x20 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x20 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x20 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x24 "EADC_SCTL9,A/D Sample Module 9 Control Register"
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hexmask.long.byte 0x24 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x24 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x24 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x24 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x24 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x24 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x24 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x24 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x28 "EADC_SCTL10,A/D Sample Module 10 Control Register"
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hexmask.long.byte 0x28 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x28 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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hexmask.long.byte 0x28 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x28 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x28 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x28 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x28 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x28 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x2C "EADC_SCTL11,A/D Sample Module 11 Control Register"
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hexmask.long.byte 0x2C 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x2C 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x2C 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x2C 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x2C 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x2C 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x2C 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x2C 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x30 "EADC_SCTL12,A/D Sample Module 12 Control Register"
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hexmask.long.byte 0x30 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x30 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x30 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x30 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x30 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x30 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x30 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x30 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x34 "EADC_SCTL13,A/D Sample Module 13 Control Register"
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hexmask.long.byte 0x34 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x34 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x34 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x34 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x34 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x34 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x34 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x34 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x38 "EADC_SCTL14,A/D Sample Module 14 Control Register"
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hexmask.long.byte 0x38 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x38 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x38 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x38 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x38 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x38 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x38 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x38 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x3C "EADC_SCTL15,A/D Sample Module 15 Control Register"
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hexmask.long.byte 0x3C 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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bitfld.long 0x3C 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D end of..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at A/D start.."
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newline
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hexmask.long.byte 0x3C 16.--20. 1. "TRGSEL,A/D Sample Module Start of Conversion Trigger Source Selection"
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hexmask.long.byte 0x3C 8.--15. 1. "TRGDLYCNT,A/D Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x3C 6.--7. "TRGDLYDIV,A/D Sample Module Start of Conversion Trigger Delay Clock Divider Selection. Trigger delay clock frequency:" "0: ADC_CLK/1,1: ADC_CLK/2,?,?"
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bitfld.long 0x3C 5. "EXTFEN,A/D External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when A/D selects STADC as..,1: Falling edge Enabled when A/D selects STADC as.."
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newline
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bitfld.long 0x3C 4. "EXTREN,A/D External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when A/D selects STADC as..,1: Rising edge Enabled when A/D selects STADC as.."
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hexmask.long.byte 0x3C 0.--3. 1. "CHSEL,A/D Sample Module Channel Selection"
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line.long 0x40 "EADC_SCTL16,A/D Sample Module 16 Control Register"
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hexmask.long.byte 0x40 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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line.long 0x44 "EADC_SCTL17,A/D Sample Module 17 Control Register"
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hexmask.long.byte 0x44 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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line.long 0x48 "EADC_SCTL18,A/D Sample Module 18 Control Register"
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hexmask.long.byte 0x48 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend. When A/D converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend A/D sampling time after trigger source is coming to get enough.."
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group.long 0xD0++0x1F
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line.long 0x0 "EADC_INTSRC0,ADC Interrupt 0 Source Enable Control Register."
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bitfld.long 0x0 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x0 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x0 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x0 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x0 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x0 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x0 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x0 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x0 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x0 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x0 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x0 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x0 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x0 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x0 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x0 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x0 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x0 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x0 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x4 "EADC_INTSRC1,ADC Interrupt 1 Source Enable Control Register."
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bitfld.long 0x4 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x4 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x4 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x4 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x4 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x4 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x4 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x4 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x4 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x4 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x4 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x4 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0x4 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x4 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x4 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x4 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x4 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x4 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x4 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x8 "EADC_INTSRC2,ADC Interrupt 2 Source Enable Control Register."
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bitfld.long 0x8 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x8 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x8 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x8 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x8 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x8 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0x8 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x8 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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newline
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bitfld.long 0x8 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x8 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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newline
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bitfld.long 0x8 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x8 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0x8 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x8 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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newline
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bitfld.long 0x8 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x8 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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newline
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bitfld.long 0x8 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x8 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x8 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0xC "EADC_INTSRC3,ADC Interrupt 3 Source Enable Control Register."
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bitfld.long 0xC 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0xC 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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newline
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bitfld.long 0xC 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0xC 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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newline
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bitfld.long 0xC 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0xC 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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newline
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bitfld.long 0xC 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0xC 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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newline
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bitfld.long 0xC 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0xC 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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newline
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bitfld.long 0xC 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0xC 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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newline
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bitfld.long 0xC 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0xC 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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newline
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bitfld.long 0xC 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0xC 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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newline
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bitfld.long 0xC 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0xC 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0xC 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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line.long 0x10 "EADC_CMP0,A/D Result Compare Register 0"
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hexmask.long.word 0x10 16.--27. 1. "CMPDAT,Comparison Data. The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x10 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register." "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x10 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x10 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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newline
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bitfld.long 0x10 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x10 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x10 0. "ADCMPEN,A/D Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x14 "EADC_CMP1,A/D Result Compare Register 1"
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hexmask.long.word 0x14 16.--27. 1. "CMPDAT,Comparison Data. The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x14 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register." "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x14 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x14 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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newline
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bitfld.long 0x14 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x14 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x14 0. "ADCMPEN,A/D Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x18 "EADC_CMP2,A/D Result Compare Register 2"
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hexmask.long.word 0x18 16.--27. 1. "CMPDAT,Comparison Data. The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x18 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register." "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x18 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x18 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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newline
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bitfld.long 0x18 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x18 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x18 0. "ADCMPEN,A/D Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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line.long 0x1C "EADC_CMP3,A/D Result Compare Register 3"
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hexmask.long.word 0x1C 16.--27. 1. "CMPDAT,Comparison Data. The 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software."
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bitfld.long 0x1C 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register." "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when both.."
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hexmask.long.byte 0x1C 8.--11. 1. "CMPMCNT,Compare Match Count"
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hexmask.long.byte 0x1C 3.--7. 1. "CMPSPL,Compare Sample Module Selection"
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newline
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bitfld.long 0x1C 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x1C 1. "ADCMPIE,A/D Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x1C 0. "ADCMPEN,A/D Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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rgroup.long 0xF0++0x7
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line.long 0x0 "EADC_STATUS0,A/D Status Register 0"
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hexmask.long.word 0x0 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
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hexmask.long.word 0x0 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
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line.long 0x4 "EADC_STATUS1,A/D Status Register 1"
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bitfld.long 0x4 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
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group.long 0xF8++0x3
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line.long 0x0 "EADC_STATUS2,A/D Status Register 2"
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bitfld.long 0x0 27. "AOV,for All Sample Module A/D Result Data Register Overrun Flags Check . Note: This bit will keep 1 when any OVn Flag is equal to 1." "0: None of sample module data register overrun flag..,1: Any one of sample module data register overrun.."
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bitfld.long 0x0 26. "AVALID,for All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check. Note: This bit will keep 1 when any VALIDn Flag is equal to 1." "0: None of sample module data register valid flag..,1: Any one of sample module data register valid.."
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bitfld.long 0x0 25. "STOVF,for All A/D Sample Module Start of Conversion Overrun Flags Check. Note: This bit will keep 1 when any SPOVFn Flag is equal to 1." "0: None of sample module event overrun flag SPOVFn..,1: Any one of sample module event overrun flag.."
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bitfld.long 0x0 24. "ADOVIF,All A/D Interrupt Flag Overrun Bits Check . Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1." "0: None of ADINT interrupt flag ADOVIFn..,1: Any one of ADINT interrupt flag ADOVIFn.."
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bitfld.long 0x0 23. "BUSY,Busy/Idle. Note: This bit is read only." "0: EADC is in idle state,1: EADC is busy at conversion"
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hexmask.long.byte 0x0 16.--20. 1. "CHANNEL,Current Conversion Channel"
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newline
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bitfld.long 0x0 15. "ADCMPO3,ADC Compare 3 Output Status. The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT3..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 14. "ADCMPO2,ADC Compare 2 Output Status. The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT2..,1: Conversion result in EADC_DAT great than or.."
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newline
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bitfld.long 0x0 13. "ADCMPO1,ADC Compare 1 Output Status. The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT1..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x0 12. "ADCMPO0,ADC Compare 0 Output Status. The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status." "0: Conversion result in EADC_DAT less than CMPDAT0..,1: Conversion result in EADC_DAT great than or.."
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newline
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bitfld.long 0x0 11. "ADOVIF3,A/D ADINT3 Interrupt Flag Overrun. Note: This bit is cleared by writing 1 to it." "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x0 10. "ADOVIF2,A/D ADINT2 Interrupt Flag Overrun. Note: This bit is cleared by writing 1 to it." "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is overwritten to 1"
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newline
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bitfld.long 0x0 9. "ADOVIF1,A/D ADINT1 Interrupt Flag Overrun. Note: This bit is cleared by writing 1 to it." "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x0 8. "ADOVIF0,A/D ADINT0 Interrupt Flag Overrun. Note: This bit is cleared by writing 1 to it." "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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newline
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bitfld.long 0x0 7. "ADCMPF3,ADC Compare 3 Flag. When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.. Note: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x0 6. "ADCMPF2,ADC Compare 2 Flag. When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.. Note: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x0 5. "ADCMPF1,ADC Compare 1 Flag. When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.. Note: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x0 4. "ADCMPF0,ADC Compare 0 Flag. When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.. Note: This bit is cleared by writing 1 to it." "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x0 3. "ADIF3,A/D ADINT3 Interrupt Flag. Note1: This bit is cleared by writing 1 to it.. Note2:This bit indicates whether an A/D conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 2. "ADIF2,A/D ADINT2 Interrupt Flag. Note1: This bit is cleared by writing 1 to it. . Note2:This bit indicates whether an A/D conversion of specific sample module has been completed" "0: No ADINT2 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 1. "ADIF1,A/D ADINT1 Interrupt Flag. Note1: This bit is cleared by writing 1 to it.. Note2:This bit indicates whether an A/D conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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bitfld.long 0x0 0. "ADIF0,A/D ADINT0 Interrupt Flag. Note1: This bit is cleared by writing 1 to it.. Note2:This bit indicates whether an A/D conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: This bit is cleared by writing 1 to it"
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|
rgroup.long 0xFC++0x13
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|
line.long 0x0 "EADC_STATUS3,A/D Status Register 3"
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|
hexmask.long.byte 0x0 0.--4. 1. "CURSPL,ADC Current Sample Module. This register show the current ADC is controlled by which sample module control logic modules.. If the ADC is Idle this bit filed will set to 0x1F.. This is a read only register."
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|
line.long 0x4 "EADC_DDAT0,A/D Double Data Register 0 for Sample Module 0"
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bitfld.long 0x4 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0x4 16. "OV,Overrun Flag. If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is recent..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is.."
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hexmask.long.word 0x4 0.--15. 1. "RESULT,A/D Conversion Results. This field contains 12 bits conversion results.. When the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].. When.."
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|
line.long 0x8 "EADC_DDAT1,A/D Double Data Register 1 for Sample Module 1"
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|
bitfld.long 0x8 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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bitfld.long 0x8 16. "OV,Overrun Flag. If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is recent..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is.."
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hexmask.long.word 0x8 0.--15. 1. "RESULT,A/D Conversion Results. This field contains 12 bits conversion results.. When the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].. When.."
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|
line.long 0xC "EADC_DDAT2,A/D Double Data Register 2 for Sample Module 2"
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|
bitfld.long 0xC 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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|
bitfld.long 0xC 16. "OV,Overrun Flag. If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is recent..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is.."
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hexmask.long.word 0xC 0.--15. 1. "RESULT,A/D Conversion Results. This field contains 12 bits conversion results.. When the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].. When.."
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|
line.long 0x10 "EADC_DDAT3,A/D Double Data Register 3 for Sample Module 3"
|
|
bitfld.long 0x10 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is not..,1: Double data in RESULT (EADC_DDATn[15:0]) is valid"
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|
bitfld.long 0x10 16. "OV,Overrun Flag. If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1. It is cleared by hardware after EADC_DDAT register is read." "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is recent..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is.."
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newline
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hexmask.long.word 0x10 0.--15. 1. "RESULT,A/D Conversion Results. This field contains 12 bits conversion results.. When the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].. When.."
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|
tree.end
|
|
tree "EBI (External Bus Interface)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "EBI_CTL0,External Bus Interface Bank0 Control Register"
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|
bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit. Note: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE. The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.. Note: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider. The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse. This bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select. This bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x0 0. "EN,EBI Enable Bit. This bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
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|
line.long 0x4 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read. This field defines the number of R2R idle cycle.. When read action is finish and next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: The Data Access Hold Time (tAHD) during EBI..,1: The Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: The Data Access Hold Time (tAHD) during EBI..,1: The Data Access Hold Time (tAHD) during EBI.."
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hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write. This field defines the number of W2X idle cycle.. When write action is finish W2X idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time. TAHD define data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time. TACC define data access time (tACC)."
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|
group.long 0x10++0x7
|
|
line.long 0x0 "EBI_CTL1,External Bus Interface Bank1 Control Register"
|
|
bitfld.long 0x0 24. "WBUFEN,EBI Write Buffer Enable Bit. Note: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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|
bitfld.long 0x0 16.--18. "TALE,Extend Time of ALE. The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.. Note: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 8.--10. "MCLKDIV,External Output Clock Divider. The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:" "0: HCLK/1,1: HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x0 2. "CSPOLINV,Chip Select Pin Polar Inverse. This bit defines the active level of EBI chip select pin (EBI_nCS)." "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x0 1. "DW16,EBI Data Width 16-bit Select. This bit defines if the EBI data width is 8-bit or 16-bit." "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x0 0. "EN,EBI Enable Bit. This bit is the functional enable bit for EBI." "0: EBI function Disabled,1: EBI function Enabled"
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|
line.long 0x4 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
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hexmask.long.byte 0x4 24.--27. 1. "R2R,Idle Cycle Between Read-to-read. This field defines the number of R2R idle cycle.. When read action is finish and next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state."
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bitfld.long 0x4 23. "WAHDOFF,Access Hold Time Disable Control When Write" "0: The Data Access Hold Time (tAHD) during EBI..,1: The Data Access Hold Time (tAHD) during EBI.."
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newline
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bitfld.long 0x4 22. "RAHDOFF,Access Hold Time Disable Control When Read" "0: The Data Access Hold Time (tAHD) during EBI..,1: The Data Access Hold Time (tAHD) during EBI.."
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hexmask.long.byte 0x4 12.--15. 1. "W2X,Idle Cycle After Write. This field defines the number of W2X idle cycle.. When write action is finish W2X idle cycle is inserted and EBI_nCS return to idle state."
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newline
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bitfld.long 0x4 8.--10. "TAHD,EBI Data Access Hold Time. TAHD define data access hold time (tAHD)." "0,1,2,3,4,5,6,7"
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|
hexmask.long.byte 0x4 3.--7. 1. "TACC,EBI Data Access Time. TACC define data access time (tACC)."
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tree.end
|
|
tree "FMC (Flash Memory Controller)"
|
|
base ad:0x4000C000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "FMC_ISPCTL,ISP Control Register"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect). This bit is set by hardware when a triggered ISP meets any of the following conditions:. This bit needs to be cleared by writing 1 to it.. (1) APROM writes to itself if APUEN is set to 0.. (2) LDROM writes to itself.." "0,1"
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bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect). LDROM update enable bit.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
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newline
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bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
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newline
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bitfld.long 0x0 1. "BS,Boot Select (Write Protect). Set/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Booting from APROM,1: Booting from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect). ISP function enable bit. Set this bit to enable ISP function.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled"
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line.long 0x4 "FMC_ISPADDR,ISP Address Register"
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hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address. The NuMicro M451 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.. For Checksum Calculation command this field is the flash.."
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line.long 0x8 "FMC_ISPDAT,ISP Data Register"
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|
hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data. Write data to this register before ISP program operation.. Read data from this register after ISP read operation."
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|
line.long 0xC "FMC_ISPCMD,ISP CMD Register"
|
|
hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP CMD. ISP command table is shown below:. The other commands are invalid."
|
|
line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
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bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect). Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed"
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|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "FMC_DFBA,Data Flash Base Address"
|
|
hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address. This register indicates Data Flash start address. It is a read only register.. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1"
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|
group.long 0x18++0x3
|
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line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register"
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bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect). The NuMicro M451 series support adjustable flash access timing to optimize the flash access cycles in different working frequency.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "?,1: Frequency 12MHz,?,?,?,?,?,?"
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group.long 0x40++0x3
|
|
line.long 0x0 "FMC_ISPSTS,ISP Status Register"
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|
hexmask.long.word 0x0 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only). All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0] 9'h000} ~ {VECMAP[14:0] 9'h1FF}"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect). This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1).." "0,1"
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newline
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rbitfld.long 0x0 5. "PGFF,Flash Program with Fast Verification Flag (Read Only). This bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP flash erase or ISP read CID operation" "0: Flash Program is success,1: Flash Program is fail. Program data is different.."
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rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only). This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?"
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newline
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rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only). Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.. This bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed"
|
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group.long 0x80++0xF
|
|
line.long 0x0 "FMC_MPDAT0,ISP Data0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "ISPDAT0,ISP Data 0. This register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data."
|
|
line.long 0x4 "FMC_MPDAT1,ISP Data1 Register"
|
|
hexmask.long 0x4 0.--31. 1. "ISPDAT1,ISP Data 1. This register is the second 32-bit data for 64-bit/multi-word programming."
|
|
line.long 0x8 "FMC_MPDAT2,ISP Data2 Register"
|
|
hexmask.long 0x8 0.--31. 1. "ISPDAT2,ISP Data 2. This register is the third 32-bit data for multi-word programming."
|
|
line.long 0xC "FMC_MPDAT3,ISP Data3 Register"
|
|
hexmask.long 0xC 0.--31. 1. "ISPDAT3,ISP Data 3. This register is the fourth 32-bit data for multi-word programming."
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x0 "FMC_MPSTS,ISP Multi-program Status Register"
|
|
bitfld.long 0x0 7. "D3,ISP DATA 3 Flag (Read Only). This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete." "0: FMC_MPDAT3 register is empty or program to flash..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x0 6. "D2,ISP DATA 2 Flag (Read Only). This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete." "0: FMC_MPDAT2 register is empty or program to flash..,1: FMC_MPDAT2 register has been written and not.."
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newline
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bitfld.long 0x0 5. "D1,ISP DATA 1 Flag (Read Only). This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete." "0: FMC_MPDAT1 register is empty or program to flash..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x0 4. "D0,ISP DATA 0 Flag (Read Only). This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete." "0: FMC_MPDAT0 register is empty or program to flash..,1: FMC_MPDAT0 register has been written and not.."
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newline
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bitfld.long 0x0 2. "ISPFF,ISP Fail Flag (Read Only). This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1) APROM.." "0,1"
|
|
bitfld.long 0x0 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
|
|
newline
|
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bitfld.long 0x0 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only). Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.. This bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
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|
line.long 0x4 "FMC_MPADDR,ISP Multi-program Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "MPADDR,ISP Multi-word Program Address. MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.. MPADDR will keep the final ISP address when ISP multi-word program is complete."
|
|
tree.end
|
|
tree "GPIO (General Purpose I/Os)"
|
|
base ad:0x40004000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "PA_MODE,PA I/O Mode Control"
|
|
bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
|
|
bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
|
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newline
|
|
bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
|
|
bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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newline
|
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
|
|
bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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newline
|
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
|
|
bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x3
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line.long 0x0 "PA_PIN,PA Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0x14++0x17
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line.long 0x0 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x40++0xF
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line.long 0x0 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x50++0x3
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line.long 0x0 "PB_PIN,PB Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0x54++0x17
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line.long 0x0 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x80++0xF
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line.long 0x0 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x90++0x3
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line.long 0x0 "PC_PIN,PC Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0x94++0x17
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line.long 0x0 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0xC0++0xF
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line.long 0x0 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0xD0++0x3
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line.long 0x0 "PD_PIN,PD Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0xD4++0x17
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line.long 0x0 "PD_DBEN,PD De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x100++0xF
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line.long 0x0 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x110++0x3
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line.long 0x0 "PE_PIN,PE Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0x114++0x1B
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line.long 0x0 "PE_DBEN,PE De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PE_INTEN,PE Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PE_SLEWCTL,PE High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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line.long 0x18 "PE_DRVCTL,PE High Drive Strength Control Register"
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bitfld.long 0x18 13. "HDRVEN13,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x18 12. "HDRVEN12,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x18 11. "HDRVEN11,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x18 10. "HDRVEN10,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x18 9. "HDRVEN9,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x18 8. "HDRVEN8,Port E Pin[N] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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group.long 0x140++0xF
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line.long 0x0 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 28.--29. "MODE14,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 26.--27. "MODE13,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 24.--25. "MODE12,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 22.--23. "MODE11,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 20.--21. "MODE10,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 18.--19. "MODE9,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 16.--17. "MODE8,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 14.--15. "MODE7,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 12.--13. "MODE6,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 10.--11. "MODE5,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 8.--9. "MODE4,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 6.--7. "MODE3,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 4.--5. "MODE2,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 2.--3. "MODE1,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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bitfld.long 0x0 0.--1. "MODE0,Port A-f I/O Pin[N] Mode Control. Determine each I/O mode of Px.n pins.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,?,3: The PB"
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line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-f Pin[N] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-f Pin[N] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note2: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 14. "DATMSK14,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 13. "DATMSK13,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 12. "DATMSK12,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 11. "DATMSK11,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 10. "DATMSK10,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 9. "DATMSK9,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 8. "DATMSK8,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 7. "DATMSK7,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 6. "DATMSK6,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 5. "DATMSK5,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 4. "DATMSK4,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 3. "DATMSK3,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 2. "DATMSK2,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 1. "DATMSK1,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0xC 0. "DATMSK0,Port A-f Pin[N] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x150++0x3
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line.long 0x0 "PF_PIN,PF Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-f Pin[N] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note1: . Note2: The.." "0,1"
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group.long 0x154++0x17
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line.long 0x0 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x0 15. "DBEN15,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-f Pin[N] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-f Pin[N] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x8 31. "RHIEN15,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-f Pin[N] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-f Pin[N] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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newline
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bitfld.long 0xC 9. "INTSRC9,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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newline
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bitfld.long 0xC 7. "INTSRC7,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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newline
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bitfld.long 0xC 5. "INTSRC5,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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newline
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bitfld.long 0xC 3. "INTSRC3,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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newline
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bitfld.long 0xC 1. "INTSRC1,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-f Pin[N] Interrupt Source Flag. Write Operation :. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x10 15. "SMTEN15,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 13. "SMTEN13,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 11. "SMTEN11,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 9. "SMTEN9,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 7. "SMTEN7,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 5. "SMTEN5,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 3. "SMTEN3,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x10 1. "SMTEN1,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-f Pin[N] Input Schmitt Trigger Enable Bit. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x14 15. "HSREN15,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 13. "HSREN13,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 11. "HSREN11,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 9. "HSREN9,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 7. "HSREN7,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 5. "HSREN5,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 3. "HSREN3,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 1. "HSREN1,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-f Pin[N] High Slew Rate Control. Note2: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x440++0x3
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line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control Register"
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bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode. Note: It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x800++0x13B
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line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x20 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x24 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x28 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x30 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x34 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x38 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x40 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x44 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x48 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x4C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x50 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x54 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x58 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x5C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x60 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x64 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x68 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x6C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x70 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x74 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x78 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
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bitfld.long 0x7C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x80 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x84 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x88 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x8C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x90 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x94 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x98 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0x9C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xA8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xAC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xB8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
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bitfld.long 0xBC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xC8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xCC "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xCC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD0 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD4 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xD8 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xD8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xDC "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xDC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE0 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE4 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xE8 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xE8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xEC "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xEC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xF0 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xF4 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xF8 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xF8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xFC "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
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bitfld.long 0xFC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x100 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x100 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x104 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x104 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x108 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x108 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x10C "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x10C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x110 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x110 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x114 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x114 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x118 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x118 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x11C "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x11C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x120 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x120 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x124 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x124 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x128 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x128 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x12C "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x12C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x130 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x130 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x134 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x134 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x138 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
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bitfld.long 0x138 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x940++0x1F
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line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x0 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x4 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x8 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x8 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0xC "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0xC 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x10 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x10 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x14 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x14 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x18 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x18 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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line.long 0x1C "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.N Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Note3: The PB.9/PB.10/PC.9/PC.14/PC.15/PD.10/PD.11/PE.2/PE.6/PE.7/PE.14 pin is ignored for M45xD/M45xC." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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tree.end
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tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
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base ad:0x0
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tree "I2C0"
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base ad:0x40080000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL,I2C Control Register"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C Controller Disabled,1: I2C Controller Enabled"
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newline
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bitfld.long 0x0 5. "STA,I2C START Control. Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control. In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag. When a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.. For.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data . Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS,I2C Status Register"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status. 2. If the BUSEN and PECEN are enabled the status of PECERR I2C_BUSSTS[3] is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been.."
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided . Note: The minimum value of I2C_CLKDIV is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit. When Enabled the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-Out Counter Disabled,1: Time-Out Counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4. When Enabled The time-out period is extend 4 times." "0: Time-Out Counter Input Clock Divided Disabled,1: Time-Out Counter Input Clock Divided Enabled"
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newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag. This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.. Note: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x17
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag. When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x8 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x8 10. "PECCLR,PEC Clear at Repeat Start. The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: The PEC calculation is cleared by 'Repeat Start'..,1: The PEC calculation is cleared by 'Repeat Start'.."
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newline
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bitfld.long 0x8 9. "TIDLE,Timer Check in Idle State. The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: The BUSTOUT is used to calculate the clock low..,1: The BUSTOUT is used to calculate the IDLE period.."
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bitfld.long 0x8 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception. This bit is set by software and cleared by hardware when the PEC is transferred or when a STOP condition or an Address Matched is received" "0: No PEC transfer,1: PEC transmission/reception is requested"
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newline
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bitfld.long 0x8 7. "BUSEN,BUS Enable Bit. Note: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function is Disabled,1: The system management function is Enable"
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bitfld.long 0x8 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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newline
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bitfld.long 0x8 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x8 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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newline
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bitfld.long 0x8 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled and the SUSCON will be.."
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bitfld.long 0x8 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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newline
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bitfld.long 0x8 1. "PECEN,Packet Error Checking Calculation Enable Bit" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x8 0. "ACKMEN,Acknowledge Control by Manual. In order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0xC "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0xC 5. "PECIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Indicates the byte count done interrupt is..,1: Indicates the byte count done interrupt is Enabled"
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bitfld.long 0xC 4. "TORSTEN,Time Out Reset Enable Bit" "0: Indicates the I2C state machine reset is Disable,1: Indicates the I2C state machine reset is Enable."
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newline
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bitfld.long 0xC 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Indicates the time extended interrupt is Disabled,1: Indicates the time extended interrupt is Enabled"
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bitfld.long 0xC 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: Indicates the SCLK low time-out interrupt is..,1: Indicates the SCLK low time-out interrupt is.."
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newline
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bitfld.long 0xC 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit. For Master it calculates the period from START to ACK. For Slave it calculates the period from START to STOP" "0: Indicates the cumulative clock low time-out..,1: Indicates the cumulative clock low time-out.."
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bitfld.long 0xC 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Indicates the bus clock low time-out detection..,1: Indicates the bus clock low time-out detection.."
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line.long 0x10 "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x10 6. "CLKTO,Clock Low Cumulate Time-out Status . Note: Software can write 1 to clear this bit." "0: Indicates that the cumulative clock low is no..,1: Indicates that the cumulative clock low time-out.."
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bitfld.long 0x10 5. "BUSTO,Bus Time-out Status . In bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.. Note: Software can write 1 to clear this bit." "0: Indicates that there is no any time-out or..,1: Indicates that a time-out or external clock.."
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newline
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bitfld.long 0x10 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x10 3. "ALERT,SMBus Alert Status . Note: 1. The SMALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: Indicates SMALERT pin state is low.. No SMBALERT..,1: Indicates SMALERT pin state is high.. Indicates.."
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newline
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bitfld.long 0x10 2. "PECERR,PEC Error in Reception . Note: Software can write 1 to clear this bit." "0: Indicates the PEC value equal the received PEC..,1: Indicates the PEC value doesn't match the.."
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bitfld.long 0x10 1. "BCDONE,Byte Count Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: Indicates the transmission/ receive is not..,1: Indicates the transmission/ receive is finished.."
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newline
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bitfld.long 0x10 0. "BUSY,Bus Busy. Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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line.long 0x14 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.byte 0x14 0.--7. 1. "PLDSIZE,Transfer Byte Number. The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 255 Bytes. . Notice: The byte number counting includes address command code and data frame."
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rgroup.long 0x54++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x58++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value. Indicate the bus time-out value in bus is IDLE or SCLK low.. Note: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer. The field is used to configure the cumulative clock extension time-out.. Note: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set."
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tree.end
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tree "I2C1"
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base ad:0x40081000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL,I2C Control Register"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C Controller Disabled,1: I2C Controller Enabled"
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newline
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bitfld.long 0x0 5. "STA,I2C START Control. Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control. In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag. When a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.. For.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.byte 0x4 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data . Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS,I2C Status Register"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status. 2. If the BUSEN and PECEN are enabled the status of PECERR I2C_BUSSTS[3] is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been.."
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 0.--7. 1. "DIVIDER,I2C Clock Divided . Note: The minimum value of I2C_CLKDIV is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit. When Enabled the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-Out Counter Disabled,1: Time-Out Counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4. When Enabled The time-out period is extend 4 times." "0: Time-Out Counter Input Clock Divided Disabled,1: Time-Out Counter Input Clock Divided Enabled"
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newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag. This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.. Note: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.byte 0x8 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.byte 0xC 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.byte 0x10 1.--7. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.byte 0x14 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.byte 0x18 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.byte 0x1C 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.byte 0x20 1.--7. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x17
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag. When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x8 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x8 10. "PECCLR,PEC Clear at Repeat Start. The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation." "0: The PEC calculation is cleared by 'Repeat Start'..,1: The PEC calculation is cleared by 'Repeat Start'.."
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newline
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bitfld.long 0x8 9. "TIDLE,Timer Check in Idle State. The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: The BUSTOUT is used to calculate the clock low..,1: The BUSTOUT is used to calculate the IDLE period.."
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bitfld.long 0x8 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception. This bit is set by software and cleared by hardware when the PEC is transferred or when a STOP condition or an Address Matched is received" "0: No PEC transfer,1: PEC transmission/reception is requested"
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newline
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bitfld.long 0x8 7. "BUSEN,BUS Enable Bit. Note: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function is Disabled,1: The system management function is Enable"
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bitfld.long 0x8 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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newline
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bitfld.long 0x8 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x8 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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newline
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bitfld.long 0x8 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled and the SUSCON will be.."
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bitfld.long 0x8 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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newline
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bitfld.long 0x8 1. "PECEN,Packet Error Checking Calculation Enable Bit" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x8 0. "ACKMEN,Acknowledge Control by Manual. In order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0xC "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0xC 5. "PECIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Indicates the byte count done interrupt is..,1: Indicates the byte count done interrupt is Enabled"
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bitfld.long 0xC 4. "TORSTEN,Time Out Reset Enable Bit" "0: Indicates the I2C state machine reset is Disable,1: Indicates the I2C state machine reset is Enable."
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newline
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bitfld.long 0xC 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Indicates the time extended interrupt is Disabled,1: Indicates the time extended interrupt is Enabled"
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bitfld.long 0xC 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: Indicates the SCLK low time-out interrupt is..,1: Indicates the SCLK low time-out interrupt is.."
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newline
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bitfld.long 0xC 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit. For Master it calculates the period from START to ACK. For Slave it calculates the period from START to STOP" "0: Indicates the cumulative clock low time-out..,1: Indicates the cumulative clock low time-out.."
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bitfld.long 0xC 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Indicates the bus clock low time-out detection..,1: Indicates the bus clock low time-out detection.."
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line.long 0x10 "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x10 6. "CLKTO,Clock Low Cumulate Time-out Status . Note: Software can write 1 to clear this bit." "0: Indicates that the cumulative clock low is no..,1: Indicates that the cumulative clock low time-out.."
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bitfld.long 0x10 5. "BUSTO,Bus Time-out Status . In bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.. Note: Software can write 1 to clear this bit." "0: Indicates that there is no any time-out or..,1: Indicates that a time-out or external clock.."
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newline
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bitfld.long 0x10 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x10 3. "ALERT,SMBus Alert Status . Note: 1. The SMALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: Indicates SMALERT pin state is low.. No SMBALERT..,1: Indicates SMALERT pin state is high.. Indicates.."
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newline
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bitfld.long 0x10 2. "PECERR,PEC Error in Reception . Note: Software can write 1 to clear this bit." "0: Indicates the PEC value equal the received PEC..,1: Indicates the PEC value doesn't match the.."
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bitfld.long 0x10 1. "BCDONE,Byte Count Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: Indicates the transmission/ receive is not..,1: Indicates the transmission/ receive is finished.."
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newline
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bitfld.long 0x10 0. "BUSY,Bus Busy. Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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line.long 0x14 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.byte 0x14 0.--7. 1. "PLDSIZE,Transfer Byte Number. The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 255 Bytes. . Notice: The byte number counting includes address command code and data frame."
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rgroup.long 0x54++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x58++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value. Indicate the bus time-out value in bus is IDLE or SCLK low.. Note: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer. The field is used to configure the cumulative clock extension time-out.. Note: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set."
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tree.end
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tree.end
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tree "NMI (Non-maskable Interrupt)"
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base ad:0x40000300
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group.long 0x0++0x3
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line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
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bitfld.long 0x0 15. "UART1_INT,UART1 NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
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bitfld.long 0x0 14. "UART0_INT,UART0 NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
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newline
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bitfld.long 0x0 13. "EINT5,External Interrupt From PF.0 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PF.0 pin NMI source..,1: External interrupt from PF.0 pin NMI source.."
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bitfld.long 0x0 12. "EINT4,External Interrupt From PE.0 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PE.0 pin NMI source..,1: External interrupt from PE.0 pin NMI source.."
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newline
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bitfld.long 0x0 11. "EINT3,External Interrupt From PD.0 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PD.0 pin NMI source..,1: External interrupt from PD.0 pin NMI source.."
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bitfld.long 0x0 10. "EINT2,External Interrupt From PC.0 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PC.0 pin NMI source..,1: External interrupt from PC.0 pin NMI source.."
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newline
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bitfld.long 0x0 9. "EINT1,External Interrupt From PB.0 PD.3 or PE.5 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PB.0 PD.3 or PE.5 pin..,1: External interrupt from PB.0 PD.3 or PE.5 pin.."
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bitfld.long 0x0 8. "EINT0,External Interrupt From PA.0 PD.2 or PE.4 Pin NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from PA.0 PD.2 or PE.4 pin..,1: External interrupt from PA.0 PD.2 or PE.4 pin.."
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newline
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bitfld.long 0x0 7. "TAMPER_INT,TAMPER_INT NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Backup register tamper detected interrupt.NMI..,1: Backup register tamper detected interrupt.NMI.."
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bitfld.long 0x0 6. "RTC_INT,RTC NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
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newline
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock fail detected interrupt NMI source Disabled,1: Clock fail detected interrupt NMI source Enabled"
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bitfld.long 0x0 3. "SRAM_PERR,SRAM ParityCheck Error NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
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newline
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bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
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bitfld.long 0x0 1. "IRC_INT,IRC TRIM NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
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newline
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bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
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rgroup.long 0x4++0x3
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line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
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bitfld.long 0x0 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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bitfld.long 0x0 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
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newline
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bitfld.long 0x0 13. "EINT5,External Interrupt From PF.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PF.0 interrupt is..,1: External Interrupt from PF.0 interrupt is asserted"
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bitfld.long 0x0 12. "EINT4,External Interrupt From PE.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PE.0 interrupt is..,1: External Interrupt from PE.0 interrupt is asserted"
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newline
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bitfld.long 0x0 11. "EINT3,External Interrupt From PD.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PD.0 interrupt is..,1: External Interrupt from PD.0 interrupt is asserted"
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bitfld.long 0x0 10. "EINT2,External Interrupt From PC.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.0 interrupt is..,1: External Interrupt from PC.0 interrupt is asserted"
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newline
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bitfld.long 0x0 9. "EINT1,External Interrupt From PB.0 PD.3 or PE.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.0 PD.3 or PE.5..,1: External Interrupt from PB.0 PD.3 or PE.5.."
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bitfld.long 0x0 8. "EINT0,External Interrupt From PA.0 PD.2 or PE.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.0 PD.2 or PE.4..,1: External Interrupt from PA.0 PD.2 or PE.4.."
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newline
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bitfld.long 0x0 7. "TAMPER_INT,TAMPER_INT Interrupt Flag (Read Only)" "0: Backup register tamper detected interrupt is..,1: Backup register tamper detected interrupt is.."
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bitfld.long 0x0 6. "RTC_INT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
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newline
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bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
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bitfld.long 0x0 3. "SRAM_PERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
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newline
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bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
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bitfld.long 0x0 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
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newline
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bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
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tree.end
|
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tree "NVIC (Nested Vectored Interrupt Controller)"
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base ad:0xE000E100
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group.long 0x0++0x7
|
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line.long 0x0 "NVIC_ISER1,IRQ0 ~ IRQ63 Set-enable Control Register"
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hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit. The NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled. Write Operation:"
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line.long 0x4 "NVIC_ISER2,IRQ0 ~ IRQ63 Set-enable Control Register"
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hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit. The NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled. Write Operation:"
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group.long 0x80++0x7
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line.long 0x0 "NVIC_ICER1,IRQ0 ~ IRQ63 Clear-enable Control Register"
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hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit. The NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.. Write Operation:"
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line.long 0x4 "NVIC_ICER2,IRQ0 ~ IRQ63 Clear-enable Control Register"
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hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit. The NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.. Write Operation:"
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group.long 0x100++0x7
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line.long 0x0 "NVIC_ISPR1,IRQ0 ~ IRQ63 Set-pending Control Register"
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hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending . The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending. Write Operation:"
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line.long 0x4 "NVIC_ISPR2,IRQ0 ~ IRQ63 Set-pending Control Register"
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hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending . The NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending. Write Operation:"
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group.long 0x180++0x7
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line.long 0x0 "NVIC_ICPR1,IRQ0 ~ IRQ63 Clear-pending Control Register"
|
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hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending. The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts and show which interrupts are pending. Write Operation:"
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line.long 0x4 "NVIC_ICPR2,IRQ0 ~ IRQ63 Clear-pending Control Register"
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hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending. The NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts and show which interrupts are pending. Write Operation:"
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|
group.long 0x200++0x7
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|
line.long 0x0 "NVIC_IABR1,IRQ0 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags. The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
|
|
line.long 0x4 "NVIC_IABR2,IRQ0 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags. The NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active."
|
|
group.long 0x300++0x3
|
|
line.long 0x0 "NVIC_IPR1,IRQ0 ~ IRQ63 Priority Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
group.long 0x33C++0x3
|
|
line.long 0x0 "NVIC_IPR2,IRQ0 ~ IRQ63 Priority Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRI_4n_3,Priority of IRQ_4n+3. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRI_4n_2,Priority of IRQ_4n+2. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRI_4n_1,Priority of IRQ_4n+1. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRI_4n_0,Priority of IRQ_4n+0. '0' denotes the highest priority and '15' denotes the lowest priority"
|
|
group.long 0xE00++0x3
|
|
line.long 0x0 "STIR,Software Trigger Interrupt Registers"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID. Write to the STIR To Generate An Interrupt from Software. When the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR. Interrupt ID of the interrupt to trigger in the range 0-63. For example a value.."
|
|
tree.end
|
|
tree "OTG (USB On-The-Go)"
|
|
base ad:0x4004D000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "OTG_CTL,OTG Control Register"
|
|
bitfld.long 0x0 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function Disabled,1: OTG ID pin status change wake-up function Enabled"
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|
bitfld.long 0x0 4. "OTGEN,OTG Function Enable Bit. User needs to set this bit to enable OTG function while USB frame configured as OTG device. When USB frame not configured as OTG device this bit is must be low." "0: OTG function Disabled,1: OTG function Enabled"
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|
newline
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bitfld.long 0x0 2. "HNPREQEN,OTG HNP Request Enable Bit. When USB frame as A-device set this bit when A-device allows to process HNP protocol A-device changes role from Host to Peripheral. This bit will be cleared when OTG state changes from a_suspend to a_peripheral or.." "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
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|
bitfld.long 0x0 1. "BUSREQ,OTG Bus Request. If OTG A-device wants to do data transfers via USB bus setting this bit will drive VBUS high to detect USB device connection. If user won't use the bus any more clearing this bit will drop VBUS to save power. This bit will be.." "0: Not launch VBUS in OTG A-device or not request..,1: Launch VBUS in OTG A-device or request SRP in.."
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|
newline
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|
bitfld.long 0x0 0. "VBUSDROP,Drop VBUS Control. If user application running on this OTG A-device wants to conserve power set this bit to drop VBUS. BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device." "0: Not drop the VBUS,1: Drop the VBUS"
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|
line.long 0x4 "OTG_PHYCTL,OTG PHY Control Register"
|
|
bitfld.long 0x4 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity. The polarity of off-chip USB VBUS power switch valid signal depends on the selected component. A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch. Set this.." "0: The polarity of off-chip USB VBUS power switch..,1: The polarity of off-chip USB VBUS power switch.."
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|
bitfld.long 0x4 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity. The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need. A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch.. The polarity of enabling.." "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
|
|
newline
|
|
bitfld.long 0x4 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
|
|
bitfld.long 0x4 0. "OTGPHYEN,OTG PHY Enable Bit. When USB frame is configured as OTG-device user needs to set this bit before using OTG function. If device is not configured as OTG-device this bit is 'don't care'." "0: OTG PHY Disabled,1: OTG PHY Enabled"
|
|
line.long 0x8 "OTG_INTEN,OTG Interrupt Enable Register"
|
|
bitfld.long 0x8 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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|
bitfld.long 0x8 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit. If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high a interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
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|
bitfld.long 0x8 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit. If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high a interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x8 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit. If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high a interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
|
|
bitfld.long 0x8 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit. If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high a interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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|
bitfld.long 0x8 7. "HOSTIEN,Act As Host Interrupt Enable Bit. If this bit is set to 1 and the device is changed as a host a interrupt will be asserted." "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
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|
newline
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bitfld.long 0x8 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit. If this bit is set to 1 and the device is changed as a peripheral a interrupt will be asserted." "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
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|
bitfld.long 0x8 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit. If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high a interrupt will be asserted." "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
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|
bitfld.long 0x8 4. "GOIDLEIEN,OTG Device Goes to IDLE State Interrupt Enable Bit. Note: Going to idle state means going to a_idle or b_idle state. Please refer to A-device state diagram and B-device state diagram in OTG spec." "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x8 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x8 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x8 1. "VBEIEN,VBUS Error Interrupt Enable Bit. Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec." "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
|
|
bitfld.long 0x8 0. "ROLECHGIEN,Role (Host or Peripheral) Changed Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
line.long 0xC "OTG_INTSTS,OTG Interrupt Status Register"
|
|
bitfld.long 0xC 13. "SRPDETIF,SRP Detected Interrupt Status. Note: Write 1 to clear this status." "0: SRP not detected,1: SRP detected"
|
|
bitfld.long 0xC 11. "SECHGIF,SESSEND State Change Interrupt Status. Note: Write 1 to clear this flag." "0: SESSEND (OTG_STATUS[2]) not toggled,1: SESSEND (OTG_STATUS[2]) from high to low or from.."
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|
newline
|
|
bitfld.long 0xC 10. "VBCHGIF,VBUSVLD State Change Interrupt Status. Note: Write 1 to clear this status." "0: VBUSVLD (OTG_STATUS[5]) not toggled,1: VBUSVLD (OTG_STATUS[5]) from high to low or from.."
|
|
bitfld.long 0xC 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status. Note: Write 1 to clear this status." "0: AVLD (OTG_STATUS[4]) not toggled,1: AVLD (OTG_STATUS[4]) from high to low or low to.."
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|
newline
|
|
bitfld.long 0xC 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status. Note: Write 1 to clear this status." "0: BVLD (OTG_STATUS[3]) is not toggled,1: BVLD (OTG_STATUS[3]) from high to low or low to.."
|
|
bitfld.long 0xC 7. "HOSTIF,Act As Host Interrupt Status. Note: Write 1 to clear this flag." "0: This device does not act as a host,1: This device acts as a host"
|
|
newline
|
|
bitfld.long 0xC 6. "PDEVIF,Act As Peripheral Interrupt Status. Note: Write 1 to clear this flag." "0: This device does not act as a peripheral,1: This device acts as a peripheral"
|
|
bitfld.long 0xC 5. "IDCHGIF,ID State Change Interrupt Status. Note: Write 1 to clear this flag." "0: IDSTS (OTG_STATUS[1]) not toggled,1: IDSTS (OTG_STATUS[1]) from high to low or from.."
|
|
newline
|
|
bitfld.long 0xC 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status. Flag is set if the OTG device transfers from non-idle state to idle state. The OTG device will be neither a host nor a peripheral.. Note 1: Going to idle state means going to a_idle or b_idle state." "0: OTG device does not go back to idle state..,1: Going to idle state means going to a_idle or.."
|
|
bitfld.long 0xC 3. "HNPFIF,HNP Fail Interrupt Status. When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state this bit will be set when A-device does not connect after specified interval expires. . Note: Write 1 to clear this.." "0: A-device connects to B-device before specified..,1: A-device does not connect to B-device before.."
|
|
newline
|
|
bitfld.long 0xC 2. "SRPFIF,SRP Fail Interrupt Status. After initiating SRP an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum defined in OTG specification. This flag is set when the OTG B-device does not get VBUS high after this.." "0: OTG B-device gets VBUS high before this interval,1: OTG B-device does not get VBUS high before this.."
|
|
bitfld.long 0xC 1. "VBEIF,VBUS Error Interrupt Status. This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. . Note: Write 1 to clear this flag and recover from.." "0: OTG A-device drives VBUS over threshold voltage..,1: OTG A-device cannot drive VBUS over threshold.."
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|
newline
|
|
bitfld.long 0xC 0. "ROLECHGIF,OTG Role Change Interrupt Status. This flag is set when the role of an OTG device changed from a host to a peripheral or changed from a peripheral to a host while USB_ID pin status does not change.. Note: Write 1 to clear this flag." "0: OTG device role not changed,1: OTG device role changed"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "OTG_STATUS,OTG Status Register"
|
|
bitfld.long 0x0 5. "VBUSVLD,VBUS Valid Status. When VBUS is larger than 4.7V this bit will be set to 1." "0: VBUS is not valid,1: VBUS is valid"
|
|
bitfld.long 0x0 4. "AVLD,A-device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
|
|
newline
|
|
bitfld.long 0x0 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
|
|
bitfld.long 0x0 2. "SESSEND,Session End Status. When VBUS voltage is lower than 0.4V this bit will be set to 1. Session end means no meaningful power on VBUS." "0: Session is not end,1: Session is end"
|
|
newline
|
|
bitfld.long 0x0 1. "IDSTS,USB_ID Pin State of Mini-b/Micro-plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
|
|
bitfld.long 0x0 0. "OVERCUR,over Current Condition. The voltage on VBUS cannot reach a minimum VBUS valid threshold 4.4V minimum within a maximum time of 100ms after OTG A-device drives VBUS high." "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drives VBUS high in this.."
|
|
tree.end
|
|
tree "PDMA (Peripheral Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "CURSCAT"
|
|
base ad:0x400080C0
|
|
rgroup.long 0x0++0x2F
|
|
line.long 0x0 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x4 "PDMA_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x8 "PDMA_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0xC "PDMA_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x10 "PDMA_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x14 "PDMA_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x14 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x18 "PDMA_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
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hexmask.long 0x18 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
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line.long 0x1C "PDMA_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x1C 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
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line.long 0x20 "PDMA_CURSCAT8,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
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hexmask.long 0x20 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x24 "PDMA_CURSCAT9,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
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hexmask.long 0x24 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
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line.long 0x28 "PDMA_CURSCAT10,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
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|
hexmask.long 0x28 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x2C "PDMA_CURSCAT11,Current Scatter-gather Descriptor Table Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
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hexmask.long 0x2C 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
tree.end
|
|
tree "DSCT_CTL"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
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hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
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bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
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|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
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newline
|
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bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
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hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
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newline
|
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bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
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bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
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|
group.long 0x20++0x3
|
|
line.long 0x0 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PDMA_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PDMA_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PDMA_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "PDMA_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDMA_DSCT10_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDMA_DSCT11_CTL,Descriptor Table Control Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This field is used to set the source address increment size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates interrupt. . Note: If this bit set to '1' .." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
tree.end
|
|
tree "DSCT_DA"
|
|
base ad:0x40008008
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PDMA_DSCT5_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PDMA_DSCT6_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PDMA_DSCT7_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PDMA_DSCT8_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "PDMA_DSCT9_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDMA_DSCT10_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDMA_DSCT11_DA,Destination Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
tree.end
|
|
tree "DSCT_NEXT"
|
|
base ad:0x4000800C
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PDMA_DSCT0_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_DSCT1_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PDMA_DSCT2_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PDMA_DSCT3_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PDMA_DSCT4_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PDMA_DSCT5_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PDMA_DSCT6_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PDMA_DSCT7_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PDMA_DSCT8_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "PDMA_DSCT9_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDMA_DSCT10_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDMA_DSCT11_NEXT,First Scatter-gather Descriptor Table Offset Address of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long.word 0x0 2.--15. 1. "NEXT,PDMA Next Descriptor Table Offset Address Register. This field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA) if the next descriptor table is 0x2000_0100 then.."
|
|
tree.end
|
|
tree "DSCT_SA"
|
|
base ad:0x40008004
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PDMA_DSCT5_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PDMA_DSCT6_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PDMA_DSCT7_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PDMA_DSCT8_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "PDMA_DSCT9_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "PDMA_DSCT10_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "PDMA_DSCT11_SA,Source Address Register of PDMA Channel n. (M45xD/M45xC Only Support Channel 0~7)"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
tree.end
|
|
tree "PDMA"
|
|
base ad:0x40008000
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "PDMA_CHCTL,PDMA Channel Control Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "CHENn,PDMA Channel Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note1: If software stops corresponding PDMA transfer by setting PDMA_STOP register this bit will be cleared automatically.."
|
|
wgroup.long 0x404++0x7
|
|
line.long 0x0 "PDMA_STOP,PDMA Transfer Stop Control Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "STOPn,PDMA Transfer Stop Control Register (Write Only). User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).. By bit field:. By write 0xFFFF_FFFF to PDMA_STOP:. Setting all PDMA_STOP bit.."
|
|
line.long 0x4 "PDMA_SWREQ,PDMA Software Request Register"
|
|
hexmask.long.word 0x4 0.--11. 1. "SWREQn,PDMA Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or.."
|
|
rgroup.long 0x40C++0x3
|
|
line.long 0x0 "PDMA_TRGSTS,PDMA Channel Request Status Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "REQSTSn,PDMA Channel Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When PDMA controller finishes channel transfer this bit will be cleared automatically. . Note1:.."
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FPRISETn,PDMA Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level.. Write Operation:. Note1: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register.. Note2: FPRISET8~11 is M45xG/M45xE only."
|
|
wgroup.long 0x414++0x3
|
|
line.long 0x0 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "FPRICLRn,PDMA Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note1: User can read PDMA_PRISET register to know the channel priority.. Note2: FPRICLR8~11 is M45xG/M45xE only."
|
|
group.long 0x418++0x13
|
|
line.long 0x0 "PDMA_INTEN,PDMA Interrupt Enable Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "INTENn,PDMA Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt.. Note: INTEN8~11 is M45xG/M45xE only."
|
|
line.long 0x4 "PDMA_INTSTS,PDMA Interrupt Status Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "REQTOFn,Request Time-out Flag for Each Channel [N] (M45xD/M45xC Only). This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits."
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rbitfld.long 0x4 2. "TEIF,Table Empty Interrupt Flag (Read Only). This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode. User can read TEIF register to indicate which channel finished transfer." "0: PDMA channel transfer is not finished,1: PDMA channel transfer is finished and the.."
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|
newline
|
|
rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only). This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
|
|
bitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read-only). This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
|
|
line.long 0x8 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
|
|
hexmask.long.word 0x8 0.--11. 1. "ABTIFn,PDMA Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. . Note: ABTIF8~11 is M45xG/M45xE only."
|
|
line.long 0xC "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
|
|
hexmask.long.word 0xC 0.--11. 1. "TDIFn,Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits.. Note: TDIF8~11 is M45xG/M45xE only."
|
|
line.long 0x10 "PDMA_SCATSTS,PDMA Scatter-gather Table Empty Status Register"
|
|
hexmask.long.word 0x10 0.--11. 1. "TEMPTYFn,Scatter-gather Table Empty Flag Register. This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn (PDMA_SWREQ[11:0]) set to high or channel has finished transmission and the operation mode is Stop mode. User can write 1.."
|
|
rgroup.long 0x42C++0x3
|
|
line.long 0x0 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "TXACTFn,Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active.. Note: TXACTF8~11 is M45xG/M45xE only."
|
|
group.long 0x434++0x1B
|
|
line.long 0x0 "PDMA_TOUTEN,PDMA Time-out Enable Register (M45xD/M45xC Only)"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TOUTENn,PDMA Time-out Enable Bits"
|
|
line.long 0x4 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register (M45xD/M45xC Only)"
|
|
hexmask.long.byte 0x4 0.--7. 1. "TOUTIENn,PDMA Time-out Interrupt Enable Bits"
|
|
line.long 0x8 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address Register. In Scatter-Gather mode this is the base address for calculating the next link - list address. The next link address equation is . Note: Only useful in Scatter-Gather mode."
|
|
line.long 0xC "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register (M45xD/M45xC Only)"
|
|
hexmask.long.word 0xC 16.--31. 1. "TOC1,Time-out Counter for Channel 1. This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock."
|
|
hexmask.long.word 0xC 0.--15. 1. "TOC0,Time-out Counter for Channel 0. This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock."
|
|
line.long 0x10 "PDMA_TOC2_3,PDMA Time-out Counter Ch3 and Ch2 Register (M45xD/M45xC Only)"
|
|
hexmask.long.word 0x10 16.--31. 1. "TOC3,Time-out Period Counter for Channel 3. This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock."
|
|
hexmask.long.word 0x10 0.--15. 1. "TOC2,Time-out Period Counter for Channel 2. This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock."
|
|
line.long 0x14 "PDMA_TOC4_5,PDMA Time-out Counter Ch5 and Ch4 Register (M45xD/M45xC Only)"
|
|
hexmask.long.word 0x14 16.--31. 1. "TOC5,Time-out Period Counter for Channel 5. This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock."
|
|
hexmask.long.word 0x14 0.--15. 1. "TOC4,Time-out Period Counter for Channel 4. This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock."
|
|
line.long 0x18 "PDMA_TOC6_7,PDMA Time-out Counter Ch7 and Ch6 Register (M45xD/M45xC Only)"
|
|
hexmask.long.word 0x18 16.--31. 1. "TOC7,Time-out Period Counter for Channel 7. This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock."
|
|
hexmask.long.word 0x18 0.--15. 1. "TOC6,Time-out Period Counter for Channel 6. This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock."
|
|
group.long 0x480++0xB
|
|
line.long 0x0 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0"
|
|
hexmask.long.byte 0x0 24.--28. 1. "REQSRC3,Channel 3 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x0 16.--20. 1. "REQSRC2,Channel 2 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "REQSRC1,Channel 1 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x0 0.--4. 1. "REQSRC0,Channel 0 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.. Note 1: A peripheral can't assign to two channels at the same time.. Note 2: This field.."
|
|
line.long 0x4 "PDMA_REQSEL4_7,PDMA Request Source Select Register 1"
|
|
hexmask.long.byte 0x4 24.--28. 1. "REQSRC7,Channel 7 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x4 16.--20. 1. "REQSRC6,Channel 6 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "REQSRC5,Channel 5 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x4 0.--4. 1. "REQSRC4,Channel 4 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
line.long 0x8 "PDMA_REQSEL8_11,PDMA Request Source Select Register 2"
|
|
hexmask.long.byte 0x8 24.--28. 1. "REQSRC11,Channel 11 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x8 16.--20. 1. "REQSRC10,Channel 10 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--12. 1. "REQSRC9,Channel 9 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
hexmask.long.byte 0x8 0.--4. 1. "REQSRC8,Channel 8 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
|
|
tree.end
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Generator and Capture Timer)"
|
|
base ad:0x0
|
|
tree "PWM0"
|
|
base ad:0x40058000
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "PWM_CTL0,PWM Control Register 0"
|
|
bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). PWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
|
|
bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. . Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
|
|
newline
|
|
bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each PWM channel are..,1: Unify the PWM_CH2 and PWM_CH4 to output the same.."
|
|
hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: If IMMLDENn Enabled WINLDENn and CTRLDn will be invalid."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "WINLDENn,Window Load Enable Bit. Each bit n controls the corresponding PWM channel n."
|
|
hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-load. Each bit n controls the corresponding PWM channel n.. In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period."
|
|
line.long 0x4 "PWM_CTL1,PWM Control Register 1"
|
|
bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode. Each bit n controls the output mode of corresponding PWM channel n.. Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
|
|
hexmask.long.byte 0x4 16.--21. 1. "CNTMODEn,PWM Counter Mode. Each bit n controls the corresponding PWM channel n."
|
|
newline
|
|
hexmask.long.word 0x4 0.--11. 1. "CNTTYPEn,PWM Counter Behavior Type. Each bit n controls corresponding PWM channel n."
|
|
line.long 0x8 "PWM_SYNC,PWM Synchronization Register"
|
|
bitfld.long 0x8 24.--26. "PHSDIRn,PWM Phase Direction Control. Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after..,?,?,?,?,?,?"
|
|
bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the positive..,1: The inversed state of pin SYNC is passed to the.."
|
|
newline
|
|
bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count. The register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x8 16. "SNFLTEN,PWM0_SYNC_IN Noise Filter Enable Bit" "0: Noise filter of input pin PWM0_SYNC_IN Disabled,1: Noise filter of input pin PWM0_SYNC_IN Enabled"
|
|
hexmask.long.byte 0x8 8.--13. 1. "SINSRCn,PWM0_SYNC_IN Source Selection. Each bit n controls corresponding PWM channel n."
|
|
newline
|
|
bitfld.long 0x8 0.--2. "PHSENn,SYNC Phase Enable Bit. Each bit n controls corresponding PWM channel n." "0: PWM counter load PHS value Disabled,1: PWM counter load PHS value Enabled,?,?,?,?,?,?"
|
|
line.long 0xC "PWM_SWSYNC,PWM Software Control Synchronization Register"
|
|
bitfld.long 0xC 0.--2. "SWSYNCn,Software SYNC Function. Each bit n controls corresponding PWM channel n.. When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "PWM_CLKSRC,PWM Clock Source Register"
|
|
bitfld.long 0x10 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
bitfld.long 0x10 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
newline
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bitfld.long 0x10 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x14 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0"
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hexmask.long.word 0x14 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x18 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2"
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hexmask.long.word 0x18 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x1C "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4"
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hexmask.long.word 0x1C 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x20 "PWM_CNTEN,PWM Counter Enable Register"
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hexmask.long.byte 0x20 0.--5. 1. "CNTENn,PWM Counter Enable Bits. Each bit n controls the corresponding PWM channel n."
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line.long 0x24 "PWM_CNTCLR,PWM Clear Counter Register"
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hexmask.long.byte 0x24 0.--5. 1. "CNTCLRn,Clear PWM Counter Control Bit. It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n."
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line.long 0x28 "PWM_LOAD,PWM Load Register"
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hexmask.long.byte 0x28 0.--5. 1. "LOADn,Re-load PWM Comparator Register (CMPDAT) Control Bit. This bit is software write hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.. Write Operation:"
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group.long 0x30++0x17
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line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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line.long 0x4 "PWM_PERIOD1,PWM Period Register 1"
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hexmask.long.word 0x4 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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line.long 0x8 "PWM_PERIOD2,PWM Period Register 2"
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hexmask.long.word 0x8 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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line.long 0xC "PWM_PERIOD3,PWM Period Register 3"
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hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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line.long 0x10 "PWM_PERIOD4,PWM Period Register 4"
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hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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line.long 0x14 "PWM_PERIOD5,PWM Period Register 5"
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hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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group.long 0x70++0xB
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line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0"
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bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x0 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2"
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bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x4 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4"
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bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x8 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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newline
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hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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group.long 0x80++0xB
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line.long 0x0 "PWM_PHS0_1,PWM Counter Phase Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x4 "PWM_PHS2_3,PWM Counter Phase Register 2"
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hexmask.long.word 0x4 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x8 "PWM_PHS4_5,PWM Counter Phase Register 4"
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hexmask.long.word 0x8 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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rgroup.long 0x90++0x17
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line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x4 "PWM_CNT1,PWM Counter Register 1"
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bitfld.long 0x4 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x4 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x8 "PWM_CNT2,PWM Counter Register 2"
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bitfld.long 0x8 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x8 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0xC "PWM_CNT3,PWM Counter Register 3"
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bitfld.long 0xC 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0xC 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x10 "PWM_CNT4,PWM Counter Register 4"
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bitfld.long 0x10 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x10 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x14 "PWM_CNT5,PWM Counter Register 5"
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bitfld.long 0x14 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x14 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
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hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,PWM Period (Center) Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter count to (PERIODn+1).. Note: This bit is center point control when PWM counter operating in up-down counter.."
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hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,PWM Zero Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter count to zero."
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line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
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hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,PWM Compare Down Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter down count to CMPDAT.. Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4."
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hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,PWM Compare Up Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter up count to CMPDAT.. Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4."
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line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
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hexmask.long.byte 0x8 0.--5. 1. "MSKENn,PWM Mask Enable Bits. Each bit n controls the corresponding PWM channel n.. The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data."
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line.long 0xC "PWM_MSK,PWM Mask Data Register"
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hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,PWM Mask Data Bit. This data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n."
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line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select (M45xD/M45xC Only). For PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.. Brake..,1: Brake 1 pin source come from PWM1_BRAKE1.. Brake.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select (M45xD/M45xC Only). For PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.. Brake..,1: Brake 0 pin source come from PWM1_BRAKE0.. Brake.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count. The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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newline
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count. The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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newline
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0"
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bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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newline
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bitfld.long 0x18 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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newline
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bitfld.long 0x18 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2"
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bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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newline
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bitfld.long 0x1C 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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newline
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bitfld.long 0x1C 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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newline
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bitfld.long 0x1C 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4"
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bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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hexmask.long.byte 0x24 0.--5. 1. "PINVn,PWM PIN Polar Inverse Control Bits. The register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n."
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line.long 0x28 "PWM_POEN,PWM Output Enable Register"
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hexmask.long.byte 0x28 0.--5. 1. "POENn,PWM Pin Output Enable Bits. Each bit n controls the corresponding PWM channel n."
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wgroup.long 0xDC++0x3
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line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x0 8.--10. "BRKLTRGn,PWM Level Brake Software Trigger (Write Only) (Write Protect). Each bit n controls the corresponding PWM pair n.. Write 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. . Note: This register is write.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "BRKETRGn,PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only). Each bit n controls the corresponding PWM pair n.. Write 1 to this bit will trigger edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. . Note: This register.." "0,1,2,3,4,5,6,7"
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group.long 0xE0++0x2B
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line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,PWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4."
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bitfld.long 0x0 23. "IFAIEN4_5,PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,PWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4."
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bitfld.long 0x0 15. "IFAIEN2_3,PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 8.--13. 1. "PIENn,PWM Period Point Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note1: When up-down counter type period point means center point.. Note2: Odd channels will read always 0 at complementary mode."
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bitfld.long 0x0 7. "IFAIEN0_1,PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 0.--5. 1. "ZIENn,PWM Zero Point Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: Odd channels will read always 0 at complementary mode."
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line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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hexmask.long.byte 0x8 24.--29. 1. "CMPDIFn,PWM Compare Down Count Interrupt Flag. Each bit n controls the corresponding PWM channel n.. Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.. Note1: If CMPDAT equal to.."
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bitfld.long 0x8 23. "IFAIF4_5,PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag. Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.. Note1: If CMPDAT equal to.."
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bitfld.long 0x8 15. "IFAIF2_3,PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 8.--13. 1. "PIFn,PWM Period Point Interrupt Flag. This bit is set by hardware when PWM counter reaches PWM_PERIODn software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n."
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bitfld.long 0x8 7. "IFAIF0_1,PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 0.--5. 1. "ZIFn,PWM Zero Point Interrupt Flag. Each bit n controls the corresponding PWM channel n.. This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero."
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line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel5 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel5 level-detect brake state is released,1: When PWM channel5 level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel4 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel4 level-detect brake state is released,1: When PWM channel4 level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel3 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel3 level-detect brake state is released,1: When PWM channel3 level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel2 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel2 level-detect brake state is released,1: When PWM channel2 level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel1 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel1 level-detect brake state is released,1: When PWM channel1 level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel0 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel0 level-detect brake state is released,1: When PWM channel0 level-detect brake detects a.."
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bitfld.long 0xC 21. "BRKESTS5,PWM Channel5 Edge-detect Brake Status" "0: PWM channel5 edge-detect brake state is released,1: When PWM channel5 edge-detect brake detects a.."
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bitfld.long 0xC 20. "BRKESTS4,PWM Channel4 Edge-detect Brake Status" "0: PWM channel4 edge-detect brake state is released,1: When PWM channel4 edge-detect brake detects a.."
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bitfld.long 0xC 19. "BRKESTS3,PWM Channel3 Edge-detect Brake Status" "0: PWM channel3 edge-detect brake state is released,1: When PWM channel3 edge-detect brake detects a.."
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bitfld.long 0xC 18. "BRKESTS2,PWM Channel2 Edge-detect Brake Status" "0: PWM channel2 edge-detect brake state is released,1: When PWM channel2 edge-detect brake detects a.."
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bitfld.long 0xC 17. "BRKESTS1,PWM Channel1 Edge-detect Brake Status" "0: PWM channel1 edge-detect brake state is released,1: When PWM channel1 edge-detect brake detects a.."
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bitfld.long 0xC 16. "BRKESTS0,PWM Channel0 Edge-detect Brake Status" "0: PWM channel0 edge-detect brake state is released,1: When PWM channel0 edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel5 level-detect brake event do not..,1: When PWM channel5 level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel4 level-detect brake event do not..,1: When PWM channel4 level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel3 level-detect brake event do not..,1: When PWM channel3 level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel2 level-detect brake event do not..,1: When PWM channel2 level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel1 level-detect brake event do not..,1: When PWM channel1 level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel0 level-detect brake event do not..,1: When PWM channel0 level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel5 edge-detect brake event do not..,1: When PWM channel5 edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel4 edge-detect brake event do not..,1: When PWM channel4 edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel3 edge-detect brake event do not..,1: When PWM channel3 edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel2 edge-detect brake event do not..,1: When PWM channel2 edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel1 edge-detect brake event do not..,1: When PWM channel1 edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel0 edge-detect brake event do not..,1: When PWM channel0 edge-detect brake event.."
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line.long 0x10 "PWM_IFA,PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x10 23. "IFAEN4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH4 and PWM_CH5 interrupt flag accumulator..,1: PWM_CH4 and PWM_CH5 interrupt flag accumulator.."
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bitfld.long 0x10 20.--22. "IFSEL4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 4,1: CNT equal to PERIOD in channel 4,?,?,?,?,?,?"
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hexmask.long.byte 0x10 16.--19. 1. "IFCNT4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. . IFAIF4_5 (PWM_INTSTS0[23]) will be set in.."
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bitfld.long 0x10 15. "IFAEN2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH2 and PWM_CH3 interrupt flag accumulator..,1: PWM_CH2 and PWM_CH3 interrupt flag accumulator.."
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bitfld.long 0x10 12.--14. "IFSEL2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 2,1: CNT equal to PERIOD in channel 2,?,?,?,?,?,?"
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hexmask.long.byte 0x10 8.--11. 1. "IFCNT2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. . IFAIF2_3 (PWM_INTSTS0[15]) will be set in.."
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bitfld.long 0x10 7. "IFAEN0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH0 and PWM_CH1 interrupt flag accumulator..,1: PWM_CH0 and PWM_CH1 interrupt flag accumulator.."
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bitfld.long 0x10 4.--6. "IFSEL0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 0,1: CNT equal to PERIOD in channel 0,?,?,?,?,?,?"
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hexmask.long.byte 0x10 0.--3. 1. "IFCNT0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. . IFAIF0_1 (PWM_INTSTS0[7]) will be set in.."
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line.long 0x14 "PWM_DACTRGEN,PWM Trigger DAC Enable Register"
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hexmask.long.byte 0x14 24.--29. 1. "CDTRGEn,PWM Compare Down Count Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to1. Each bit n controls the corresponding PWM channel n.. Note1: This bit should keep at 0 when PWM.."
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hexmask.long.byte 0x14 16.--21. 1. "CUTRGEn,PWM Compare Up Count Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to1. Each bit n controls the corresponding PWM channel n.. Note1: This bit should keep at 0 when PWM.."
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hexmask.long.byte 0x14 8.--13. 1. "PTEn,PWM Period Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to1. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x14 0.--5. 1. "ZTEn,PWM Zero Point Trigger DAC Enable Bit. PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. Each bit n controls the corresponding PWM channel n."
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line.long 0x18 "PWM_EADCTS0,PWM Trigger EADC Source Select Register 0"
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bitfld.long 0x18 31. "TRGEN3,PWM_CH3 Trigger EADC Enable Bit" "0: PWM_CH3 Trigger EADC Disabled,1: PWM_CH3 Trigger EADC Enabled"
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hexmask.long.byte 0x18 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x18 23. "TRGEN2,PWM_CH2 Trigger EADC Enable Bit" "0: PWM_CH2 Trigger EADC Disabled,1: PWM_CH2 Trigger EADC Enabled"
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hexmask.long.byte 0x18 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x18 15. "TRGEN1,PWM_CH1 Trigger EADC Enable Bit" "0: PWM_CH1 Trigger EADC Disabled,1: PWM_CH1 Trigger EADC Enabled"
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hexmask.long.byte 0x18 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x18 7. "TRGEN0,PWM_CH0 Trigger EADC Enable Bit" "0: PWM_CH0 Trigger EADC Disabled,1: PWM_CH0 Trigger EADC Enabled"
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hexmask.long.byte 0x18 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger EADC Source Select"
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line.long 0x1C "PWM_EADCTS1,PWM Trigger EADC Source Select Register 1"
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bitfld.long 0x1C 15. "TRGEN5,PWM_CH5 Trigger EADC Enable Bit" "0: PWM_CH5 Trigger EADC Disabled,1: PWM_CH5 Trigger EADC Enabled"
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hexmask.long.byte 0x1C 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x1C 7. "TRGEN4,PWM_CH4 Trigger EADC Enable Bit" "0: PWM_CH4 Trigger EADC Disabled,1: PWM_CH4 Trigger EADC Enabled"
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hexmask.long.byte 0x1C 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger EADC Source Select"
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line.long 0x20 "PWM_FTCMPDAT0_1,PWM Free Trigger Compare Register 0"
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hexmask.long.word 0x20 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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line.long 0x24 "PWM_FTCMPDAT2_3,PWM Free Trigger Compare Register 2"
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hexmask.long.word 0x24 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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line.long 0x28 "PWM_FTCMPDAT4_5,PWM Free Trigger Compare Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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group.long 0x110++0x3
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line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
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hexmask.long.byte 0x0 0.--5. 1. "SSENn,PWM Synchronous Start Function Enable Bits. When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.."
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|
wgroup.long 0x114++0x3
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|
line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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|
bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable Bit (Write Only). PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.. Writing this bit to 1 will also set the counter.." "0,1"
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|
group.long 0x120++0x3
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|
line.long 0x0 "PWM_STATUS,PWM Status Register"
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|
bitfld.long 0x0 24. "DACTRGF,DAC Start of Conversion Flag" "0: Indicates no DAC start of conversion trigger..,1: Indicates an DAC start of conversion trigger.."
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hexmask.long.byte 0x0 16.--21. 1. "ADCTRGFn,EADC Start of Conversion Flag. Each bit n controls the corresponding PWM channel n."
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|
newline
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bitfld.long 0x0 8.--10. "SYNCINFn,Input Synchronization Latched Flag. Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software..,?,?,?,?,?,?"
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hexmask.long.byte 0x0 0.--5. 1. "CNTMAXFn,Time-base Counter Equal to 0xFFFF Latched Flag. Each bit n controls the corresponding PWM channel n."
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group.long 0x200++0x7
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line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
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|
hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Bits. Each bit n controls the corresponding PWM channel n."
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line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
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hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Bits. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Bits. Each bit n controls the corresponding PWM channel n."
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newline
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|
hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Bits. Each bit n controls the corresponding PWM channel n."
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|
hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Bits. Each bit n controls the corresponding PWM channel n."
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|
rgroup.long 0x208++0x33
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|
line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
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hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only). This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.. Note: This bit will be cleared automatically.."
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hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only). This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.. Note: This bit will be cleared automatically.."
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line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
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|
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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|
line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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|
group.long 0x23C++0x3
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|
line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register"
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|
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT4/5,?,?"
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bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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|
newline
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|
bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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|
newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT2/3,?,?"
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bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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|
newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT0/1,?,?"
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bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0xB
|
|
line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
|
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hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
|
|
line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
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line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
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|
group.long 0x250++0x7
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line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,PWM Capture Falling Latch Interrupt Enable Bit. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CINTENR corresponding channel CAPFIEN must be disabled."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,PWM Capture Rising Latch Interrupt Enable Bit. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CINTENR corresponding channel CAPRIEN must be disabled."
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line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,PWM Capture Falling Latch Interrupt Flag. This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer.."
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hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,PWM Capture Rising Latch Interrupt Flag. This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer.."
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rgroup.long 0x304++0x2F
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line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0x4 "PWM_PBUF1,PWM PERIOD1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0x8 "PWM_PBUF2,PWM PERIOD2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0xC "PWM_PBUF3,PWM PERIOD3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0x10 "PWM_PBUF4,PWM PERIOD4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0x14 "PWM_PBUF5,PWM PERIOD5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
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line.long 0x18 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
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hexmask.long.word 0x18 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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line.long 0x1C "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
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hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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line.long 0x20 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
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hexmask.long.word 0x20 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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line.long 0x24 "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
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hexmask.long.word 0x24 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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line.long 0x28 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
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hexmask.long.word 0x28 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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line.long 0x2C "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
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hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
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rgroup.long 0x340++0xB
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line.long 0x0 "PWM_FTCBUF0_1,PWM FTCMPDAT0_1 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
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line.long 0x4 "PWM_FTCBUF2_3,PWM FTCMPDAT2_3 Buffer"
|
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hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
|
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line.long 0x8 "PWM_FTCBUF4_5,PWM FTCMPDAT4_5 Buffer"
|
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hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
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group.long 0x34C++0x3
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line.long 0x0 "PWM_FTCI,PWM FTCMPDAT Indicator Register"
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bitfld.long 0x0 8.--10. "FTCMDn,PWM FTCMPDAT Down Indicator" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "FTCMUn,PWM FTCMPDAT Up Indicator" "0,1,2,3,4,5,6,7"
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tree.end
|
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tree "PWM1"
|
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base ad:0x40059000
|
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group.long 0x0++0x2B
|
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line.long 0x0 "PWM_CTL0,PWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). PWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects PWM output,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled PWM all counters will keep current value until exit ICE debug mode. . Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x0 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each PWM channel are..,1: Unify the PWM_CH2 and PWM_CH4 to output the same.."
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hexmask.long.byte 0x0 16.--21. 1. "IMMLDENn,Immediately Load Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: If IMMLDENn Enabled WINLDENn and CTRLDn will be invalid."
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "WINLDENn,Window Load Enable Bit. Each bit n controls the corresponding PWM channel n."
|
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hexmask.long.byte 0x0 0.--5. 1. "CTRLDn,Center Re-load. Each bit n controls the corresponding PWM channel n.. In up-down counter type PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period."
|
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line.long 0x4 "PWM_CTL1,PWM Control Register 1"
|
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bitfld.long 0x4 24.--26. "OUTMODEn,PWM Output Mode. Each bit n controls the output mode of corresponding PWM channel n.. Note: When operating in group function these bits must all set to the same mode." "0: PWM independent mode,1: PWM complementary mode,?,?,?,?,?,?"
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hexmask.long.byte 0x4 16.--21. 1. "CNTMODEn,PWM Counter Mode. Each bit n controls the corresponding PWM channel n."
|
|
newline
|
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hexmask.long.word 0x4 0.--11. 1. "CNTTYPEn,PWM Counter Behavior Type. Each bit n controls corresponding PWM channel n."
|
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line.long 0x8 "PWM_SYNC,PWM Synchronization Register"
|
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bitfld.long 0x8 24.--26. "PHSDIRn,PWM Phase Direction Control. Each bit n controls corresponding PWM channel n." "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after..,?,?,?,?,?,?"
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bitfld.long 0x8 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the positive..,1: The inversed state of pin SYNC is passed to the.."
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|
newline
|
|
bitfld.long 0x8 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count. The register bits control the counter number of edge detector." "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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|
newline
|
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bitfld.long 0x8 16. "SNFLTEN,PWM0_SYNC_IN Noise Filter Enable Bit" "0: Noise filter of input pin PWM0_SYNC_IN Disabled,1: Noise filter of input pin PWM0_SYNC_IN Enabled"
|
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hexmask.long.byte 0x8 8.--13. 1. "SINSRCn,PWM0_SYNC_IN Source Selection. Each bit n controls corresponding PWM channel n."
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newline
|
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bitfld.long 0x8 0.--2. "PHSENn,SYNC Phase Enable Bit. Each bit n controls corresponding PWM channel n." "0: PWM counter load PHS value Disabled,1: PWM counter load PHS value Enabled,?,?,?,?,?,?"
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line.long 0xC "PWM_SWSYNC,PWM Software Control Synchronization Register"
|
|
bitfld.long 0xC 0.--2. "SWSYNCn,Software SYNC Function. Each bit n controls corresponding PWM channel n.. When SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit." "0,1,2,3,4,5,6,7"
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line.long 0x10 "PWM_CLKSRC,PWM Clock Source Register"
|
|
bitfld.long 0x10 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
bitfld.long 0x10 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x10 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,?,?,?,?,?,?"
|
|
line.long 0x14 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0"
|
|
hexmask.long.word 0x14 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x18 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2"
|
|
hexmask.long.word 0x18 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
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line.long 0x1C "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4"
|
|
hexmask.long.word 0x1C 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale . The clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1)."
|
|
line.long 0x20 "PWM_CNTEN,PWM Counter Enable Register"
|
|
hexmask.long.byte 0x20 0.--5. 1. "CNTENn,PWM Counter Enable Bits. Each bit n controls the corresponding PWM channel n."
|
|
line.long 0x24 "PWM_CNTCLR,PWM Clear Counter Register"
|
|
hexmask.long.byte 0x24 0.--5. 1. "CNTCLRn,Clear PWM Counter Control Bit. It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n."
|
|
line.long 0x28 "PWM_LOAD,PWM Load Register"
|
|
hexmask.long.byte 0x28 0.--5. 1. "LOADn,Re-load PWM Comparator Register (CMPDAT) Control Bit. This bit is software write hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.. Write Operation:"
|
|
group.long 0x30++0x17
|
|
line.long 0x0 "PWM_PERIOD0,PWM Period Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
line.long 0x4 "PWM_PERIOD1,PWM Period Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
line.long 0x8 "PWM_PERIOD2,PWM Period Register 2"
|
|
hexmask.long.word 0x8 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
line.long 0xC "PWM_PERIOD3,PWM Period Register 3"
|
|
hexmask.long.word 0xC 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
line.long 0x10 "PWM_PERIOD4,PWM Period Register 4"
|
|
hexmask.long.word 0x10 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
line.long 0x14 "PWM_PERIOD5,PWM Period Register 5"
|
|
hexmask.long.word 0x14 0.--15. 1. "PERIOD,PWM Period Register. Up-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD."
|
|
group.long 0x50++0x17
|
|
line.long 0x0 "PWM_CMPDAT0,PWM Comparator Register 0"
|
|
hexmask.long.word 0x0 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
|
|
line.long 0x4 "PWM_CMPDAT1,PWM Comparator Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x8 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0xC "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x10 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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line.long 0x14 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMP,PWM Comparator Register. CMP use to compare with CNTR to generate PWM waveform interrupt and trigger EADC/DAC.. In independent mode CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.. In complementary mode CMPDAT0 2 4 denote as first.."
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group.long 0x70++0xB
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line.long 0x0 "PWM_DTCTL0_1,PWM Dead-time Control Register 0"
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bitfld.long 0x0 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x0 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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hexmask.long.word 0x0 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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line.long 0x4 "PWM_DTCTL2_3,PWM Dead-time Control Register 2"
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bitfld.long 0x4 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x4 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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hexmask.long.word 0x4 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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line.long 0x8 "PWM_DTCTL4_5,PWM Dead-time Control Register 4"
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bitfld.long 0x8 24. "DTCKSEL,Dead-time Clock Select (Write Protect) (M45xD/M45xC Only). Note: This register is write protected. Refer to REGWRPROT register." "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x8 16. "DTEN,Dead-time Insertion for PWM Pair (PWM_CH0 PWM_CH1) (PWM_CH2 PWM_CH3) (PWM_CH4 PWM_CH5) Enable Bit (Write Protect). Dead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive the outputs.." "0: Dead-time insertion on the pin pair Disabled,1: Dead-time insertion on the pin pair Enabled"
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hexmask.long.word 0x8 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect). The dead-time can be calculated from the following formula: . Note: This register is write protected. Refer to SYS_REGLCTL register."
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group.long 0x80++0xB
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line.long 0x0 "PWM_PHS0_1,PWM Counter Phase Register 0"
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hexmask.long.word 0x0 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x4 "PWM_PHS2_3,PWM Counter Phase Register 2"
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hexmask.long.word 0x4 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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line.long 0x8 "PWM_PHS4_5,PWM Counter Phase Register 4"
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hexmask.long.word 0x8 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits. PHS determines the PWM synchronous start phase value. These bits only use in synchronous function."
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rgroup.long 0x90++0x17
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line.long 0x0 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x0 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x0 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x4 "PWM_CNT1,PWM Counter Register 1"
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bitfld.long 0x4 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x4 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x8 "PWM_CNT2,PWM Counter Register 2"
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bitfld.long 0x8 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x8 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0xC "PWM_CNT3,PWM Counter Register 3"
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bitfld.long 0xC 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0xC 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x10 "PWM_CNT4,PWM Counter Register 4"
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bitfld.long 0x10 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x10 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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line.long 0x14 "PWM_CNT5,PWM Counter Register 5"
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bitfld.long 0x14 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x14 0.--15. 1. "CNT,PWM Data Register (Read Only). User can monitor CNTR to know the current value in 16-bit period counter."
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group.long 0xB0++0x2B
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line.long 0x0 "PWM_WGCTL0,PWM Generation Register 0"
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hexmask.long.word 0x0 16.--27. 1. "PRDPCTLn,PWM Period (Center) Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter count to (PERIODn+1).. Note: This bit is center point control when PWM counter operating in up-down counter.."
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hexmask.long.word 0x0 0.--11. 1. "ZPCTLn,PWM Zero Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter count to zero."
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line.long 0x4 "PWM_WGCTL1,PWM Generation Register 1"
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hexmask.long.word 0x4 16.--27. 1. "CMPDCTLn,PWM Compare Down Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter down count to CMPDAT.. Note: In complementary mode CMPDCTL1 3 5 use as another CMPDCTL for channel 0 2 4."
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hexmask.long.word 0x4 0.--11. 1. "CMPUCTLn,PWM Compare Up Point Control. Each bit n controls the corresponding PWM channel n.. PWM can control output level when PWM counter up count to CMPDAT.. Note: In complementary mode CMPUCTL1 3 5 use as another CMPUCTL for channel 0 2 4."
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line.long 0x8 "PWM_MSKEN,PWM Mask Enable Register"
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hexmask.long.byte 0x8 0.--5. 1. "MSKENn,PWM Mask Enable Bits. Each bit n controls the corresponding PWM channel n.. The PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data."
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line.long 0xC "PWM_MSK,PWM Mask Data Register"
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hexmask.long.byte 0xC 0.--5. 1. "MSKDATn,PWM Mask Data Bit. This data bit control the state of PWMn output pin if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n."
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line.long 0x10 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x10 24. "BK1SRC,Brake 1 Pin Source Select (M45xD/M45xC Only). For PWM0 setting:" "0: Brake 1 pin source come from PWM0_BRAKE1.. Brake..,1: Brake 1 pin source come from PWM1_BRAKE1.. Brake.."
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bitfld.long 0x10 16. "BK0SRC,Brake 0 Pin Source Select (M45xD/M45xC Only). For PWM0 setting:" "0: Brake 0 pin source come from PWM0_BRAKE0.. Brake..,1: Brake 0 pin source come from PWM1_BRAKE0.. Brake.."
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bitfld.long 0x10 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is passed.."
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bitfld.long 0x10 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count. The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x10 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is passed.."
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bitfld.long 0x10 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count. The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,?,?,?,?,?,?"
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bitfld.long 0x10 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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line.long 0x14 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x14 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x14 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x14 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x14 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection Disabled,1: Brake Function triggered by CSS detection Enabled"
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line.long 0x18 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0"
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bitfld.long 0x18 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x18 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x18 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x18 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x18 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x18 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x18 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x18 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x18 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x18 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x18 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x1C "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2"
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bitfld.long 0x1C 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x1C 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x1C 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x1C 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x1C 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x1C 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x1C 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x1C 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x1C 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x1C 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x1C 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x20 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4"
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bitfld.long 0x20 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM odd channel level-detect brake function not..,1: PWM odd channel output tri-state when..,?,?"
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bitfld.long 0x20 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM even channel level-detect brake function not..,1: PWM even channel output tri-state when..,?,?"
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bitfld.long 0x20 15. "SYSLBEN,System Fail As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x20 13. "BRKP1LEN,BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x20 12. "BRKP0LEN,BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x20 9. "CPO1LBEN,ACMP1_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x20 8. "CPO0LBEN,ACMP0_O Digital Output As Level-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x20 7. "SYSEBEN,System Fail As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x20 5. "BRKP1EEN,PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 4. "BRKP0EEN,PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled"
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bitfld.long 0x20 1. "CPO1EBEN,ACMP1_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x20 0. "CPO0EBEN,ACMP0_O Digital Output As Edge-detect Brake Source Enable Bit (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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line.long 0x24 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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hexmask.long.byte 0x24 0.--5. 1. "PINVn,PWM PIN Polar Inverse Control Bits. The register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n."
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line.long 0x28 "PWM_POEN,PWM Output Enable Register"
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hexmask.long.byte 0x28 0.--5. 1. "POENn,PWM Pin Output Enable Bits. Each bit n controls the corresponding PWM channel n."
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wgroup.long 0xDC++0x3
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line.long 0x0 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x0 8.--10. "BRKLTRGn,PWM Level Brake Software Trigger (Write Only) (Write Protect). Each bit n controls the corresponding PWM pair n.. Write 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register. . Note: This register is write.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "BRKETRGn,PWM Edge Brake Software Trigger (Write Only) (Write Protect) (M45xD/M45xC Only). Each bit n controls the corresponding PWM pair n.. Write 1 to this bit will trigger edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register. . Note: This register.." "0,1,2,3,4,5,6,7"
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group.long 0xE0++0x2B
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line.long 0x0 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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hexmask.long.byte 0x0 24.--29. 1. "CMPDIENn,PWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: In complementary mode CMPDIEN1 3 5 use as another CMPDIEN for channel 0 2 4."
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bitfld.long 0x0 23. "IFAIEN4_5,PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPUIENn,PWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: In complementary mode CMPUIEN1 3 5 use as another CMPUIEN for channel 0 2 4."
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bitfld.long 0x0 15. "IFAIEN2_3,PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 8.--13. 1. "PIENn,PWM Period Point Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note1: When up-down counter type period point means center point.. Note2: Odd channels will read always 0 at complementary mode."
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bitfld.long 0x0 7. "IFAIEN0_1,PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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hexmask.long.byte 0x0 0.--5. 1. "ZIENn,PWM Zero Point Interrupt Enable Bits. Each bit n controls the corresponding PWM channel n.. Note: Odd channels will read always 0 at complementary mode."
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line.long 0x4 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x4 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x4 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x4 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x4 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5 Enabled"
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bitfld.long 0x4 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3 Enabled"
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bitfld.long 0x4 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1 Enabled"
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line.long 0x8 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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hexmask.long.byte 0x8 24.--29. 1. "CMPDIFn,PWM Compare Down Count Interrupt Flag. Each bit n controls the corresponding PWM channel n.. Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.. Note1: If CMPDAT equal to.."
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bitfld.long 0x8 23. "IFAIF4_5,PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 16.--21. 1. "CMPUIFn,PWM Compare Up Count Interrupt Flag. Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.. Note1: If CMPDAT equal to.."
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bitfld.long 0x8 15. "IFAIF2_3,PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 8.--13. 1. "PIFn,PWM Period Point Interrupt Flag. This bit is set by hardware when PWM counter reaches PWM_PERIODn software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n."
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bitfld.long 0x8 7. "IFAIF0_1,PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag. Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register software can clear this bit by writing 1 to it." "0,1"
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hexmask.long.byte 0x8 0.--5. 1. "ZIFn,PWM Zero Point Interrupt Flag. Each bit n controls the corresponding PWM channel n.. This bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero."
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line.long 0xC "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0xC 29. "BRKLSTS5,PWM Channel5 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel5 level-detect brake state is released,1: When PWM channel5 level-detect brake detects a.."
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rbitfld.long 0xC 28. "BRKLSTS4,PWM Channel4 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel4 level-detect brake state is released,1: When PWM channel4 level-detect brake detects a.."
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rbitfld.long 0xC 27. "BRKLSTS3,PWM Channel3 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel3 level-detect brake state is released,1: When PWM channel3 level-detect brake detects a.."
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rbitfld.long 0xC 26. "BRKLSTS2,PWM Channel2 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel2 level-detect brake state is released,1: When PWM channel2 level-detect brake detects a.."
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rbitfld.long 0xC 25. "BRKLSTS1,PWM Channel1 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel1 level-detect brake state is released,1: When PWM channel1 level-detect brake detects a.."
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rbitfld.long 0xC 24. "BRKLSTS0,PWM Channel0 Level-detect Brake Status (Read Only). Note: This bit is read only and auto cleared by hardware. When enabled brake source return to high level PWM will release brake state until current PWM period finished. The PWM waveform will.." "0: PWM channel0 level-detect brake state is released,1: When PWM channel0 level-detect brake detects a.."
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bitfld.long 0xC 21. "BRKESTS5,PWM Channel5 Edge-detect Brake Status" "0: PWM channel5 edge-detect brake state is released,1: When PWM channel5 edge-detect brake detects a.."
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bitfld.long 0xC 20. "BRKESTS4,PWM Channel4 Edge-detect Brake Status" "0: PWM channel4 edge-detect brake state is released,1: When PWM channel4 edge-detect brake detects a.."
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bitfld.long 0xC 19. "BRKESTS3,PWM Channel3 Edge-detect Brake Status" "0: PWM channel3 edge-detect brake state is released,1: When PWM channel3 edge-detect brake detects a.."
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bitfld.long 0xC 18. "BRKESTS2,PWM Channel2 Edge-detect Brake Status" "0: PWM channel2 edge-detect brake state is released,1: When PWM channel2 edge-detect brake detects a.."
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bitfld.long 0xC 17. "BRKESTS1,PWM Channel1 Edge-detect Brake Status" "0: PWM channel1 edge-detect brake state is released,1: When PWM channel1 edge-detect brake detects a.."
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bitfld.long 0xC 16. "BRKESTS0,PWM Channel0 Edge-detect Brake Status" "0: PWM channel0 edge-detect brake state is released,1: When PWM channel0 edge-detect brake detects a.."
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bitfld.long 0xC 13. "BRKLIF5,PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel5 level-detect brake event do not..,1: When PWM channel5 level-detect brake event.."
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bitfld.long 0xC 12. "BRKLIF4,PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel4 level-detect brake event do not..,1: When PWM channel4 level-detect brake event.."
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bitfld.long 0xC 11. "BRKLIF3,PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel3 level-detect brake event do not..,1: When PWM channel3 level-detect brake event.."
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bitfld.long 0xC 10. "BRKLIF2,PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel2 level-detect brake event do not..,1: When PWM channel2 level-detect brake event.."
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bitfld.long 0xC 9. "BRKLIF1,PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel1 level-detect brake event do not..,1: When PWM channel1 level-detect brake event.."
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bitfld.long 0xC 8. "BRKLIF0,PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel0 level-detect brake event do not..,1: When PWM channel0 level-detect brake event.."
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bitfld.long 0xC 5. "BRKEIF5,PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel5 edge-detect brake event do not..,1: When PWM channel5 edge-detect brake event.."
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bitfld.long 0xC 4. "BRKEIF4,PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel4 edge-detect brake event do not..,1: When PWM channel4 edge-detect brake event.."
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bitfld.long 0xC 3. "BRKEIF3,PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel3 edge-detect brake event do not..,1: When PWM channel3 edge-detect brake event.."
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bitfld.long 0xC 2. "BRKEIF2,PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel2 edge-detect brake event do not..,1: When PWM channel2 edge-detect brake event.."
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bitfld.long 0xC 1. "BRKEIF1,PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel1 edge-detect brake event do not..,1: When PWM channel1 edge-detect brake event.."
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bitfld.long 0xC 0. "BRKEIF0,PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect). Note: This register is write protected. Refer to SYS_REGLCTL register." "0: PWM channel0 edge-detect brake event do not..,1: When PWM channel0 edge-detect brake event.."
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line.long 0x10 "PWM_IFA,PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x10 23. "IFAEN4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH4 and PWM_CH5 interrupt flag accumulator..,1: PWM_CH4 and PWM_CH5 interrupt flag accumulator.."
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bitfld.long 0x10 20.--22. "IFSEL4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 4,1: CNT equal to PERIOD in channel 4,?,?,?,?,?,?"
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hexmask.long.byte 0x10 16.--19. 1. "IFCNT4_5,PWM_CH4 and PWM_CH5 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. . IFAIF4_5 (PWM_INTSTS0[23]) will be set in.."
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bitfld.long 0x10 15. "IFAEN2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH2 and PWM_CH3 interrupt flag accumulator..,1: PWM_CH2 and PWM_CH3 interrupt flag accumulator.."
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bitfld.long 0x10 12.--14. "IFSEL2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 2,1: CNT equal to PERIOD in channel 2,?,?,?,?,?,?"
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hexmask.long.byte 0x10 8.--11. 1. "IFCNT2_3,PWM_CH2 and PWM_CH3 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. . IFAIF2_3 (PWM_INTSTS0[15]) will be set in.."
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bitfld.long 0x10 7. "IFAEN0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Enable Bit" "0: PWM_CH0 and PWM_CH1 interrupt flag accumulator..,1: PWM_CH0 and PWM_CH1 interrupt flag accumulator.."
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bitfld.long 0x10 4.--6. "IFSEL0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 0,1: CNT equal to PERIOD in channel 0,?,?,?,?,?,?"
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hexmask.long.byte 0x10 0.--3. 1. "IFCNT0_1,PWM_CH0 and PWM_CH1 Interrupt Flag Counter. The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. . IFAIF0_1 (PWM_INTSTS0[7]) will be set in.."
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line.long 0x14 "PWM_DACTRGEN,PWM Trigger DAC Enable Register"
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hexmask.long.byte 0x14 24.--29. 1. "CDTRGEn,PWM Compare Down Count Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter down count to CMPDAT if this bit is set to1. Each bit n controls the corresponding PWM channel n.. Note1: This bit should keep at 0 when PWM.."
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hexmask.long.byte 0x14 16.--21. 1. "CUTRGEn,PWM Compare Up Count Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter up count to CMPDAT if this bit is set to1. Each bit n controls the corresponding PWM channel n.. Note1: This bit should keep at 0 when PWM.."
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hexmask.long.byte 0x14 8.--13. 1. "PTEn,PWM Period Point Trigger DAC Enable Bit. PWM can trigger DAC to start action when PWM counter up count to (PERIODn+1) if this bit is set to1. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x14 0.--5. 1. "ZTEn,PWM Zero Point Trigger DAC Enable Bit. PWM can trigger EADC/DAC/DMA to start action when PWM counter down count to zero if this bit is set to1. Each bit n controls the corresponding PWM channel n."
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line.long 0x18 "PWM_EADCTS0,PWM Trigger EADC Source Select Register 0"
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bitfld.long 0x18 31. "TRGEN3,PWM_CH3 Trigger EADC Enable Bit" "0: PWM_CH3 Trigger EADC Disabled,1: PWM_CH3 Trigger EADC Enabled"
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hexmask.long.byte 0x18 24.--27. 1. "TRGSEL3,PWM_CH3 Trigger EADC Source Select"
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bitfld.long 0x18 23. "TRGEN2,PWM_CH2 Trigger EADC Enable Bit" "0: PWM_CH2 Trigger EADC Disabled,1: PWM_CH2 Trigger EADC Enabled"
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hexmask.long.byte 0x18 16.--19. 1. "TRGSEL2,PWM_CH2 Trigger EADC Source Select"
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bitfld.long 0x18 15. "TRGEN1,PWM_CH1 Trigger EADC Enable Bit" "0: PWM_CH1 Trigger EADC Disabled,1: PWM_CH1 Trigger EADC Enabled"
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hexmask.long.byte 0x18 8.--11. 1. "TRGSEL1,PWM_CH1 Trigger EADC Source Select"
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bitfld.long 0x18 7. "TRGEN0,PWM_CH0 Trigger EADC Enable Bit" "0: PWM_CH0 Trigger EADC Disabled,1: PWM_CH0 Trigger EADC Enabled"
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hexmask.long.byte 0x18 0.--3. 1. "TRGSEL0,PWM_CH0 Trigger EADC Source Select"
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line.long 0x1C "PWM_EADCTS1,PWM Trigger EADC Source Select Register 1"
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bitfld.long 0x1C 15. "TRGEN5,PWM_CH5 Trigger EADC Enable Bit" "0: PWM_CH5 Trigger EADC Disabled,1: PWM_CH5 Trigger EADC Enabled"
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hexmask.long.byte 0x1C 8.--11. 1. "TRGSEL5,PWM_CH5 Trigger EADC Source Select"
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bitfld.long 0x1C 7. "TRGEN4,PWM_CH4 Trigger EADC Enable Bit" "0: PWM_CH4 Trigger EADC Disabled,1: PWM_CH4 Trigger EADC Enabled"
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hexmask.long.byte 0x1C 0.--3. 1. "TRGSEL4,PWM_CH4 Trigger EADC Source Select"
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line.long 0x20 "PWM_FTCMPDAT0_1,PWM Free Trigger Compare Register 0"
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hexmask.long.word 0x20 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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line.long 0x24 "PWM_FTCMPDAT2_3,PWM Free Trigger Compare Register 2"
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hexmask.long.word 0x24 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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line.long 0x28 "PWM_FTCMPDAT4_5,PWM Free Trigger Compare Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register. FTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0 2 4 corresponding complementary pairs PWM_CH0and PWM_CH1 PWM_CH2 and PWM_CH3 PWM_CH4 and PWM_CH5."
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group.long 0x110++0x3
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line.long 0x0 "PWM_SSCTL,PWM Synchronous Start Control Register"
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hexmask.long.byte 0x0 0.--5. 1. "SSENn,PWM Synchronous Start Function Enable Bits. When synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM.."
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wgroup.long 0x114++0x3
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line.long 0x0 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,PWM Counter Synchronous Start Enable Bit (Write Only). PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.. Writing this bit to 1 will also set the counter.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "PWM_STATUS,PWM Status Register"
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bitfld.long 0x0 24. "DACTRGF,DAC Start of Conversion Flag" "0: Indicates no DAC start of conversion trigger..,1: Indicates an DAC start of conversion trigger.."
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hexmask.long.byte 0x0 16.--21. 1. "ADCTRGFn,EADC Start of Conversion Flag. Each bit n controls the corresponding PWM channel n."
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bitfld.long 0x0 8.--10. "SYNCINFn,Input Synchronization Latched Flag. Each bit n controls the corresponding PWM channel n." "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred software..,?,?,?,?,?,?"
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hexmask.long.byte 0x0 0.--5. 1. "CNTMAXFn,Time-base Counter Equal to 0xFFFF Latched Flag. Each bit n controls the corresponding PWM channel n."
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group.long 0x200++0x7
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line.long 0x0 "PWM_CAPINEN,PWM Capture Input Enable Register"
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hexmask.long.byte 0x0 0.--5. 1. "CAPINENn,Capture Input Enable Bits. Each bit n controls the corresponding PWM channel n."
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line.long 0x4 "PWM_CAPCTL,PWM Capture Control Register"
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hexmask.long.byte 0x4 24.--29. 1. "FCRLDENn,Falling Capture Reload Enable Bits. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x4 16.--21. 1. "RCRLDENn,Rising Capture Reload Enable Bits. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x4 8.--13. 1. "CAPINVn,Capture Inverter Enable Bits. Each bit n controls the corresponding PWM channel n."
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hexmask.long.byte 0x4 0.--5. 1. "CAPENn,Capture Function Enable Bits. Each bit n controls the corresponding PWM channel n."
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rgroup.long 0x208++0x33
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line.long 0x0 "PWM_CAPSTS,PWM Capture Status Register"
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hexmask.long.byte 0x0 8.--13. 1. "CFLIFOVn,Capture Falling Latch Interrupt Flag Overrun Status (Read Only). This flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.. Note: This bit will be cleared automatically.."
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hexmask.long.byte 0x0 0.--5. 1. "CRLIFOVn,Capture Rising Latch Interrupt Flag Overrun Status (Read Only). This flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.. Note: This bit will be cleared automatically.."
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line.long 0x4 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x8 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0xC "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x10 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x14 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
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line.long 0x18 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
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line.long 0x1C "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x20 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x24 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x28 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
|
|
hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x2C "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
|
|
hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only). When rising capture condition happened the PWM counter value will be saved in this register."
|
|
line.long 0x30 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
|
|
hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only). When falling capture condition happened the PWM counter value will be saved in this register."
|
|
group.long 0x23C++0x3
|
|
line.long 0x0 "PWM_PDMACTL,PWM PDMA Control Register"
|
|
bitfld.long 0x0 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
|
|
bitfld.long 0x0 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.."
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|
newline
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bitfld.long 0x0 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT4/5,?,?"
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|
bitfld.long 0x0 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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|
newline
|
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bitfld.long 0x0 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
|
|
bitfld.long 0x0 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.."
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|
newline
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bitfld.long 0x0 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT2/3,?,?"
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|
bitfld.long 0x0 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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|
newline
|
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bitfld.long 0x0 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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|
bitfld.long 0x0 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.."
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|
newline
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bitfld.long 0x0 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved.,1: PWM_RCAPDAT0/1,?,?"
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|
bitfld.long 0x0 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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|
rgroup.long 0x240++0xB
|
|
line.long 0x0 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
|
|
line.long 0x4 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
|
|
line.long 0x8 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only). This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA."
|
|
group.long 0x250++0x7
|
|
line.long 0x0 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
|
|
hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,PWM Capture Falling Latch Interrupt Enable Bit. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CINTENR corresponding channel CAPFIEN must be disabled."
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|
hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,PWM Capture Rising Latch Interrupt Enable Bit. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CINTENR corresponding channel CAPRIEN must be disabled."
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|
line.long 0x4 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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|
hexmask.long.byte 0x4 8.--13. 1. "CFLIFn,PWM Capture Falling Latch Interrupt Flag. This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer.."
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hexmask.long.byte 0x4 0.--5. 1. "CRLIFn,PWM Capture Rising Latch Interrupt Flag. This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.. Note: When Capture with PDMA operating CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer.."
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|
rgroup.long 0x304++0x2F
|
|
line.long 0x0 "PWM_PBUF0,PWM PERIOD0 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0x4 "PWM_PBUF1,PWM PERIOD1 Buffer"
|
|
hexmask.long.word 0x4 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0x8 "PWM_PBUF2,PWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x8 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0xC "PWM_PBUF3,PWM PERIOD3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0x10 "PWM_PBUF4,PWM PERIOD4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0x14 "PWM_PBUF5,PWM PERIOD5 Buffer"
|
|
hexmask.long.word 0x14 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only). Used as PERIOD active register."
|
|
line.long 0x18 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x18 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
line.long 0x1C "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
line.long 0x20 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x20 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
line.long 0x24 "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0x24 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
line.long 0x28 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x28 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
line.long 0x2C "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x2C 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only). Used as CMP active register."
|
|
rgroup.long 0x340++0xB
|
|
line.long 0x0 "PWM_FTCBUF0_1,PWM FTCMPDAT0_1 Buffer"
|
|
hexmask.long.word 0x0 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
|
|
line.long 0x4 "PWM_FTCBUF2_3,PWM FTCMPDAT2_3 Buffer"
|
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hexmask.long.word 0x4 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
|
|
line.long 0x8 "PWM_FTCBUF4_5,PWM FTCMPDAT4_5 Buffer"
|
|
hexmask.long.word 0x8 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only). Used as FTCMPDAT active register."
|
|
group.long 0x34C++0x3
|
|
line.long 0x0 "PWM_FTCI,PWM FTCMPDAT Indicator Register"
|
|
bitfld.long 0x0 8.--10. "FTCMDn,PWM FTCMPDAT Down Indicator" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--2. "FTCMUn,PWM FTCMPDAT Up Indicator" "0,1,2,3,4,5,6,7"
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|
tree.end
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40041000
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group.long 0x0++0x23
|
|
line.long 0x0 "RTC_INIT,RTC Initiation Register"
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|
hexmask.long 0x0 1.--31. 1. "INIT,RTC Initiation. When RTC block is powered on RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357 the RTC will be in un-reset state permanently.. The INIT.."
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rbitfld.long 0x0 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
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line.long 0x4 "RTC_RWEN,RTC Access Enable Register"
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rbitfld.long 0x4 16. "RWENF,RTC Register Access Enable Flag (Read Only). This bit will be set after RTC_RWEN[15:0] register is load a 0xA965 and be cleared automatically after 1024 RTC clock." "0: RTC register read/write Disabled,1: RTC register read/write Enabled"
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hexmask.long.word 0x4 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only). Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock."
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line.long 0x8 "RTC_FREQADJ,RTC Frequency Compensation Register"
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hexmask.long.byte 0x8 8.--11. 1. "INTEGER,Integer Part"
|
|
hexmask.long.byte 0x8 0.--5. 1. "FRACTION,Fraction Part. Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number."
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|
line.long 0xC "RTC_TIME,RTC Time Loading Register"
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bitfld.long 0xC 20.--21. "TENHR,10-hour Time Digit (0~2). When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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|
hexmask.long.byte 0xC 16.--19. 1. "HR,1-Hour Time Digit (0~9)"
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newline
|
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bitfld.long 0xC 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 8.--11. 1. "MIN,1-Min Time Digit (0~9)"
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newline
|
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bitfld.long 0xC 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 0.--3. 1. "SEC,1-Sec Time Digit (0~9)"
|
|
line.long 0x10 "RTC_CAL,RTC Calendar Loading Register"
|
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hexmask.long.byte 0x10 20.--23. 1. "TENYEAR,10-Year Calendar Digit (0~9)"
|
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hexmask.long.byte 0x10 16.--19. 1. "YEAR,1-Year Calendar Digit (0~9)"
|
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newline
|
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bitfld.long 0x10 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
|
|
hexmask.long.byte 0x10 8.--11. 1. "MON,1-Month Calendar Digit (0~9)"
|
|
newline
|
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bitfld.long 0x10 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
|
|
hexmask.long.byte 0x10 0.--3. 1. "DAY,1-Day Calendar Digit (0~9)"
|
|
line.long 0x14 "RTC_CLKFMT,RTC Time Scale Selection Register"
|
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bitfld.long 0x14 0. "_24HEN,24-hour / 12-hour Time Scale Selection. Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
|
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line.long 0x18 "RTC_WEEKDAY,RTC Day of the Week Register"
|
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bitfld.long 0x18 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,?,?,?,?,?,?"
|
|
line.long 0x1C "RTC_TALM,RTC Time Alarm Register"
|
|
bitfld.long 0x1C 20.--21. "TENHR,10-hour Time Digit of Alarm Setting (0~2). When RTC runs as 12-hour time scale mode the high bit of TENHR (RTC_TIME[21]) means AM/PM indication." "0,1,2,3"
|
|
hexmask.long.byte 0x1C 16.--19. 1. "HR,1-Hour Time Digit of Alarm Setting (0~9)"
|
|
newline
|
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bitfld.long 0x1C 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "MIN,1-Min Time Digit of Alarm Setting (0~9)"
|
|
newline
|
|
bitfld.long 0x1C 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "SEC,1-Sec Time Digit of Alarm Setting (0~9)"
|
|
line.long 0x20 "RTC_CALM,RTC Calendar Alarm Register"
|
|
hexmask.long.byte 0x20 20.--23. 1. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)"
|
|
hexmask.long.byte 0x20 16.--19. 1. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)"
|
|
newline
|
|
bitfld.long 0x20 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
hexmask.long.byte 0x20 8.--11. 1. "MON,1-Month Calendar Digit of Alarm Setting (0~9)"
|
|
newline
|
|
bitfld.long 0x20 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
|
|
hexmask.long.byte 0x20 0.--3. 1. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
|
|
bitfld.long 0x0 0. "LEAPYEAR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is leap year"
|
|
group.long 0x28++0x67
|
|
line.long 0x0 "RTC_INTEN,RTC Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "SNPDIEN,Snoop Detection Interrupt Enable Bit" "0: Snoop detected interrupt Disabled,1: Snoop detected interrupt Enabled"
|
|
bitfld.long 0x0 1. "TICKIEN,Time Tick Interrupt Enable Bit" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "ALMIEN,Alarm Interrupt Enable Bit" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
|
|
line.long 0x4 "RTC_INTSTS,RTC Interrupt Indicator Register"
|
|
bitfld.long 0x4 2. "SNPDIF,Snoop Detect Interrupt Flag. When tamper pin transition event is detected this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be waken up from Power-down mode if.." "0: No snoop event is detected,1: Snoop event is detected"
|
|
bitfld.long 0x4 1. "TICKIF,RTC Time Tick Interrupt Flag. When RTC time tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled.." "0: Tick condition does not occur,1: Tick condition occur"
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|
newline
|
|
bitfld.long 0x4 0. "ALMIF,RTC Alarm Interrupt Flag. When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is.." "0: Alarm condition is not matched,1: Alarm condition is matched"
|
|
line.long 0x8 "RTC_TICK,RTC Time Tick Register"
|
|
bitfld.long 0x8 0.--2. "TICK,Time Tick Register. These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. . Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active." "0: Time tick is 1 second,1: Time tick is 1/2 second,?,?,?,?,?,?"
|
|
line.long 0xC "RTC_TAMSK,RTC Time Alarm Mask Register"
|
|
bitfld.long 0xC 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
|
|
bitfld.long 0xC 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "?,1: Hour Time Digit of Alarm Setting"
|
|
newline
|
|
bitfld.long 0xC 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
|
|
bitfld.long 0xC 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "?,1: Min Time Digit of Alarm Setting"
|
|
newline
|
|
bitfld.long 0xC 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
|
|
bitfld.long 0xC 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "?,1: Sec Time Digit of Alarm Setting"
|
|
line.long 0x10 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
|
|
bitfld.long 0x10 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
|
|
bitfld.long 0x10 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "?,1: Year Calendar Digit of Alarm Setting"
|
|
newline
|
|
bitfld.long 0x10 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
bitfld.long 0x10 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "?,1: Month Calendar Digit of Alarm Setting"
|
|
newline
|
|
bitfld.long 0x10 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
|
|
bitfld.long 0x10 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "?,1: Day Calendar Digit of Alarm Setting"
|
|
line.long 0x14 "RTC_SPRCTL,RTC Spare Functional Control Register"
|
|
bitfld.long 0x14 7. "SPRRWRDY,SPR Register Ready. This bit indicates if the registers RTC_SPRCTL RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.. After user writing registers RTC_SPRCTL RTC_SPR0 ~ RTC_SPR19 read this bit to check if these registers are updated done is.." "0: RTC_SPRCTL RTC_SPR0 ~ RTC_SPR19 updating is in..,1: RTC_SPRCTL RTC_SPR0 ~ RTC_SPR19 are updated done.."
|
|
bitfld.long 0x14 5. "SPRCSTS,SPR Clear Flag . This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.. Writes 1 to clear this bit." "0: Spare register content is not cleared,1: Spare register content is cleared"
|
|
newline
|
|
bitfld.long 0x14 3. "SNPTYPE1,Snoop Detection Mode. This bit controls TAMPER pin is edge or level detection" "0: Level detection,1: Edge detection"
|
|
bitfld.long 0x14 2. "SPRRWEN,Spare Register Enable Bit. Note: When spare register is disabled RTC_SPR0 ~ RTC_SPR19 cannot be accessed." "0: Spare register is Disabled,1: Spare register is Enabled"
|
|
newline
|
|
bitfld.long 0x14 1. "SNPTYPE0,Snoop Detection Level. This bit controls TAMPER detect event is high level/rising edge or low level/falling edge." "0: Low level/Falling edge detection,1: High level/Rising edge detection."
|
|
bitfld.long 0x14 0. "SNPDEN,Snoop Detection Enable Bit" "0: TAMPER pin detection is Disabled,1: TAMPER pin detection is Enabled"
|
|
line.long 0x18 "RTC_SPR0,RTC Spare Register 0"
|
|
hexmask.long 0x18 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x1C "RTC_SPR1,RTC Spare Register 1"
|
|
hexmask.long 0x1C 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x20 "RTC_SPR2,RTC Spare Register 2"
|
|
hexmask.long 0x20 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x24 "RTC_SPR3,RTC Spare Register 3"
|
|
hexmask.long 0x24 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x28 "RTC_SPR4,RTC Spare Register 4"
|
|
hexmask.long 0x28 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x2C "RTC_SPR5,RTC Spare Register 5"
|
|
hexmask.long 0x2C 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x30 "RTC_SPR6,RTC Spare Register 6"
|
|
hexmask.long 0x30 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
|
|
line.long 0x34 "RTC_SPR7,RTC Spare Register 7"
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hexmask.long 0x34 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x38 "RTC_SPR8,RTC Spare Register 8"
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hexmask.long 0x38 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x3C "RTC_SPR9,RTC Spare Register 9"
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hexmask.long 0x3C 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x40 "RTC_SPR10,RTC Spare Register 10"
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hexmask.long 0x40 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x44 "RTC_SPR11,RTC Spare Register 11"
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hexmask.long 0x44 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x48 "RTC_SPR12,RTC Spare Register 12"
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hexmask.long 0x48 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x4C "RTC_SPR13,RTC Spare Register 13"
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hexmask.long 0x4C 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x50 "RTC_SPR14,RTC Spare Register 14"
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hexmask.long 0x50 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x54 "RTC_SPR15,RTC Spare Register 15"
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hexmask.long 0x54 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x58 "RTC_SPR16,RTC Spare Register 16"
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hexmask.long 0x58 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x5C "RTC_SPR17,RTC Spare Register 17"
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hexmask.long 0x5C 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x60 "RTC_SPR18,RTC Spare Register 18"
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hexmask.long 0x60 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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line.long 0x64 "RTC_SPR19,RTC Spare Register 19"
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hexmask.long 0x64 0.--31. 1. "SPARE,Spare Register. This field is used to store back-up information defined by user.. This field will be cleared by hardware automatically once a snooper pin event is detected.. Before storing back-up information in to RTC_SPRx register user should.."
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group.long 0x100++0xF
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line.long 0x0 "RTC_LXTCTL,RTC 32.768 KHz Oscillator Control Register"
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bitfld.long 0x0 1.--3. "GAIN,Oscillator Gain Option. User can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption." "0: L0 mode,1: L1 mode,?,?,?,?,?,?"
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bitfld.long 0x0 0. "LXTEN,Backup Domain 32K Oscillator Enable Bit. This bit controls 32 kHz oscillator on/off. User can set either LXTEN in RTC battery power domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator. If this bit is set 1 .." "0: Oscillator is Disabled,1: Oscillator is Enabled"
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line.long 0x4 "RTC_LXTOCTL,X32KO Pin Control Register"
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bitfld.long 0x4 3. "CTLSEL,IO Pin State Backup Selection. When low speed 32 kHz oscillator is disabled X32KO (PF.0) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KO (PF.0) pin I/O function is controlled by..,1: X32KO (PF.0) pin I/O function is controlled by.."
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bitfld.long 0x4 2. "DOUT,IO Output Data" "0: X32KO (PF.0) output low,1: X32KO (PF.0) output high"
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bitfld.long 0x4 0.--1. "OPMODE,GPF0 Operation Mode" "0: X32KO (PF.0) is input only mode without pull-up..,1: X32KO (PF.0) is output push pull mode,?,?"
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line.long 0x8 "RTC_LXTICTL,X32KI Pin Control Register"
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bitfld.long 0x8 3. "CTLSEL,IO Pin State Backup Selection. When low speed 32 kHz oscillator is disabled X32KI (PF.1) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT.." "0: X32KI (PF.1) pin I/O function is controlled by..,1: X32KI (PF.1) pin I/O function is controlled by.."
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bitfld.long 0x8 2. "DOUT,IO Output Data" "0: X32KI (PF.1) output low,1: X32KI (PF.1) output high"
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bitfld.long 0x8 0.--1. "OPMODE,IO Operation Mode" "0: X32KI (PF.1) is input only mode without pull-up..,1: X32KI (PF.1) is output push pull mode,?,?"
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line.long 0xC "RTC_TAMPCTL,TAMPER Pin Control Register"
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bitfld.long 0xC 3. "CTLSEL,IO Pin State Backup Selection. When tamper function is disabled TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL.." "0: TAMPER (PF.2) I/O function is controlled by GPIO..,1: TAMPER (PF.2) I/O function is controlled by VBAT.."
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bitfld.long 0xC 2. "DOUT,IO Output Data" "0: TAMPER (PF.2) output low,1: TAMPER (PF.2) output high"
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bitfld.long 0xC 0.--1. "OPMODE,IO Operation Mode" "0: TAMPER (PF.2) is input only mode without pull-up..,1: TAMPER (PF.2) is output push pull mode,?,?"
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tree.end
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tree "SC (Smart Card Host Interface)"
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base ad:0x40090000
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group.long 0x0++0x1B
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line.long 0x0 "SC_DAT,SC Receiving/Transmit Holding Buffer Register."
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/ Transmit Holding Buffer . Write Operation:. By writing data to DAT the SC will send out an 8-bit data.. Note: If SCEN(SC_CTL[0]) is not enabled DAT cannot be programmed.. . Read Operation:. By reading DAT the SC will return an 8-bit.."
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line.long 0x4 "SC_CTL,SC Control Register."
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bitfld.long 0x4 31. "DBGOFF,ICE Debug Mode Acknowledge Enable Bit" "0: When DBGACK is high the internal counter will be..,1: No matter DBGACK is high or low the internal.."
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bitfld.long 0x4 30. "SYNC,SYNC Flag Indicator. Due to synchronization software should check this bit before writing a new value to RXRTY and TXRTY.. Note: This bit is read only." "0: synchronizing is completion user can write new..,1: Last value is synchronizing"
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bitfld.long 0x4 26. "CDLV,Card Detect Level . Note: Software must select card detect level before Smart Card engine enabled." "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin from.."
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bitfld.long 0x4 24.--25. "CDDBSEL,Card Detect De-bounce Selection. This field indicates the card detect de-bounce selection." "0: De-bounce sample card insert once per 384 (128 *..,1: De-bounce sample card insert once per 192 (64 *..,?,?"
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bitfld.long 0x4 23. "TXRTYEN,TX Error Retry Enable Bit. This bit enables transmitter retry function when parity error has occurred." "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x4 20.--22. "TXRTY,TX Error Retry Count Number. This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.. Note1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.. Note2: This field cannot be.." "?,1: The real retry number is TXRTY + 1,2: This field cannot be changed when TXRTYEN enabled,?,?,?,?,?"
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bitfld.long 0x4 19. "RXRTYEN,RX Error Retry Enable Bit. This bit enables receiver retry function when parity error has occurred.. Note: Software must fill in the RXRTY value before enabling this bit." "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x4 16.--18. "RXRTY,RX Error Retry Count Number. This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. Note1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.. Note2: This field cannot be.." "?,1: The real retry number is RXRTY + 1,2: This field cannot be changed when RXRTYEN enabled,?,?,?,?,?"
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bitfld.long 0x4 15. "NSB,Stop Bit Length. This field indicates the length of stop bit.. Note: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x4 13.--14. "TMRSEL,Timer Selection" "0: All internal timer function Disabled,1: Internal 24 bit timer Enabled. Software can..,?,?"
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hexmask.long.byte 0x4 8.--12. 1. "BGT,Block Guard Time (BGT). Note: The real block guard time is BGT + 1."
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bitfld.long 0x4 6.--7. "RXTRGLV,Rx Buffer Trigger Level . When the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled an interrupt will be generated)." "0: INTR_RDA Trigger Level with 1 Byte,1: INTR_RDA Trigger Level with 2 Bytes,?,?"
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bitfld.long 0x4 4.--5. "CONSEL,Convention Selection. Note: If AUTOCEN(SC_CTL[3]) enabled this fields are ignored." "0: Direct convention,1: Reserved.,?,?"
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bitfld.long 0x4 3. "AUTOCEN,Auto Convention Enable Bit" "0: Auto-convention Disabled,1: Auto-convention Enabled. When hardware receives.."
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bitfld.long 0x4 2. "TXOFF,TX Transition Disable Control" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x4 1. "RXOFF,RX Transition Disable Control. Note: If AUTOCEN (SC_CTL[3])is enabled these fields must be ignored." "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x4 0. "SCEN,SC Engine Enable Bit. Set this bit to 1 to enable SC operation. If this bit is cleared SC will force all transition to IDLE state." "0,1"
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line.long 0x8 "SC_ALTCTL,SC Alternate Control Register."
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rbitfld.long 0x8 15. "ACTSTS2,Internal Timer2 Active State (Read Only). This bit indicates the timer counter status of timer2." "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x8 14. "ACTSTS1,Internal Timer1 Active State (Read Only). This bit indicates the timer counter status of timer1." "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x8 13. "ACTSTS0,Internal Timer0 Active State (Read Only). This bit indicates the timer counter status of timer0." "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x8 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x8 11. "ADACEN,Auto Deactivation When Card Removal. Note: When the card is removed hardware will stop any process and then do deactivation sequence (if this bit is set). If this process completes hardware will generate an interrupt INITIF to CPU." "0: Auto deactivation Disabled when hardware..,1: Auto deactivation Enabled when hardware detected.."
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bitfld.long 0x8 8.--9. "INITSEL,Initial Timing Selection. This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).. Unit: SC clock. Activation: refer to SC Activation Sequence in Figure 6.144. Warm-reset: refer to Warm-Reset.." "0,1,2,3"
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bitfld.long 0x8 7. "CNTEN2,Internal Timer2 Start Enable Bit. This bit enables Timer 2 to start counting. Software can fill 0 to stop it and set 1 to reload and count.. Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit .." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 6. "CNTEN1,Internal Timer1 Start Enable Bit. This bit enables Timer 1 to start counting. Software can fill 0 to stop it and set 1 to reload and count.. Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]) so don't fill this bit .." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 5. "CNTEN0,Internal Timer0 Start Enable Bit. This bit enables Timer 0 to start counting. Software can fill 0 to stop it and set 1 to reload and count.. Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]). So don't fill this bit .." "0: Stops counting,1: Start counting"
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bitfld.long 0x8 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit. This bit enables SC controller to initiate the card by warm reset sequence. Note1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set.." "0: No effect,1: When the warm reset sequence completed"
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bitfld.long 0x8 3. "ACTEN,Activation Sequence Generator Enable Bit. This bit enables SC controller to initiate the card by activation sequence. Note1: When the activation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to.." "0: No effect,1: When the activation sequence completed"
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bitfld.long 0x8 2. "DACTEN,Deactivation Sequence Generator Enable Bit. This bit enables SC controller to initiate the card by deactivation sequence. Note1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be.." "0: No effect,1: When the deactivation sequence completed"
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bitfld.long 0x8 1. "RXRST,Rx Software Reset. When RXRST is set all the bytes in the receiver buffer and Rx internal state machine will be cleared.. Note: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the Rx internal state machine and pointers"
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bitfld.long 0x8 0. "TXRST,TX Software Reset. When TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.. Note: This bit will be auto cleared after reset is complete." "0: No effect,1: Reset the TX internal state machine and pointers"
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line.long 0xC "SC_EGT,SC Extend Guard Time Register."
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hexmask.long.byte 0xC 0.--7. 1. "EGT,Extended Guard Time. This field indicates the extended guard timer value.. Note: The counter is ETU base and the real extended guard time is EGT."
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line.long 0x10 "SC_RXTOUT,SC Receive Buffer Time-out Register."
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hexmask.long.word 0x10 0.--8. 1. "RFTM,SC Receiver FIFO Time-out (ETU Base). Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.. Note2: Filling all 0 to this field indicates to disable this function."
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line.long 0x14 "SC_ETUCTL,SC ETU Control Register."
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bitfld.long 0x14 15. "CMPEN,Compensation Mode Enable Bit. This bit enables clock compensation function. When this bit enabled hardware will alternate between n clock cycles and n-1 clock cycles where n is the value to be written into the ETURDIV ." "0: Compensation function Disabled,1: Compensation function Enabled"
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hexmask.long.word 0x14 0.--11. 1. "ETURDIV,ETU Rate Divider. The field indicates the clock rate divider.. The real ETU is ETURDIV + 1.. Note: Software can configure this field but this field must be greater than 0x004."
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line.long 0x18 "SC_INTEN,SC Interrupt Enable Control Register."
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bitfld.long 0x18 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit . This field is used for auto-convention error interrupt enable." "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x18 9. "RXTOIF,Receiver Buffer Time-out Interrupt Enable Bit . This field is used for receiver buffer time-out interrupt enable." "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x18 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x18 7. "CDIEN,Card Detect Interrupt Enable Bit. This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x18 6. "BGTIEN,Block Guard Time Interrupt Enable Bit. This field is used for block guard time interrupt enable." "0: Block guard time Disabled,1: Block guard time Enabled"
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bitfld.long 0x18 5. "TMR2IEN,Timer2 Interrupt Enable Bit. This field is used for TMR2 interrupt enable." "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x18 4. "TMR1IEN,Timer1 Interrupt Enable Bit. This field is used to enable the TMR1 interrupt." "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x18 3. "TMR0IEN,Timer0 Interrupt Enable Bit. This field is used to enable TMR0 interrupt enable." "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x18 2. "TERRIEN,Transfer Error Interrupt Enable Bit. This field is used for transfer error interrupt enable. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5]) parity error.." "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x18 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit. This field is used for transmit buffer empty interrupt enable." "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x18 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit. This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable." "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt Enabled"
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rgroup.long 0x1C++0x7
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line.long 0x0 "SC_INTSTS,SC Interrupt Status Register."
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bitfld.long 0x0 10. "ACERRIF,Auto Convention Error Interrupt Status Flag (Read Only). This field indicates auto convention sequence error. If the received TS at ATR state is neither 0x3B nor 0x3F this bit will be set.. Note: This bit is read only but it can be cleared by.." "0,1"
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bitfld.long 0x0 9. "RBTOIF,Receiver Buffer Time-out Interrupt Status Flag (Read Only). This field is used for receiver buffer time-out interrupt status flag.. Note: This field is the status flag of receiver buffer time-out state. If software wants to clear this bit .." "0,1"
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bitfld.long 0x0 8. "INITIF,Initial End Interrupt Status Flag (Read Only). This field is used for activation (ACTEN(SC_ALTCTL[3])) deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.. Note: This bit is read only but.." "0,1"
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bitfld.long 0x0 7. "CDIF,Card Detect Interrupt Status Flag (Read Only). This field is used for card detect interrupt status flag. The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).. Note: This field is the status flag of CINSERT(SC_STATUS[12]) or.." "0,1"
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bitfld.long 0x0 6. "BGTIF," "0,1"
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bitfld.long 0x0 5. "TMR2IF,Timer2 Interrupt Status Flag (Read Only). This field is used for TMR2 interrupt status flag.. Note: This bit is read only but it can be cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 4. "TMR1IF,Timer1 Interrupt Status Flag (Read Only). This field is used for TMR1 interrupt status flag.. Note: This bit is read only but it can be cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 3. "TMR0IF,Timer0 Interrupt Status Flag (Read Only). This field is used for TMR0 interrupt status flag.. Note: This bit is read only but it can be cleared by writing 1 to it." "0,1"
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bitfld.long 0x0 2. "TERRIF,Transfer Error Interrupt Status Flag (Read Only). This field is used for transfer error interrupt status flag. The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]) frame error FEF(SC_STATUS[5] .." "0,1"
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bitfld.long 0x0 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only). This field is used for transmit buffer empty interrupt status flag.. Note: This field is the status flag of transmit buffer empty state. If software wants to clear this bit software must.." "0,1"
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bitfld.long 0x0 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only). This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.. Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]). If.." "0,1"
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line.long 0x4 "SC_STATUS,SC Status Register."
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bitfld.long 0x4 31. "TXACT,Transmit in Active Status Flag (Read Only)" "0: This bit is cleared automatically when TX..,1: This bit is set by hardware when TX transfer is.."
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bitfld.long 0x4 30. "TXOVERR,Transmitter over Retry Error (Read Only). This bit is set by hardware when transmitter re-transmits over retry number limitation.. Note: This bit is read only but it can be cleared by writing 1 to it." "0,1"
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bitfld.long 0x4 29. "TXRERR,Transmitter Retry Error (Read Only). This bit is set by hardware when transmitter re-transmits.. Note1: This bit is read only but it can be cleared by writing 1 to it.. Note2 This bit is a flag and cannot generate any interrupt to CPU." "?,1: This bit is read only"
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bitfld.long 0x4 24.--25. "TXPOINT,Transmit Buffer Pointer Status Flag (Read Only). This field indicates the TX buffer pointer status flag. When CPU writes data into SC_DAT TXPOINT increases one. When one byte of TX Buffer is transferred to transmitter shift register TXPOINT.." "0,1,2,3"
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bitfld.long 0x4 23. "RXACT,Receiver in Active Status Flag (Read Only). This bit is set by hardware when RX transfer is in active.. This bit is cleared automatically when RX transfer is finished." "0,1"
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bitfld.long 0x4 22. "RXOVERR,Receiver over Retry Error (Read Only). This bit is set by hardware when RX transfer error retry over retry number limit.. Note1: This bit is read only but it can be cleared by writing 1 to it.. Note2: If CPU enables receiver retries function by.." "?,1: This bit is read only"
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bitfld.long 0x4 21. "RXRERR,Receiver Retry Error (Read Only). This bit is set by hardware when RX has any error and retries transfer.. Note1: This bit is read only but it can be cleared by writing 1 to it.. Note2 This bit is a flag and cannot generate any interrupt to CPU.." "?,1: This bit is read only"
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bitfld.long 0x4 16.--17. "RXPOINT,Receiver Buffer Pointer Status Flag (Read Only). This field indicates the RX buffer pointer status flag. When SC receives one byte from external device RXPOINT(SC_STATUS[17:16]) increases one. When one byte of RX buffer is read by CPU .." "0,1,2,3"
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bitfld.long 0x4 13. "CDPINSTS,Card Detect Status of SC_CD Pin Status (Read Only). This bit is the pin status flag of SC_CD" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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bitfld.long 0x4 12. "CINSERT,Card Detect Insert Status of SC_CD Pin (Read Only). This bit is set whenever card has been inserted.. Note1: This bit is read only but it can be cleared by writing '1' to it.. Note2: The card detect engine will start after SCEN (SC_CTL[0]) set." "0: No effect,1: This bit is read only"
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bitfld.long 0x4 11. "CREMOVE,Card Detect Removal Status of SC_CD Pin (Read Only). This bit is set whenever card has been removal.. Note1: This bit is read only but it can be cleared by writing '1' to it.. Note2: Card detect engine will start after SCEN (SC_CTL[0])set." "0: No effect,1: This bit is read only"
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bitfld.long 0x4 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only). This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4 otherwise is cleared by hardware." "0,1"
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bitfld.long 0x4 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only). This bit indicates TX buffer empty or not.. When the last byte of TX buffer has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into.." "0,1"
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bitfld.long 0x4 8. "TXOV,TX Overflow Error Interrupt Status Flag (Read Only). If TX buffer is full an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to '1' by hardware. . Note: This bit is read only but it can be cleared by writing 1 to it." "0,1"
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bitfld.long 0x4 6. "BEF,Receiver Break Error Status Flag (Read Only). This bit is set to logic 1 whenever the received data input (RX) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + data bits +.." "?,1: This bit is read only"
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bitfld.long 0x4 5. "FEF,Receiver Frame Error Status Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0). . Note1: This bit is.." "?,1: This bit is read only"
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bitfld.long 0x4 4. "PEF,Receiver Parity Error Status Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note1: This bit is read only but it can be cleared by writing 1 to it.. Note2: If CPU sets receiver.." "?,1: This bit is read only"
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bitfld.long 0x4 2. "RXFULL,Receiver Buffer Full Status Flag (Read Only). This bit indicates RX buffer full or not.. This bit is set when RX pointer is equal to 4 otherwise it is cleared by hardware." "0,1"
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bitfld.long 0x4 1. "RXEMPTY,Receiver Buffer Empty Status Flag(Read Only). This bit indicates RX buffer empty or not.. When the last byte of Rx buffer has been read by CPU hardware sets this bit high. It will be cleared when SC receives any new data." "0,1"
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bitfld.long 0x4 0. "RXOV,RX Overflow Error Status Flag (Read Only) . This bit is set when RX buffer overflow.. If the number of received bytes is greater than Rx Buffer size (4 bytes) this bit will be set.. Note: This bit is read only but it can be cleared by writing 1 to.." "0,1"
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group.long 0x24++0x13
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line.long 0x0 "SC_PINCTL,SC Pin Control State Register."
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bitfld.long 0x0 30. "SYNC,SYNC Flag Indicator. Due to synchronization software should check this bit when writing a new value to SC_PINCTL register.. Note: This bit is read only." "0: Synchronizing is completion user can write new..,1: Last value is synchronizing"
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bitfld.long 0x0 18. "RSTSTS,SCRST Pin Signals. This bit is the pin status of SC_RST. Note: When SC is operated at activation warm reset or deactivation mode this bit will be changed automatically. This bit is not allowed to program when SC is operated at these modes." "0: SC_RST pin is low,1: SC_RST pin is high"
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bitfld.long 0x0 17. "PWRSTS," "0: SC_PWR pin to low,1: SC_PWR pin to high"
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bitfld.long 0x0 16. "DATSTS," "0: The SC_DAT pin is low,1: The SC_DAT pin is high"
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bitfld.long 0x0 12. "SCDOSTS,SC Data Pin Output Status . This bit is the pin status of SCDATOUT . Note: When SC is operated at activation warm reset or deactivation mode this bit will be changed automatically. This bit is not allowed to program when SC is operated at these.." "0: SCDATOUT pin to low,1: SCDATOUT pin to high"
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bitfld.long 0x0 11. "PWRINV,SC_POW Pin Inverse. This bit is used for inverse the SC_POW pin.. There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]). PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for.." "0: SC_POW_ Pin is 0,1: SC_POW _Pin is 1"
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bitfld.long 0x0 9. "SCDOUT,SC Data Output Pin . This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.. Note: When SC is at activation warm reset or deactivation mode this bit will be changed automatically. So don't fill.." "0: Drive SCDATOUT pin to low,1: Drive SCDATOUT pin to high"
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bitfld.long 0x0 6. "CLKKEEP,SC Clock Enable Bit . Note: When operating in activation warm reset or deactivation mode this bit will be changed automatically. So don't fill this field when operating in these modes." "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x0 1. "SCRST,SC_RST Pin Signal. This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.. Write this field to drive SC_RST pin.. Note: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.. SC_RST pin status is low,1: Drive SC_RST pin to high.. SC_RST pin status is.."
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bitfld.long 0x0 0. "PWREN,SC_PWREN Pin Signal. Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.. Write this field to drive SC_PWR pin. Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage.." "0: SC_PWR pin status is low,1: SC_PWR pin status is high"
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line.long 0x4 "SC_TMRCTL0,SC Internal Timer Control Register 0."
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hexmask.long.byte 0x4 24.--27. 1. "OPMODE,Timer 0 Operation Mode Selection. This field indicates the internal 24-bit timer operation selection.. Refer to 6.14.5.4 for programming Timer0"
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hexmask.long.tbyte 0x4 0.--23. 1. "CNT,Timer 0 Counter Value (ETU Base). This field indicates the internal timer operation values."
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line.long 0x8 "SC_TMRCTL1,SC Internal Timer Control Register 1."
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hexmask.long.byte 0x8 24.--27. 1. "OPMODE,Timer 1 Operation Mode Selection. This field indicates the internal 8-bit timer operation selection.. Refer to 6.14.5.4 for programming Timer1"
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hexmask.long.byte 0x8 0.--7. 1. "CNT,Timer 1 Counter Value (ETU Base). This field indicates the internal timer operation values."
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line.long 0xC "SC_TMRCTL2,SC Internal Timer Control Register 2."
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hexmask.long.byte 0xC 24.--27. 1. "OPMODE,Timer 2 Operation Mode Selection. This field indicates the internal 8-bit timer operation selection. Refer to 6.14.5.4 for programming Timer2"
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hexmask.long.byte 0xC 0.--7. 1. "CNT,Timer 2 Counter Value (ETU Base). This field indicates the internal timer operation values."
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line.long 0x10 "SC_UARTCTL,SC UART Mode Control Register."
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bitfld.long 0x10 7. "OPE,Odd Parity Enable Bit. Note: This bit has effect only when PBOFF bit is '0'." "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or check.."
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bitfld.long 0x10 6. "PBOFF,Parity Bit Disable Control. Note: In smart card mode this field must be '0' (default setting is with parity bit)" "0: Parity bit is generated or checked between the..,1: Parity bit is not generated (transmitting data).."
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bitfld.long 0x10 4.--5. "WLS,Word Length Selection. Note: In smart card mode this WLS must be '00'" "0: Word length is 8 bits,1: Word length is 7 bits,?,?"
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bitfld.long 0x10 0. "UARTEN,UART Mode Enable Bit. Note3: When UART is enabled hardware will generate a reset to reset FIFO and internal state machine." "0: Smart Card mode,1: UART mode"
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rgroup.long 0x38++0x7
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line.long 0x0 "SC_TMRDAT0,SC Timer Current Data Register A."
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT0,Timer0 Current Data Value (Read Only). This field indicates the current count values of timer0."
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line.long 0x4 "SC_TMRDAT1_2,SC Timer Current Data Register B."
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hexmask.long.byte 0x4 8.--15. 1. "CNT2,Timer2 Current Data Value (Read Only). This field indicates the current count values of timer2."
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hexmask.long.byte 0x4 0.--7. 1. "CNT1,Timer1 Current Data Value (Read Only). This field indicates the current count values of timer1."
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tree.end
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tree "SCS (System Controller Space)"
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base ad:0xE000E000
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group.long 0x10++0xB
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line.long 0x0 "SYST_CTRL,SysTick Control and Status Register"
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bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag. Returns 1 if timer counted to 0 since last time this register was read.. COUNTFLAG is set by a count transition from 1 to 0.. COUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
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bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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line.long 0x4 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value. Value to load into the Current Value register when the counter reaches 0."
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line.long 0x8 "SYST_VAL,SysTick Current Value Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value. Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
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group.long 0xD04++0x3
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line.long 0x0 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit. Write Operation:. Note: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0." "0: No effect.. NMI exception is not pending,1: Changes NMI exception state to pending.. NMI.."
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bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit. Write Operation:. Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.. PendSV exception is not pending,1: Changes PendSV exception state to pending.."
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bitfld.long 0x0 27. "PENDSVRTC_CAL,PendSV Clear-pending Bit. Write Operation:. Note: This is a write only bit. To clear the PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit. Write Operation:" "0: No effect.. SysTick exception is not pending,1: Changes SysTick exception state to pending.."
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bitfld.long 0x0 25. "PENDSTRTC_CAL,SysTick Exception Clear-pending Bit. Write Operation:. Note: This is a write only bit. To clear the PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only). If set a pending exception will be serviced on exit from the debug halt state." "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Number of the Highest Pended Exception. Indicate the Exception Number of the Highest Priority Pending Enabled Exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.."
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bitfld.long 0x0 11. "RETTOBASE,Preempted Active Exceptions Indicator. Indicate whether There are Preempted Active Exceptions" "0: there are preempted active exceptions to execute,1: there are no active exceptions or the.."
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hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Number of the Current Active Exception"
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group.long 0xD0C++0x7
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line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key. When writing this register this field should be 0x05FA otherwise the write action will be unpredictable.. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
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bitfld.long 0x0 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x0 8.--10. "PRIGROUP,Interrupt Priority Grouping. This field determines the Split Of Group priority from subpriority " "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request. Writing This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested. This bit is write only and self-cleared as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit. Setting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions. This bit is write only and can only be written when the core is halted.. Note: It is the debugger's.." "0,1"
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line.long 0x4 "SCR,System Control Register"
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bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending. When an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.. The processor also wakes.." "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection. Control Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode." "0: Sleep,1: Deep sleep"
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bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable Control. This bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enters sleep or deep sleep on return from an ISR.."
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group.long 0xD18++0xB
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line.long 0x0 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x0 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
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hexmask.long.byte 0x0 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
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hexmask.long.byte 0x0 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
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line.long 0x4 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x4 30.--31. "PRI_11,Priority of System Handler 11 - SVCall. '0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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line.long 0x8 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x8 30.--31. "PRI_15,Priority of System Handler 15 - SysTick. '0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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bitfld.long 0x8 22.--23. "PRI_14,Priority of System Handler 14 - PendSV. '0' denotes the highest priority and '3' denotes the lowest priority." "0,1,2,3"
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tree.end
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tree "SPI (Serial Peripheral Interface)"
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base ad:0x0
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tree "SPI0"
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base ad:0x40060000
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group.long 0x0++0x17
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line.long 0x0 "SPI_CTL,SPI Control Register"
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bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit (Only Supported in SPI0)" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit (Only Supported in SPI0)" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x0 20. "QDIODIR,Quad or Dual I/O Mode Direction Control (Only Supported in SPI0)" "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit. Note:. Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits.. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit (Only Supported in SPI0). Note: When 2-Bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer.." "0: 2-Bit Transfer mode Disabled,1: 2-Bit Transfer mode Enabled"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width. This field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only). The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit. In Master mode the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.. Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPI_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider. The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.. . where . is the peripheral.."
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line.long 0x8 "SPI_SSCTL,SPI Slave Select Control Register"
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hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period (Only Supported in SPI0). In Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the.."
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control (Only Supported in SPI0)" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit (Only Supported in SPI0). Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode the SPI controller can work with 3-wire interface including SPI0_CLK SPI0_MISO and SPI0_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity. This bit defines the active polarity of slave selection signal (SPIn_SS)." "0: The slave selection signal SPIn_SS is active low,1: The slave selection signal SPIn_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control (Master Only). If AUTOSS bit is cleared to 0 " "0: set the SPIn_SS line to inactive state.. Keep..,1: set the SPIn_SS line to active state.. SPIn_SS.."
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line.long 0xC "SPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit. Note: In SPI master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0x10 "SPI_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. In SPI0 TXTH is a 3-bit wide configuration; in SPI1.." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. In SPI0 RXTH is a 3-bit wide configuration; in SPI1 and SPI2 .." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear. Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear. Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit. In Slave mode when TX underflow event occurs this interrupt flag will be set to 1." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity. Note 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.. Note 2: This bit should be set as 0 in I2S mode." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is not.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset. Note: If there is slave receive time-out event the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset. Note: If there is slave receive time-out event the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag. When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.. Note 1: This bit will be cleared by writing 1 to it.. Note 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: The SPI controller is disabled,1: The SPI controller is enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: Receive FIFO does not over run,1: Receive FIFO over run"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the RX FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag. In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag. In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.. Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag (Only Supported in SPI0). When the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in SPI controller logic will be started. When the value of.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt be cleared or..,1: Slave select inactive interrupt event occurrs"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt be cleared or not..,1: Slave select active interrupt event occurrs"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x3
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line.long 0x0 "SPI_TX,Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPI_RX,Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. There are 8-/4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.."
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group.long 0x60++0xB
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line.long 0x0 "SPI_I2SCTL,I2S Control Register"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit. If MCLKEN is set to 1 I2S controller will generate master clock on SPIn_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as master or slave. For Master mode I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from this chip to Audio CODEC chip. In Slave mode I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted out from buffer,1: Transmit data is zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit. Note: If set this bit to 1 I2Sn_BCLK will start to output in master mode." "0: I2S controller Disabled,1: I2S controller Enabled"
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line.long 0x4 "SPI_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider . The I2S controller will generate bit clock in Master mode. The bit clock rate F_I2SBCLK is determined by the following expression."
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hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider. If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The master clock rate F_I2SMCLK is determined by the following expressions.. F_I2SCLK is the frequency of I2S source clock.."
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line.long 0x8 "SPI_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag. When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only). Note: The SPI/I2S peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S controller logic is disabled this bit indicates the real status of SPI/I2S controller logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only). This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI1"
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base ad:0x40061000
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group.long 0x0++0x17
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line.long 0x0 "SPI_CTL,SPI Control Register"
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bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit (Only Supported in SPI0)" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit (Only Supported in SPI0)" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x0 20. "QDIODIR,Quad or Dual I/O Mode Direction Control (Only Supported in SPI0)" "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit. Note:. Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits.. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit (Only Supported in SPI0). Note: When 2-Bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer.." "0: 2-Bit Transfer mode Disabled,1: 2-Bit Transfer mode Enabled"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width. This field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only). The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit. In Master mode the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.. Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPI_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider. The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.. . where . is the peripheral.."
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line.long 0x8 "SPI_SSCTL,SPI Slave Select Control Register"
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hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period (Only Supported in SPI0). In Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the.."
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control (Only Supported in SPI0)" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit (Only Supported in SPI0). Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode the SPI controller can work with 3-wire interface including SPI0_CLK SPI0_MISO and SPI0_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity. This bit defines the active polarity of slave selection signal (SPIn_SS)." "0: The slave selection signal SPIn_SS is active low,1: The slave selection signal SPIn_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control (Master Only). If AUTOSS bit is cleared to 0 " "0: set the SPIn_SS line to inactive state.. Keep..,1: set the SPIn_SS line to active state.. SPIn_SS.."
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line.long 0xC "SPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit. Note: In SPI master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0x10 "SPI_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. In SPI0 TXTH is a 3-bit wide configuration; in SPI1.." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. In SPI0 RXTH is a 3-bit wide configuration; in SPI1 and SPI2 .." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear. Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear. Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit. In Slave mode when TX underflow event occurs this interrupt flag will be set to 1." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity. Note 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.. Note 2: This bit should be set as 0 in I2S mode." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is not.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset. Note: If there is slave receive time-out event the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset. Note: If there is slave receive time-out event the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag. When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.. Note 1: This bit will be cleared by writing 1 to it.. Note 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: The SPI controller is disabled,1: The SPI controller is enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: Receive FIFO does not over run,1: Receive FIFO over run"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the RX FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag. In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag. In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.. Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag (Only Supported in SPI0). When the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in SPI controller logic will be started. When the value of.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt be cleared or..,1: Slave select inactive interrupt event occurrs"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt be cleared or not..,1: Slave select active interrupt event occurrs"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x3
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line.long 0x0 "SPI_TX,Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPI_RX,Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. There are 8-/4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.."
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group.long 0x60++0xB
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line.long 0x0 "SPI_I2SCTL,I2S Control Register"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit. If MCLKEN is set to 1 I2S controller will generate master clock on SPIn_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as master or slave. For Master mode I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from this chip to Audio CODEC chip. In Slave mode I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted out from buffer,1: Transmit data is zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit. Note: If set this bit to 1 I2Sn_BCLK will start to output in master mode." "0: I2S controller Disabled,1: I2S controller Enabled"
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line.long 0x4 "SPI_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider . The I2S controller will generate bit clock in Master mode. The bit clock rate F_I2SBCLK is determined by the following expression."
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hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider. If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The master clock rate F_I2SMCLK is determined by the following expressions.. F_I2SCLK is the frequency of I2S source clock.."
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line.long 0x8 "SPI_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag. When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only). Note: The SPI/I2S peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S controller logic is disabled this bit indicates the real status of SPI/I2S controller logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only). This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI2"
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base ad:0x40062000
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group.long 0x0++0x17
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line.long 0x0 "SPI_CTL,SPI Control Register"
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bitfld.long 0x0 22. "QUADIOEN,Quad I/O Mode Enable Bit (Only Supported in SPI0)" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x0 21. "DUALIOEN,Dual I/O Mode Enable Bit (Only Supported in SPI0)" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x0 20. "QDIODIR,Quad or Dual I/O Mode Direction Control (Only Supported in SPI0)" "0: Quad or Dual Input mode,1: Quad or Dual Output mode"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit. Note:. Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits.. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 16. "TWOBIT,2-bit Transfer Mode Enable Bit (Only Supported in SPI0). Note: When 2-Bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer.." "0: 2-Bit Transfer mode Disabled,1: 2-Bit Transfer mode Enabled"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width. This field specifies how many bits can be transmitted/received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval (Master Only). The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit. In Master mode the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.. Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPI_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider. The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.. . where . is the peripheral.."
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line.long 0x8 "SPI_SSCTL,SPI Slave Select Control Register"
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hexmask.long.word 0x8 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period (Only Supported in SPI0). In Slave mode these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the.."
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 6. "SLVTORST,Slave Mode Time-out Reset Control (Only Supported in SPI0)" "0: When Slave mode time-out event occurs the TX and..,1: When Slave mode time-out event occurs the TX and.."
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bitfld.long 0x8 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit (Only Supported in SPI0)" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x8 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit (Only Supported in SPI0). Slave 3-wire mode is only available in SPI0. In Slave 3-wire mode the SPI controller can work with 3-wire interface including SPI0_CLK SPI0_MISO and SPI0_MOSI pins." "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity. This bit defines the active polarity of slave selection signal (SPIn_SS)." "0: The slave selection signal SPIn_SS is active low,1: The slave selection signal SPIn_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control (Master Only). If AUTOSS bit is cleared to 0 " "0: set the SPIn_SS line to inactive state.. Keep..,1: set the SPIn_SS line to active state.. SPIn_SS.."
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line.long 0xC "SPI_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit. Note: In SPI master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0x10 "SPI_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--30. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0. In SPI0 TXTH is a 3-bit wide configuration; in SPI1.." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 24.--26. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0. In SPI0 RXTH is a 3-bit wide configuration; in SPI1 and SPI2 .." "?,?,2: bit wide only,3: bit wide configuration; in SPI1 and SPI2,?,?,?,?"
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear. Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear. Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit. In Slave mode when TX underflow event occurs this interrupt flag will be set to 1." "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity. Note 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.. Note 2: This bit should be set as 0 in I2S mode." "0: The SPI data out is keep 0 if there is TX..,1: The TX underflow event occurs if there is not.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset. Note: If there is slave receive time-out event the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset. Note: If there is slave receive time-out event the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled." "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPI_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag. When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.. Note 1: This bit will be cleared by writing 1 to it.. Note 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: The SPI controller is disabled,1: The SPI controller is enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: Receive FIFO does not over run,1: Receive FIFO over run"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the RX FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag. In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag. In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.. Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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bitfld.long 0x14 5. "SLVTOIF,Slave Time-out Interrupt Flag (Only Supported in SPI0). When the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in SPI controller logic will be started. When the value of.." "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt be cleared or..,1: Slave select inactive interrupt event occurrs"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt be cleared or not..,1: Slave select active interrupt event occurrs"
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x3
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line.long 0x0 "SPI_TX,Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode or WDWIDTH (SPI_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPI_RX,Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. There are 8-/4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8] or SPI_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.."
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group.long 0x60++0xB
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line.long 0x0 "SPI_I2SCTL,I2S Control Register"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero-cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register will be set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit. If MCLKEN is set to 1 I2S controller will generate master clock on SPIn_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as master or slave. For Master mode I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from this chip to Audio CODEC chip. In Slave mode I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted out from buffer,1: Transmit data is zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit. Note: If set this bit to 1 I2Sn_BCLK will start to output in master mode." "0: I2S controller Disabled,1: I2S controller Enabled"
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line.long 0x4 "SPI_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider . The I2S controller will generate bit clock in Master mode. The bit clock rate F_I2SBCLK is determined by the following expression."
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hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider. If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The master clock rate F_I2SMCLK is determined by the following expressions.. F_I2SCLK is the frequency of I2S source clock.."
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line.long 0x8 "SPI_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag. When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only). Note: The SPI/I2S peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S controller logic is disabled this bit indicates the real status of SPI/I2S controller logic for user." "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the Rx FIFO buffer..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only). This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree.end
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tree "SYS (System Control Registers)"
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base ad:0x40000000
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rgroup.long 0x0++0x3
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line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only). This register reflects device part number code. Software can read this register to identify which device is used."
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group.long 0x4++0xF
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line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x0 8. "CPULKRF,the CPULK Reset Flag Is Set by Hardware If Cortex-m4 Lockup Happened (M45xD/M45xC Only). Note: Write 1 to clear this bit to 0." "0: No reset from CPU lockup happened,1: The Cortex-M4 lockup happened and chip is reset"
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bitfld.long 0x0 7. "CPURF,CPU Reset Flag. The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).. Note: Write 1 to clear this bit to 0." "0: No reset from CPU,1: The Cortex-M4 Core and FMC are reset by software.."
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bitfld.long 0x0 5. "SYSRF,System Reset Flag. The system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from Cortex-M4,1: The Cortex-M4 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag. The BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
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bitfld.long 0x0 3. "LVRF,LVR Reset Flag. The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag. The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.. Note1: Write 1 to clear this bit to 0.. Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is.." "0: No reset from watchdog timer or window watchdog..,1: Write 1 to clear this bit to 0"
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bitfld.long 0x0 1. "PINRF,NRESET Pin Reset Flag. The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag. The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.. Note: Write 1 to clear this bit to 0." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
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line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect). Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.. Note: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x4 4. "USBHRST,USBH Controller Reset (Write Protect) (M45xG/M45xE Only). Set this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.. Note: This bit is write protected. Refer to the.." "0: USBH controller normal operation,1: USBH controller reset"
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bitfld.long 0x4 3. "EBIRST,EBI Controller Reset (Write Protect). Set this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: EBI controller normal operation,1: EBI controller reset"
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bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset (Write Protect). Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA controller normal operation,1: PDMA controller reset"
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bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect). Setting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.. Note: This bit is write protected. Refer to.." "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect). Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.. The CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
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line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x8 28. "EADCRST,EADC Controller Reset" "0: EADC controller normal operation,1: EADC controller reset"
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bitfld.long 0x8 27. "USBDRST,USB Device Controller Reset" "0: USB device controller normal operation,1: USB device controller reset"
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bitfld.long 0x8 26. "OTGRST,OTG Controller Reset (M45xG/M45xE Only)" "0: OTG controller normal operation,1: OTG controller reset"
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bitfld.long 0x8 24. "CAN0RST,CAN0 Controller Reset" "0: CAN0 controller normal operation,1: CAN0 controller reset"
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bitfld.long 0x8 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
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bitfld.long 0x8 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x8 14. "SPI2RST,SPI2 Controller Reset (M45xG/M45xE Only)" "0: SPI2 controller normal operation,1: SPI2 controller reset"
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bitfld.long 0x8 13. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x8 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal operation,1: Analog Comparator 0/1 controller reset"
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bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0xC 17. "PWM1RST,PWM1 Controller Reset" "0: PWM1 controller normal operation,1: PWM1 controller reset"
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bitfld.long 0xC 16. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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bitfld.long 0xC 12. "DACRST,DAC Controller Reset" "0: DAC controller normal operation,1: DAC controller reset"
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bitfld.long 0xC 0. "SC0RST,SC0 Controller Reset" "0: SC0 controller normal operation,1: SC0 controller reset"
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group.long 0x18++0x7
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line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
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bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect). The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.. Note1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
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bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status. It means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function disabled this bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect). Note1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.. Note2: This bit is write protected. Refer to the SYS_REGLCTL.." "0: BOD operate in normal mode (default),1: The BOD consumes about 100uA in normal mode"
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bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag. Note: Write 1 to clear this bit to 0." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect). The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .. Note1: . While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x0 1.--2. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect). The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 2.2V,1: Brown-Out Detector threshold voltage is 2.7V,?,?"
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bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect). The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).. Note1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note2: LIRC must be enabled.." "0: Brown-out Detector function Disabled,1: This bit is write protected"
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line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
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bitfld.long 0x4 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit. This bit is used to enable/disable VBAT unity gain buffer function.. Note: After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result" "0: VBAT unity gain buffer function Disabled (default),1: VBAT unity gain buffer function Enabled"
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bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit. This bit is used to enable/disable temperature sensor function.. Note: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x37
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line.long 0x0 "SYS_PORCTL,Power-On-reset Controller Register"
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hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect). When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
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line.long 0x4 "SYS_VREFCTL,VREF Control Register"
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hexmask.long.byte 0x4 0.--4. 1. "VREFCTL,VREF Control Bits (Write Protect). Note1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note2: Connecting a 1uF capacitor to AVSS will make internal reference voltage more stable."
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line.long 0x8 "SYS_USBPHY,USB PHY Control Register (M45xG/M45xE Only)"
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bitfld.long 0x8 8. "LDO33EN,USB LDO33 Enable Bit (Write Protect) (M45xG/M45xE Only). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: USB LDO33 Disabled,1: USB LDO33 Enabled"
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bitfld.long 0x8 0.--1. "USBROLE,USB Role Option (Write Protect) (M45xG/M45xE Only). These two bits are used to select the role of USB.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Standard USB Device mode,1: Standard USB Host mode,?,?"
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line.long 0xC "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
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hexmask.long.byte 0xC 28.--31. 1. "PA7MFP,PA.7 Multi-function Pin Selection"
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hexmask.long.byte 0xC 24.--27. 1. "PA6MFP,PA.6 Multi-function Pin Selection"
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|
newline
|
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hexmask.long.byte 0xC 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
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hexmask.long.byte 0xC 16.--19. 1. "PA4MFP,PA.4 Multi-function Pin Selection"
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|
newline
|
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hexmask.long.byte 0xC 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
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hexmask.long.byte 0xC 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0xC 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
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hexmask.long.byte 0xC 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
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line.long 0x10 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
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hexmask.long.byte 0x10 28.--31. 1. "PA15MFP,PA.15 Multi-function Pin Selection"
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hexmask.long.byte 0x10 24.--27. 1. "PA14MFP,PA.14 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x10 20.--23. 1. "PA13MFP,PA.13 Multi-function Pin Selection"
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hexmask.long.byte 0x10 16.--19. 1. "PA12MFP,PA.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 12.--15. 1. "PA11MFP,PA.11 Multi-function Pin Selection"
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hexmask.long.byte 0x10 8.--11. 1. "PA10MFP,PA.10 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 4.--7. 1. "PA9MFP,PA.9 Multi-function Pin Selection"
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hexmask.long.byte 0x10 0.--3. 1. "PA8MFP,PA.8 Multi-function Pin Selection"
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line.long 0x14 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x14 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
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hexmask.long.byte 0x14 24.--27. 1. "PB6MFP,PB.6 Multi-function Pin Selection"
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|
newline
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hexmask.long.byte 0x14 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
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hexmask.long.byte 0x14 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x14 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
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hexmask.long.byte 0x14 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x14 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
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hexmask.long.byte 0x14 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
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line.long 0x18 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
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hexmask.long.byte 0x18 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
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hexmask.long.byte 0x18 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x18 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
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hexmask.long.byte 0x18 16.--19. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x18 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
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hexmask.long.byte 0x18 8.--11. 1. "PB10MFP,PB.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x18 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
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hexmask.long.byte 0x18 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
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line.long 0x1C "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x1C 28.--31. 1. "PC7MFP,PC.7 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 24.--27. 1. "PC6MFP,PC.6 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x1C 20.--23. 1. "PC5MFP,PC.5 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 16.--19. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x1C 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x1C 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
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hexmask.long.byte 0x1C 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
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line.long 0x20 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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hexmask.long.byte 0x20 28.--31. 1. "PC15MFP,PC.15 Multi-function Pin Selection"
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hexmask.long.byte 0x20 24.--27. 1. "PC14MFP,PC.14 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x20 20.--23. 1. "PC13MFP,PC.13 Multi-function Pin Selection"
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hexmask.long.byte 0x20 16.--19. 1. "PC12MFP,PC.12 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x20 12.--15. 1. "PC11MFP,PC.11 Multi-function Pin Selection"
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hexmask.long.byte 0x20 8.--11. 1. "PC10MFP,PC.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x20 4.--7. 1. "PC9MFP,PC.9 Multi-function Pin Selection"
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hexmask.long.byte 0x20 0.--3. 1. "PC8MFP,PC.8 Multi-function Pin Selection"
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line.long 0x24 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x24 28.--31. 1. "PD7MFP,PD.7 Multi-function Pin Selection"
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hexmask.long.byte 0x24 24.--27. 1. "PD6MFP,PD.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x24 20.--23. 1. "PD5MFP,PD.5 Multi-function Pin Selection"
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hexmask.long.byte 0x24 16.--19. 1. "PD4MFP,PD.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x24 12.--15. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
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hexmask.long.byte 0x24 8.--11. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x24 4.--7. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
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hexmask.long.byte 0x24 0.--3. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
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line.long 0x28 "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
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hexmask.long.byte 0x28 28.--31. 1. "PD15MFP,PD.15 Multi-function Pin Selection"
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hexmask.long.byte 0x28 24.--27. 1. "PD14MFP,PD.14 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x28 20.--23. 1. "PD13MFP,PD.13 Multi-function Pin Selection"
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hexmask.long.byte 0x28 16.--19. 1. "PD12MFP,PD.12 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x28 12.--15. 1. "PD11MFP,PD.11 Multi-function Pin Selection"
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hexmask.long.byte 0x28 8.--11. 1. "PD10MFP,PD.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x28 4.--7. 1. "PD9MFP,PD.9 Multi-function Pin Selection"
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hexmask.long.byte 0x28 0.--3. 1. "PD8MFP,PD.8 Multi-function Pin Selection"
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line.long 0x2C "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x2C 28.--31. 1. "PE7MFP,PE.7 Multi-function Pin Selection"
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hexmask.long.byte 0x2C 24.--27. 1. "PE6MFP,PE.6 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x2C 20.--23. 1. "PE5MFP,PE.5 Multi-function Pin Selection"
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hexmask.long.byte 0x2C 16.--19. 1. "PE4MFP,PE.4 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x2C 12.--15. 1. "PE3MFP,PE.3 Multi-function Pin Selection"
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hexmask.long.byte 0x2C 8.--11. 1. "PE2MFP,PE.2 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x2C 4.--7. 1. "PE1MFP,PE.1 Multi-function Pin Selection"
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hexmask.long.byte 0x2C 0.--3. 1. "PE0MFP,PE.0 Multi-function Pin Selection"
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line.long 0x30 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
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hexmask.long.byte 0x30 24.--27. 1. "PE14_MFP,PE.14 Multi-function Pin Selection"
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hexmask.long.byte 0x30 20.--23. 1. "PE13MFP,PE.13 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x30 16.--19. 1. "PE12MFP,PE.12 Multi-function Pin Selection"
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hexmask.long.byte 0x30 12.--15. 1. "PE11MFP,PE.11 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x30 8.--11. 1. "PE10MFP,PE.10 Multi-function Pin Selection"
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hexmask.long.byte 0x30 4.--7. 1. "PE9MFP,PE.9 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x30 0.--3. 1. "PE8MFP,PE.8 Multi-function Pin Selection"
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line.long 0x34 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
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hexmask.long.byte 0x34 28.--31. 1. "PF7MFP,PF.7 Multi-function Pin Selection"
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hexmask.long.byte 0x34 24.--27. 1. "PF6MFP,PF.6 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x34 20.--23. 1. "PF5MFP,PF.5 Multi-function Pin Selection"
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hexmask.long.byte 0x34 16.--19. 1. "PF4MFP,PF.4 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x34 12.--15. 1. "PF3MFP,PF.3 Multi-function Pin Selection"
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hexmask.long.byte 0x34 8.--11. 1. "PF2MFP,PF.2 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x34 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
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hexmask.long.byte 0x34 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
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group.long 0xC0++0x3
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line.long 0x0 "SYS_SRAM_INTCTL,System SRAM Interrupt Enable Control Register"
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bitfld.long 0x0 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
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rgroup.long 0xC4++0x7
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line.long 0x0 "SYS_SRAM_STATUS,System SRAM Parity Error Status Register"
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bitfld.long 0x0 0. "PERRIF,SRAM Parity Check Error Flag" "0: No System SRAM parity error,1: System SRAM parity error occur"
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line.long 0x4 "SYS_SRAM_ERRADDR,System SRAM Parity Check Error Address Register"
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hexmask.long 0x4 0.--31. 1. "ERRADDR,System SRAM Parity Error Address. This register shows system SRAM parity error byte address."
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group.long 0xD0++0x3
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line.long 0x0 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
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bitfld.long 0x0 4. "USBBIST,USB BIST Enable Bit (Write Protect). This bit enables BIST test for USB RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system USB BIST Disabled,1: system USB BIST Enabled"
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bitfld.long 0x0 3. "CANBIST,CAN BIST Enable Bit (Write Protect). This bit enables BIST test for CAN RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system CAN BIST Disabled,1: system CAN BIST Enabled"
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newline
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bitfld.long 0x0 2. "CRBIST,CACHE BIST Enable Bit (Write Protect). This bit enables BIST test for CACHE RAM. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system CACHE BIST Disabled,1: system CACHE BIST Enabled"
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bitfld.long 0x0 1. "SRBIST1,2nd SRAM BIST Enable Bit (Write Protect). This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system SRAM BIST Disabled,1: system SRAM BIST Enabled"
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newline
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bitfld.long 0x0 0. "SRBIST0,1st SRAM BIST Enable Bit (Write Protect). This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: system SRAM BIST Disabled,1: system SRAM BIST Enabled"
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rgroup.long 0xD4++0x3
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line.long 0x0 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
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bitfld.long 0x0 20. "USBBEND,USB SRAM BIST Test Finish" "0: USB SRAM BIST is active,1: USB SRAM BIST test finish"
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bitfld.long 0x0 19. "CANBEND,CAN SRAM BIST Test Finish" "0: CAN SRAM BIST is active,1: CAN SRAM BIST test finish"
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|
newline
|
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bitfld.long 0x0 18. "CRBEND,CACHE SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finish"
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bitfld.long 0x0 17. "SRBEND1,2nd SRAM BIST Test Finish" "0: 2nd system SRAM BIST is active,1: 2nd system SRAM BIST finish"
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|
newline
|
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bitfld.long 0x0 16. "SRBEND0,1st SRAM BIST Test Finish" "0: 1st system SRAM BIST active,1: 1st system SRAM BIST finish"
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bitfld.long 0x0 4. "USBBEF,USB SRAM BIST Fail Flag" "0: USB SRAM BIST test pass,1: USB SRAM BIST test fail"
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|
newline
|
|
bitfld.long 0x0 3. "CANBEF,CAN SRAM BIST Fail Flag" "0: CAN SRAM BIST test pass,1: CAN SRAM BIST test fail"
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bitfld.long 0x0 2. "CRBISTEF,CACHE SRAM BIST Fail Flag" "0: System CACHE RAM BIST test pass,1: System CACHE RAM BIST test fail"
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|
newline
|
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bitfld.long 0x0 1. "SRBISTEF1,2nd System SRAM BIST Fail Flag" "0: 2nd system SRAM BIST test pass,1: 2nd system SRAM BIST test fail"
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bitfld.long 0x0 0. "SRBISTEF0,1st System SRAM BIST Fail Flag" "0: 1st system SRAM BIST test pass,1: 1st system SRAM BIST test fail"
|
|
group.long 0xF0++0xB
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line.long 0x0 "SYS_IRCTCTL,HIRC Trim Control Register"
|
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bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count. This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.. Once the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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|
newline
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bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection. This field defines that trim value calculation is based on how many 32.768 kHz clock.. Note: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection. This field indicates the target frequency of 22.1184 MHz internal high speed RC oscillator (HIRC) auto trim.. During auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
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line.long 0x4 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKEIEN,Clock Error Interrupt Enable Bit. This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.. If this bit is set to1 and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_IRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS[2]) status to.."
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bitfld.long 0x4 1. "TFAILIEN,Trim Failure Interrupt Enable Bit. This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).. If this bit.." "0: Disable TFAILIF(SYS_IRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger.."
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line.long 0x8 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status. When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status. This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will.." "0: Trim value update limitation count does not reach,1: Trim value update limitation count reached and.."
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newline
|
|
bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status. This bit indicates the HIRC frequency is locked.. This is a status bit and doesn't trigger any interrupt." "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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group.long 0x100++0x3
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|
line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
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|
hexmask.long.byte 0x0 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only). Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is.."
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|
group.long 0x400++0x3
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|
line.long 0x0 "SYS_AHBMCTL,AHB Bus Matrix Priority Control Register"
|
|
bitfld.long 0x0 0. "INTACTEN,Highest AHB Bus Priority of Cortex M4 Core Enable Bit (Write Protect). Enable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Run robin mode,1: Cortex-M4 CPU with highest bus priority when.."
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|
tree.end
|
|
tree "TMR (Timer Controller)"
|
|
base ad:0x0
|
|
tree "TMR01"
|
|
base ad:0x40050000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "TIMER0_CTL,Timer0 Control and Status Register"
|
|
bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
|
|
newline
|
|
bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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|
bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?"
|
|
newline
|
|
bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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|
rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
|
|
newline
|
|
bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled." "0: Event counter mode Disabled,1: Event counter mode Enabled"
|
|
bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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|
newline
|
|
bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.."
|
|
bitfld.long 0x0 21. "TRGEADC,Trigger EADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger EADC." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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|
newline
|
|
bitfld.long 0x0 20. "TRGDAC,Trigger DAC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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|
bitfld.long 0x0 19. "TRGPWM,Trigger PWM Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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|
newline
|
|
bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM.."
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|
hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
|
|
line.long 0x4 "TIMER0_CMP,Timer0 Compare Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.. Note1: Never write 0x0 or 0x1 in CMPDAT field or.."
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|
line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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rgroup.long 0xC++0x7
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line.long 0x0 "TIMER0_CNT,Timer0 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24- bit counter value .. If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT value for getting current 24- bit event input counter value."
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line.long 0x4 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x7
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line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: Tx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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newline
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit. This bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?"
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newline
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.."
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line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag. This bit indicates the timer external capture interrupt flag status.. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x20++0xB
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line.long 0x0 "TIMER1_CTL,Timer1 Control and Status Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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newline
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGEADC,Trigger EADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger EADC." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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newline
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bitfld.long 0x0 20. "TRGDAC,Trigger DAC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x0 19. "TRGPWM,Trigger PWM Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM.."
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
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line.long 0x4 "TIMER1_CMP,Timer1 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.. Note1: Never write 0x0 or 0x1 in CMPDAT field or.."
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line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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rgroup.long 0x2C++0x7
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line.long 0x0 "TIMER1_CNT,Timer1 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24- bit counter value .. If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT value for getting current 24- bit event input counter value."
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line.long 0x4 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x34++0x7
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line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: Tx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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newline
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit. This bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?"
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newline
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.."
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line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag. This bit indicates the timer external capture interrupt flag status.. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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tree.end
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tree "TMR23"
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base ad:0x40051000
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group.long 0x0++0xB
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line.long 0x0 "TIMER2_CTL,Timer2 Control and Status Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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newline
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGEADC,Trigger EADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger EADC." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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newline
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bitfld.long 0x0 20. "TRGDAC,Trigger DAC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x0 19. "TRGPWM,Trigger PWM Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM.."
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
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line.long 0x4 "TIMER2_CMP,Timer2 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.. Note1: Never write 0x0 or 0x1 in CMPDAT field or.."
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line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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rgroup.long 0xC++0x7
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line.long 0x0 "TIMER2_CNT,Timer2 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24- bit counter value .. If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT value for getting current 24- bit event input counter value."
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line.long 0x4 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x7
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line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: Tx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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newline
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit. This bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?"
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newline
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.."
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line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag. This bit indicates the timer external capture interrupt flag status.. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x20++0xB
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line.long 0x0 "TIMER3_CTL,Timer3 Control and Status Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot mode,1: The Timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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newline
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter Pin),1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGEADC,Trigger EADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger EADC." "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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newline
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bitfld.long 0x0 20. "TRGDAC,Trigger DAC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC." "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x0 19. "TRGPWM,Trigger PWM Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM." "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger PWM.."
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter"
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line.long 0x4 "TIMER3_CMP,Timer3 Compare Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Compared Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.. Note1: Never write 0x0 or 0x1 in CMPDAT field or.."
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line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matches the CMPDAT value"
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rgroup.long 0x2C++0x7
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line.long 0x0 "TIMER3_CNT,Timer3 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. If EXTCNTEN (TIMERx_CTL[24] ) is 0 user can read CNT value for getting current 24- bit counter value .. If EXTCNTEN (TIMERx_CTL[24] ) is 1 user can read CNT value for getting current 24- bit event input counter value."
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line.long 0x4 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x34++0x7
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line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit." "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of Tx_EXT pin is detected with de-bounce circuit." "0: Tx_EXT (x= 0~3) pin de-bounce Disabled,1: Tx_EXT (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt Disabled,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer External Capture Pin Enable Bit. This bit enables the Tx_EXT pin." "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on Tx_EXT (x= 0~3) pin will be..,1: A Rising edge on Tx_EXT (x= 0~3) pin will be..,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A Falling edge of external counting pin will be..,1: A Rising edge of external counting pin will be.."
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line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer External Capture Interrupt Flag. This bit indicates the timer external capture interrupt flag status.. Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will.." "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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base ad:0x0
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tree "UART0"
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base ad:0x40070000
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group.long 0x0++0x17
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX DMA Enable Bit. This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX DMA Enable Bit. This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Bit. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Bit" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.."
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit (Not Available in UART2/UART3). Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empt interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable . The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note : Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.. Note2: Refer to Figure 6.1321 and Figure 6.1322 for RS-485 function mode." "0: n RTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control. This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag (Read Only). This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit is read only but can be cleared by writing.." "0: nCTS input has not change state,1: nCTS input has change state"
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rgroup.long 0x18++0x7
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line.long 0x0 "UART_FIFOSTS,UART FIFO Status Register"
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bitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only). If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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bitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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bitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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bitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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bitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only). This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) . Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) . Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.."
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bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) . This bit is set to logic '1' when auto-baud rate detect function is finished. . Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only). This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit is read only but can be cleared.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x4 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HWBUFEINT,in DMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HWTOINT,in DMA Mode Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HWMODINT,in DMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HWRLSINT,in DMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HWBUFEIF,in DMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 20. "HWTOIF,in DMA Mode Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 19. "HWMODIF,in DMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 18. "HWRLSIF,in DMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only). This bit is set if chip wake-up from power-down state by data wake-up.. Note1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared.." "0: Chip stays in power-down state,1: If WKDATIEN"
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bitfld.long 0x4 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only). Note1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
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bitfld.long 0x4 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel). This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "RXTOINT,Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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bitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel). Note: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) .." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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bitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.. Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
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bitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 4. "RXTOIF,Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled the Tout interrupt will be generated.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 3. "MODEMIF,Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) . This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x1B
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 623."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 623."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0,1"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function (AUD) . Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD). Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LINTXEN,LIN TX Break Mode Enable Bit (Only Available in UART0/UART1 Channel). Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LINRXEN,LIN RX Enable Bit (Only Available in UART0/UART1 Channel)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "BRKFL,UART LIN Break Field Length (Only Available in UART0/UART1 Channel). This field indicates a 4-bit LIN TX break field count.. Note1: This break field length is BRKFL + 1"
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function (Only Available in UART0/UART1..,?,?"
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line.long 0x14 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "PID,LIN PID Bits. If the parity generated by hardware user fill ID0~ID5 (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.. Note1: User can fill any 8-bit value to this.."
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bitfld.long 0x14 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x14 20.--21. "BSL,LIN Break/Sync Delimiter Length . Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
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hexmask.long.byte 0x14 16.--19. 1. "BRKFL,LIN Break Field Length . This field indicates a 4-bit LIN TX break field count.. Note1: These registers are shadow registers of BRKFL User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).. Note2: This break.."
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bitfld.long 0x14 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 11. "RXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x14 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x14 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x14 8. "SENDH,LIN TX Send Header Enable Bit. The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).. Note1: These registers are shadow registers of SENDH.." "0: Send LIN TX header Disabled,1: These registers are shadow registers of SENDH"
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bitfld.long 0x14 4. "MUTE,LIN Mute Mode Enable Bit. Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.13.5.9 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x14 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit. Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) . Note3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x14 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit. Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).. Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x14 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x14 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x18 "UART_LINSTS,UART LIN Status Register"
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rbitfld.long 0x18 9. "BITEF,Bit Error Detect Status Flag (Read Only) . At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BITEF (UART_LINSTS[9]) will be set." "0,1"
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rbitfld.long 0x18 8. "BRKDETF,LIN Break Detection Flag (Read Only). This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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rbitfld.long 0x18 3. "SLVSYNCF,LIN Slave Sync Field (Read Only). This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x18 2. "SLVIDPEF,LIN Slave ID Parity Error Flag . This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x18 1. "SLVHEF,LIN Slave Header Error Flag (Read Only). This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame.." "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x18 0. "SLVHDETF,LIN Slave Header Detection Flag (Read Only)). This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.. Note3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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tree.end
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tree "UART1"
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base ad:0x40071000
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group.long 0x0++0x17
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX DMA Enable Bit. This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX DMA Enable Bit. This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Bit. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Bit" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.."
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit (Not Available in UART2/UART3). Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empt interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable . The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note : Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.. Note2: Refer to Figure 6.1321 and Figure 6.1322 for RS-485 function mode." "0: n RTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control. This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag (Read Only). This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit is read only but can be cleared by writing.." "0: nCTS input has not change state,1: nCTS input has change state"
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rgroup.long 0x18++0x7
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line.long 0x0 "UART_FIFOSTS,UART FIFO Status Register"
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bitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only). If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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bitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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bitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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bitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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bitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only). This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) . Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) . Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.."
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bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) . This bit is set to logic '1' when auto-baud rate detect function is finished. . Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only). This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit is read only but can be cleared.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x4 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HWBUFEINT,in DMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HWTOINT,in DMA Mode Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HWMODINT,in DMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HWRLSINT,in DMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HWBUFEIF,in DMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 20. "HWTOIF,in DMA Mode Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 19. "HWMODIF,in DMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 18. "HWRLSIF,in DMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only). This bit is set if chip wake-up from power-down state by data wake-up.. Note1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared.." "0: Chip stays in power-down state,1: If WKDATIEN"
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bitfld.long 0x4 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only). Note1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
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bitfld.long 0x4 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel). This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "RXTOINT,Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel). Note: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) .." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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bitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.. Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
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bitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 4. "RXTOIF,Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled the Tout interrupt will be generated.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 3. "MODEMIF,Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) . This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x1B
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 623."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 623."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0,1"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function (AUD) . Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD). Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LINTXEN,LIN TX Break Mode Enable Bit (Only Available in UART0/UART1 Channel). Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LINRXEN,LIN RX Enable Bit (Only Available in UART0/UART1 Channel)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "BRKFL,UART LIN Break Field Length (Only Available in UART0/UART1 Channel). This field indicates a 4-bit LIN TX break field count.. Note1: This break field length is BRKFL + 1"
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function (Only Available in UART0/UART1..,?,?"
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line.long 0x14 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x14 24.--31. 1. "PID,LIN PID Bits. If the parity generated by hardware user fill ID0~ID5 (PID [29:24] )hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.. Note1: User can fill any 8-bit value to this.."
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bitfld.long 0x14 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and 'sync..,?,?"
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bitfld.long 0x14 20.--21. "BSL,LIN Break/Sync Delimiter Length . Note: This bit used for LIN master to sending header field." "0: The LIN break/sync delimiter length is 1-bit time,1: The LIN break/sync delimiter length is 2-bit time,?,?"
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hexmask.long.byte 0x14 16.--19. 1. "BRKFL,LIN Break Field Length . This field indicates a 4-bit LIN TX break field count.. Note1: These registers are shadow registers of BRKFL User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).. Note2: This break.."
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bitfld.long 0x14 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
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bitfld.long 0x14 11. "RXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x14 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x14 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x14 8. "SENDH,LIN TX Send Header Enable Bit. The LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).. Note1: These registers are shadow registers of SENDH.." "0: Send LIN TX header Disabled,1: These registers are shadow registers of SENDH"
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bitfld.long 0x14 4. "MUTE,LIN Mute Mode Enable Bit. Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.13.5.9 (LIN slave mode)." "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x14 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit. Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode this bit should be kept cleared) . Note3: The control and interactions of this field are.." "0: UART_BAUD updated is written by software (if no..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x14 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit. Note2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).. Note3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x14 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x14 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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line.long 0x18 "UART_LINSTS,UART LIN Status Register"
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rbitfld.long 0x18 9. "BITEF,Bit Error Detect Status Flag (Read Only) . At TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BITEF (UART_LINSTS[9]) will be set." "0,1"
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rbitfld.long 0x18 8. "BRKDETF,LIN Break Detection Flag (Read Only). This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software." "0: LIN break not detected,1: LIN break detected"
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rbitfld.long 0x18 3. "SLVSYNCF,LIN Slave Sync Field (Read Only). This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. When the receiver header have some error been detect user must reset the internal circuit to re-search new frame.." "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x18 2. "SLVIDPEF,LIN Slave ID Parity Error Flag . This bit is set by hardware when receipted frame ID parity is not correct." "0: No active,1: Receipted frame ID parity is not correct"
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rbitfld.long 0x18 1. "SLVHEF,LIN Slave Header Error Flag (Read Only). This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include 'break delimiter is too short (less than 0.5 bit time)' 'frame.." "0: LIN header error not detected,1: LIN header error detected"
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rbitfld.long 0x18 0. "SLVHDETF,LIN Slave Header Detection Flag (Read Only)). This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.. Note3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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tree.end
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tree "UART2"
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base ad:0x40072000
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group.long 0x0++0x17
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX DMA Enable Bit. This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX DMA Enable Bit. This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Bit. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Bit" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.."
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit (Not Available in UART2/UART3). Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empt interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable . The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note : Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.. Note2: Refer to Figure 6.1321 and Figure 6.1322 for RS-485 function mode." "0: n RTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control. This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag (Read Only). This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit is read only but can be cleared by writing.." "0: nCTS input has not change state,1: nCTS input has change state"
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rgroup.long 0x18++0x7
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line.long 0x0 "UART_FIFOSTS,UART FIFO Status Register"
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bitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only). If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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bitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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bitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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bitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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bitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only). This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) . Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) . Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.."
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bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) . This bit is set to logic '1' when auto-baud rate detect function is finished. . Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only). This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit is read only but can be cleared.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x4 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HWBUFEINT,in DMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HWTOINT,in DMA Mode Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HWMODINT,in DMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HWRLSINT,in DMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HWBUFEIF,in DMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 20. "HWTOIF,in DMA Mode Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 19. "HWMODIF,in DMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 18. "HWRLSIF,in DMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only). This bit is set if chip wake-up from power-down state by data wake-up.. Note1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared.." "0: Chip stays in power-down state,1: If WKDATIEN"
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bitfld.long 0x4 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only). Note1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
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bitfld.long 0x4 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel). This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "RXTOINT,Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel). Note: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) .." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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bitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.. Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
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bitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 4. "RXTOIF,Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled the Tout interrupt will be generated.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 3. "MODEMIF,Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) . This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x13
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 623."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 623."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0,1"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function (AUD) . Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD). Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LINTXEN,LIN TX Break Mode Enable Bit (Only Available in UART0/UART1 Channel). Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LINRXEN,LIN RX Enable Bit (Only Available in UART0/UART1 Channel)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "BRKFL,UART LIN Break Field Length (Only Available in UART0/UART1 Channel). This field indicates a 4-bit LIN TX break field count.. Note1: This break field length is BRKFL + 1"
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function (Only Available in UART0/UART1..,?,?"
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tree.end
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tree "UART3"
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base ad:0x40073000
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group.long 0x0++0x17
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Receiving/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX DMA Enable Bit. This bit can enable or disable RX DMA service." "0: RX DMA Disabled,1: RX DMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX DMA Enable Bit. This bit can enable or disable TX DMA service." "0: TX DMA Disabled,1: TX DMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Time-out Counter Enable Bit" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Bit. Note: Hardware will clear this bit when the incoming data wake-up operation finishes and 'system clock' work stable." "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Bit" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled when the system.."
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bitfld.long 0x4 8. "LINIEN,LIN Bus Interrupt Enable Bit (Not Available in UART2/UART3). Note: This bit is used for LIN function mode." "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empt interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable . The receiver is disabled or not (set 1 to disable receiver). Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the TX internal state machine and pointers"
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note: This bit will automatically clear at least 3 UART peripheral clock cycles." "0: No effect,1: Reset the RX internal state machine and pointers"
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note:This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note : Parity bit is generated on each outgoing character and is checked on each incoming data." "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note1: Refer to Figure 6.1310 and Figure 6.1311 for UART function mode.. Note2: Refer to Figure 6.1321 and Figure 6.1322 for RS-485 function mode." "0: n RTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS (Request-to-send) Signal Control. This bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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rbitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag (Read Only). This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit is read only but can be cleared by writing.." "0: nCTS input has not change state,1: nCTS input has change state"
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rgroup.long 0x18++0x7
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line.long 0x0 "UART_FIFOSTS,UART FIFO Status Register"
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bitfld.long 0x0 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x0 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only). If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit is read only but can be cleared by writing '1' to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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bitfld.long 0x0 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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bitfld.long 0x0 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into DAT (TX.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x0 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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bitfld.long 0x0 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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bitfld.long 0x0 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x0 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x0 6. "BIF,Break Interrupt Flag (Read Only). This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity +.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x0 5. "FEF,Framing Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit is read only but.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x0 4. "PEF,Parity Error Flag (Read Only). This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit is read only but can be cleared by writing '1' to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x0 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) . Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x0 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) . Note1: This bit is set to logic '1' in Auto-baud Rate Detect mode and the baud rate counter is overflow.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate counter is underflow,1: This bit is set to logic '1' in Auto-baud Rate.."
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bitfld.long 0x0 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) . This bit is set to logic '1' when auto-baud rate detect function is finished. . Note: This bit is read only but can be cleared by writing '1' to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x0 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only). This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit is read only but can be cleared.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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line.long 0x4 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x4 29. "HWBUFEINT,in DMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1." "0: No buffer error interrupt is generated in DMA mode,1: Buffer error interrupt is generated in DMA mode"
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bitfld.long 0x4 28. "HWTOINT,in DMA Mode Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No Tout interrupt is generated in DMA mode,1: Tout interrupt is generated in DMA mode"
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bitfld.long 0x4 27. "HWMODINT,in DMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1." "0: No Modem interrupt is generated in DMA mode,1: Modem interrupt is generated in DMA mode"
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bitfld.long 0x4 26. "HWRLSINT,in DMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in DMA mode,1: RLS interrupt is generated in DMA mode"
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bitfld.long 0x4 21. "HWBUFEIF,in DMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 20. "HWTOIF,in DMA Mode Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). If TOUTIEN (UART_INTEN [4]) is enabled the Tout.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 19. "HWMODIF,in DMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 18. "HWRLSIF,in DMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only). This bit is set if chip wake-up from power-down state by data wake-up.. Note1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared.." "0: Chip stays in power-down state,1: If WKDATIEN"
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bitfld.long 0x4 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only). Note1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.. Note2: This bit is read only but can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSIEN"
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bitfld.long 0x4 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel). This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1." "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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bitfld.long 0x4 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BFERRIEN(UART_INTEN[5] and BERRIF(UART_INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x4 12. "RXTOINT,Time-out Interrupt Indicator (Read Only). This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No Tout interrupt is generated,1: Tout interrupt is generated"
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bitfld.long 0x4 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x4 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x4 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x4 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x4 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel). Note: This bit is read only. This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) .." "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF SLVIDPEF.."
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bitfld.long 0x4 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.. Note: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are.." "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
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bitfld.long 0x4 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BERRIF (UART_INTSTS[5])is set the transfer is not correct. If BFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x4 4. "RXTOIF,Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUTIEN (UART_INTEN [4]) is enabled the Tout interrupt will be generated.." "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
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bitfld.long 0x4 3. "MODEMIF,Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x4 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x4 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) . This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x4 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x13
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divisor Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detail description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detail description is shown in Table 623."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown in Table 623."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal" "0: None inverse receiving input signal,1: Inverse receiving input signal. (Default)"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal" "0: None inverse transmitting signal. (Default),1: Inverse transmitting output signal"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note : The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0,1"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function (AUD) . Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD). Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0xC 7. "LINTXEN,LIN TX Break Mode Enable Bit (Only Available in UART0/UART1 Channel). Note: When TX break field transfer operation finished this bit will be cleared automatically." "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0xC 6. "LINRXEN,LIN RX Enable Bit (Only Available in UART0/UART1 Channel)" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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hexmask.long.byte 0xC 0.--3. 1. "BRKFL,UART LIN Break Field Length (Only Available in UART0/UART1 Channel). This field indicates a 4-bit LIN TX break field count.. Note1: This break field length is BRKFL + 1"
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function (Only Available in UART0/UART1..,?,?"
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tree.end
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tree.end
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tree "USBD (USB Device Controller)"
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base ad:0x400C0000
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group.long 0x0++0xB
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line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register"
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bitfld.long 0x0 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.."
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bitfld.long 0x0 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x0 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
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bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register"
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bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by write 1 to.."
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bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
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bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
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bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
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bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
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bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
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bitfld.long 0x4 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event does not occur,1: No-event-wake-up event occurred cleared by write.."
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bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB bus.."
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bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status. The USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred check EPSTS0~5[2:0] to know.."
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bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status. The BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] to know.."
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line.long 0x8 "USBD_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address"
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rgroup.long 0xC++0x3
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line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register"
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bitfld.long 0x0 29.--31. "EPSTS7,Endpoint 7 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 26.--28. "EPSTS6,Endpoint 6 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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|
bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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|
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bitfld.long 0x0 7. "OV,Overrun. It indicates that the received data is over the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.."
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|
group.long 0x10++0x3
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line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register"
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|
bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.."
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|
bitfld.long 0x0 9. "PWRDN,Power-down PHY Transceiver Low Active (M45xD/M45xC Only)" "0: Power-down related circuits of PHY transceiver,1: Turn-on related circuits of PHY transceiver"
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bitfld.long 0x0 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low and USB_D- high).."
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bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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bitfld.long 0x0 3. "TOUT,Time-out Status. Note: This bit is read only." "0: No time-out,1: No Bus response more than 18 bits time"
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bitfld.long 0x0 2. "RESUME,Resume Status. Note: This bit is read only." "0: No bus resume,1: Resume from suspend"
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bitfld.long 0x0 1. "SUSPEND,Suspend Status. Note: This bit is read only." "0: Bus no suspend,1: Bus idle more than 3 ms either cable is plugged.."
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bitfld.long 0x0 0. "USBRST,USB Reset Status. Note: This bit is read only." "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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|
rgroup.long 0x14++0x3
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|
line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register"
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|
bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
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|
group.long 0x18++0x3
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line.long 0x0 "USBD_STBUFSEG,USB Setup Token Buffer Segmentation Register"
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|
hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,SETUP Token Buffer Segmentation. It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is. USBD_SRAM address + {STBUFSEG 3'b000} . Note: It is used for SETUP token.."
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|
group.long 0x90++0x3
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|
line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register"
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bitfld.long 0x0 0. "SE0,Drive Single Ended Zero in USB Bus. The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
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|
group.long 0x500++0x7F
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|
line.long 0x0 "USBD_BUFSEG0,USB Endpoint 0 Buffer Segmentation Register"
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|
hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x4 "USBD_MXPLD0,USB Endpoint 0 Maximal Payload Register"
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hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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|
line.long 0x8 "USBD_CFG0,USB Endpoint 0 Configuration Register"
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bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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|
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bitfld.long 0x8 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
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hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0xC "USBD_CFGP0,USB Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xC 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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|
line.long 0x10 "USBD_BUFSEG1,USB Endpoint 1 Buffer Segmentation Register"
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hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x14 "USBD_MXPLD1,USB Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x18 "USBD_CFG1,USB Endpoint 1 Configuration Register"
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bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x18 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0x1C "USBD_CFGP1,USB Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x1C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x1C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x20 "USBD_BUFSEG2,USB Endpoint 2 Buffer Segmentation Register"
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hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x24 "USBD_MXPLD2,USB Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x28 "USBD_CFG2,USB Endpoint 2 Configuration Register"
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bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x28 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
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hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0x2C "USBD_CFGP2,USB Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x2C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x2C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x30 "USBD_BUFSEG3,USB Endpoint 3 Buffer Segmentation Register"
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hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x34 "USBD_MXPLD3,USB Endpoint 3 Maximal Payload Register"
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hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x38 "USBD_CFG3,USB Endpoint 3 Configuration Register"
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bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x38 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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line.long 0x3C "USBD_CFGP3,USB Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x3C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x3C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x40 "USBD_BUFSEG4,USB Endpoint 4 Buffer Segmentation Register"
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hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x44 "USBD_MXPLD4,USB Endpoint 4 Maximal Payload Register"
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hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x48 "USBD_CFG4,USB Endpoint 4 Configuration Register"
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bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x48 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0x4C "USBD_CFGP4,USB Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x4C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x4C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x50 "USBD_BUFSEG5,USB Endpoint 5 Buffer Segmentation Register"
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hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x54 "USBD_MXPLD5,USB Endpoint 5 Maximal Payload Register"
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hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x58 "USBD_CFG5,USB Endpoint 5 Configuration Register"
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bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x58 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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|
bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0x5C "USBD_CFGP5,USB Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x5C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x5C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x60 "USBD_BUFSEG6,USB Endpoint 6 Buffer Segmentation Register"
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hexmask.long.byte 0x60 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x64 "USBD_MXPLD6,USB Endpoint 6 Maximal Payload Register"
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hexmask.long.word 0x64 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x68 "USBD_CFG6,USB Endpoint 6 Configuration Register"
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bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x68 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x68 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x68 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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line.long 0x6C "USBD_CFGP6,USB Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x6C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x6C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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line.long 0x70 "USBD_BUFSEG7,USB Endpoint 7 Buffer Segmentation Register"
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hexmask.long.byte 0x70 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is. USBD_SRAM address + {BUFSEG[8:3] 3'b000}. Refer to the section.."
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line.long 0x74 "USBD_MXPLD7,USB Endpoint 7 Maximal Payload Register"
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hexmask.long.word 0x74 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in.."
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line.long 0x78 "USBD_CFG7,USB Endpoint 7 Configuration Register"
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bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x78 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x78 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshaking." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x78 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint"
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|
line.long 0x7C "USBD_CFGP7,USB Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x7C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x7C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0: No effect,1: Clear the IN token had ready to transmit the.."
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tree.end
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tree "USBH (USB 1.1 Host Controller)"
|
|
base ad:0x40009000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "HCREVISION,Host Controller Revision Register"
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|
hexmask.long.byte 0x0 0.--7. 1. "REV,Revision Number. Indicates the Open HCI Specification revision number implemented by the Hardware. Host Controller supports 1.1 specification."
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|
group.long 0x4++0x33
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line.long 0x0 "HCCONTROL,Host Controller Control Register"
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bitfld.long 0x0 6.--7. "HCFS,Host Controller Functional State. This field sets the Host Controller state. The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port. States are:" "0: USBRESET,1: USBRESUME,?,?"
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bitfld.long 0x0 5. "BLE,Bulk List Enable Bit" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
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bitfld.long 0x0 4. "CLE,Control List Enable Bit" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next frame.."
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|
bitfld.long 0x0 3. "IE,Isochronous List Enable Bit. Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list. Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list." "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the next.."
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bitfld.long 0x0 2. "PLE,Periodic List Enable Bit. When set this bit enables processing of the Periodic (interrupt and isochronous) list. The Host Controller checks this bit prior to attempting any periodic transfers in a frame.. Note: To enable the processing of the.." "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
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bitfld.long 0x0 0.--1. "CBSR,Control Bulk Service Ratio. This specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been.." "0: Number of Control EDs over Bulk EDs served is 1:1,1: Number of Control EDs over Bulk EDs served is 2:1,?,?"
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line.long 0x4 "HCCOMMANDSTATUS,Host Controller CMD Status Register"
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bitfld.long 0x4 16.--17. "SOC,Schedule Overrun Count. These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been.." "0,1,2,3"
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bitfld.long 0x4 2. "BLF,Bulk List Filled. Set high to indicate there is an active TD on the Bulk list. This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Bulk list"
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bitfld.long 0x4 1. "CLF,Control List Filled. Set high to indicate there is an active TD on the Control List. It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List." "0: No active TD found or Host Controller begins to..,1: An active TD added or found on the Control list"
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bitfld.long 0x4 0. "HCR,Host Controller Reset. This bit is set to initiate the software reset of Host Controller. This bit is cleared by the Host Controller upon completed of the reset operation.. This bit when set didn't reset the Root Hub and no subsequent reset.." "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
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line.long 0x8 "HCINTERRUPTSTATUS,Host Controller Interrupt Status Register"
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bitfld.long 0x8 6. "RHSC,Root Hub Status Change. This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed." "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
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bitfld.long 0x8 5. "FNO,Frame Number Overflow. This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1." "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to 0.."
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bitfld.long 0x8 3. "RD,Resume Detected. Set when Host Controller detects resume signaling on a downstream port." "0: No resume signaling detected on a downstream port,1: Resume signaling detected on a downstream port"
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bitfld.long 0x8 2. "SF,Start of Frame. Set when the Frame Management functional block signals a 'Start of Frame' event. Host Control generates a SOF token at the same time." "0: .Not the start of a frame,1: .Indicate the start of a frame and Host.."
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bitfld.long 0x8 1. "WDH,Write Back Done Head. Set after the Host Controller has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared." "0: .Host Controller didn't update HccaDoneHead,1: .Host Controller has written HcDoneHead to.."
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bitfld.long 0x8 0. "SO,Scheduling Overrun. Set when the List Processor determines a Schedule Overrun has occurred." "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
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line.long 0xC "HCINTERRUPTENABLE,Host Controller Interrupt Enable Register"
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bitfld.long 0xC 31. "MIE,Master Interrupt Enable Bit. This bit is a global interrupt enable. A write of '1' allows interrupts to be enabled via the specific enable bits listed above.. Write Operation:" "0: No effect.. Interrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0xC 6. "RHSC,Root Hub Status Change Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0xC 5. "FNO,Frame Number Overflow Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to FNO..,1: Interrupt generation due to FNO.."
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bitfld.long 0xC 3. "RD,Resume Detected Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0xC 2. "SF,Start of Frame Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to SF..,1: Interrupt generation due to SF.."
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bitfld.long 0xC 1. "WDH,Write Back Done Head Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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bitfld.long 0xC 0. "SO,Scheduling Overrun Enable Bit. Write Operation:" "0: No effect.. Interrupt generation due to SO..,1: Interrupt generation due to SO.."
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line.long 0x10 "HCINTERRUPTDISABLE,Host Controller Interrupt Disable Register"
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bitfld.long 0x10 31. "MIE,Master Interrupt Disable Bit. Global interrupt disable. Writing '1' to disable all interrupts.. Write Operation:" "0: No effect.. Interrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0x10 6. "RHSC,Root Hub Status Change Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
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bitfld.long 0x10 5. "FNO,Frame Number Overflow Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to FNO..,1: Interrupt generation due to FNO.."
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bitfld.long 0x10 3. "RD,Resume Detected Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to RD..,1: Interrupt generation due to RD.."
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bitfld.long 0x10 2. "SF,Start of Frame Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to SF..,1: Interrupt generation due to SF.."
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bitfld.long 0x10 1. "WDH,Write Back Done Head Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to WDH..,1: Interrupt generation due to WDH.."
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bitfld.long 0x10 0. "SO,Scheduling Overrun Disable Bit. Write Operation:" "0: No effect.. Interrupt generation due to SO..,1: Interrupt generation due to SO.."
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line.long 0x14 "HCHCCA,Host Controller Communication Area Register"
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hexmask.long.tbyte 0x14 8.--31. 1. "HCCA,Host Controller Communication Area. Pointer to indicate base address of the Host Controller Communication Area (HCCA)."
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line.long 0x18 "HCPERIODCURRENTED,Host Controller Period Current ED Register"
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hexmask.long 0x18 4.--31. 1. "PCED,Periodic Current ED. Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor."
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line.long 0x1C "HCCONTROLHEADED,Host Controller Control Head ED Register"
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hexmask.long 0x1C 4.--31. 1. "CHED,Control Head ED. Pointer to indicate physical address of the first Endpoint Descriptor of the Control list."
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line.long 0x20 "HCCONTROLCURRENTED,Host Controller Control Current ED Register"
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hexmask.long 0x20 4.--31. 1. "CCED,Control Current Head ED. Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list."
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line.long 0x24 "HCBULKHEADED,Host Controller Bulk Head ED Register"
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hexmask.long 0x24 4.--31. 1. "BHED,Bulk Head ED. Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list."
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line.long 0x28 "HCBULKCURRENTED,Host Controller Bulk Current ED Register"
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hexmask.long 0x28 4.--31. 1. "BCED,Bulk Current Head ED. Pointer to indicate the physical address of the current endpoint of the Bulk list."
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line.long 0x2C "HCDONEHEAD,Host Controller Done Head Register"
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hexmask.long 0x2C 4.--31. 1. "DH,Done Head. Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue."
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line.long 0x30 "HCFMINTERVAL,Host Controller Frame Interval Register"
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bitfld.long 0x30 31. "FIT,Frame Interval Toggle. This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0])." "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into FI.."
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hexmask.long.word 0x30 16.--30. 1. "FSMPS,FS Largest Data Packet. This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame."
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hexmask.long.word 0x30 0.--13. 1. "FI,Frame Interval. This field specifies the length of a frame as (bit times - 1). For 12 000 bit times in a frame a value of 11 999 is stored here."
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rgroup.long 0x38++0x7
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line.long 0x0 "HCFMREMAINING,Host Controller Frame Remaining Register"
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bitfld.long 0x0 31. "FRT,Frame Remaining Toggle. This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0." "0,1"
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hexmask.long.word 0x0 0.--13. 1. "FR,Frame Remaining. When the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period. When the count reaches 0 (end of frame) the counter reloads with Frame Interval. In addition the counter loads when.."
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line.long 0x4 "HCFMNUMBER,Host Controller Frame Number Register"
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hexmask.long.word 0x4 0.--15. 1. "FN,Frame Number. This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]). The count rolls over from 'FFFFh' to '0h.'"
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group.long 0x40++0x17
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line.long 0x0 "HCPERIODICSTART,Host Controller Periodic Start Register"
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hexmask.long.word 0x0 0.--13. 1. "PS,Periodic Start. This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin."
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line.long 0x4 "HCLSTHRESHOLD,Host Controller Low-speed Threshold Register"
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hexmask.long.word 0x4 0.--11. 1. "LST,Low-speed Threshold"
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line.long 0x8 "HCRHDESCRIPTORA,Host Controller Root Hub Descriptor A Register"
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bitfld.long 0x8 12. "NOCP,No over Current Protection. This bit describes how the over current status for the Root Hub ports reported." "0: Over current status is reported,1: Over current status is not reported"
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bitfld.long 0x8 11. "OCPM,over Current Protection Mode. This bit describes how the over current status for the Root Hub ports reported. This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared." "0: Global Over current,1: Individual Over current"
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bitfld.long 0x8 8. "PSM,Power Switching Mode. This bit is used to specify how the power switching of the Root Hub ports is controlled." "0: Global Switching,1: Individual Switching"
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hexmask.long.byte 0x8 0.--7. 1. "NDP,Number Downstream Ports. USB host control supports two downstream ports and only one port is available in this series of chip."
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line.long 0xC "HCRHDESCRIPTORB,Host Controller Root Hub Descriptor B Register"
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hexmask.long.word 0xC 16.--31. 1. "PPCM,Port Power Control Mask. Global power switching. This field is only valid if PowerSwitchingMode is set (individual port switching). When set the port only responds to individual port power switching commands (Set/ClearPortPower). When cleared the.."
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line.long 0x10 "HCRHSTATUS,Host Controller Root Hub Status Register"
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bitfld.long 0x10 31. "CRWE,Clear Remote Wake-up Enable Bit. This bit is use to clear DRWE (HcRhStatus[15]).. This bit always read as zero.. Write Operation:" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
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bitfld.long 0x10 17. "OCIC,over Current Indicator Change. This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).. Write 1 to clear this bit to zero." "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) change"
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bitfld.long 0x10 16. "LPSC,Set Global Power" "0: No effect,1: Set global power"
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bitfld.long 0x10 15. "DRWE,Device Remote Wakeup Enable Bit. This bit controls if port's Connect Status Change as a remote wake-up event.. Write Operation:" "0: No effect.. Connect Status Change as a remote..,1: Connect Status Change as a remote wake-up event.."
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bitfld.long 0x10 1. "OCI,over Current Indicator. This bit reflects the state of the over current status pin. This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared." "0: No over current condition,1: Over current condition"
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bitfld.long 0x10 0. "LPS,Clear Global Power" "0: No effect,1: Clear global power"
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line.long 0x14 "HCRHPORTSTATUS1,Host Controller Root Hub Port Status [1]"
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bitfld.long 0x14 20. "PRSC,Port Reset Status Change. This bit indicates that the port reset signal has completed.. Write 1 to clear this bit to zero." "0: Port reset is not complete,1: Port reset is complete"
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bitfld.long 0x14 19. "OCIC,Port over Current Indicator Change. This bit is set when POCI (HcRhPortStatus1[3]) changes.. Write 1 to clear this bit to zero." "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changes"
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bitfld.long 0x14 18. "PSSC,Port Suspend Status Change. This bit indicates the completion of the selective resume sequence for the port.. Write 1 to clear this bit to zero." "0: Port resume is not completed,1: Port resume completed"
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bitfld.long 0x14 17. "PESC,Port Enable Status Change. This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.. Write 1 to clear this bit to zero." "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
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bitfld.long 0x14 16. "CSC,Connect Status Change. This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).. Write 1 to clear this bit to zero." "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect event.."
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bitfld.long 0x14 9. "LSDA,Low Speed Device Attached (Read) or Clear Port Power (Write). This bit defines the speed (and bud idle) of the attached device. It is only valid when CCS (HcRhPortStatus1[0]) is set.. This bit is also used to clear port power.. Write Operation:" "0: No effect.. Full Speed device,1: Clear PPS (HcRhPortStatus1[8]).. Low-speed device"
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bitfld.long 0x14 8. "PPS,Port Power Status. This bit reflects the power state of the port regardless of the power switching mode.. Write Operation:" "0: No effect.. Port power is Diabled,1: Port Power Enabled.. Port power is Enabled"
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bitfld.long 0x14 4. "PRS,Port Reset Status. This bit reflects the reset state of the port.. Write Operation:" "0: No effect.. Port reset signal is not active,1: Set port reset.. Port reset signal is active"
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bitfld.long 0x14 3. "POCI,Port over Current Indicator (Read) or Clear Port Suspend (Write). This bit reflects the state of the over current status pin dedicated to this port. This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is.." "0: No effect.. No over current condition,1: Clear port suspend.. Over current condition"
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bitfld.long 0x14 2. "PSS,Port Suspend Status. This bit indicates the port is suspended. Write Operation:" "0: No effect.. Port is not suspended,1: Set port suspend.. Port is selectively suspended"
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bitfld.long 0x14 1. "PES,Port Enable Status. Write Operation:" "0: No effect.. Port Disabled,1: Set port enable.. Port Enabled"
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bitfld.long 0x14 0. "CCS,CurrentConnectStatus (Read) or ClearPortEnable Bit (Write). Write Operation:" "0: No effect.. No device connected,1: Clear port enable.. Device connected"
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group.long 0x200++0x7
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line.long 0x0 "HCPHYCONTROL,Host Controller PHY Control Regsiter"
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bitfld.long 0x0 27. "STBYEN,USB Transceiver Standby Enable Bit. This bit controls if USB transceiver could enter the standby mode to reduce power consumption." "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
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line.long 0x4 "HCMISCCONTROL,Host Controller Miscellaneous Control Register"
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bitfld.long 0x4 16. "DPRT1,Disable Port 1. This bit controls if the connection between USB host controller and transceiver of port 1 is disabled. If the connection is disabled the USB host controller will not recognize any event of USB bus.. Set this bit high the.." "0: The connection between USB host controller and..,1: The connection between USB host controller and.."
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bitfld.long 0x4 3. "OCAL,over Current Active Low. This bit controls the polarity of over current flag from external power IC." "0: Over current flag is high active,1: Over current flag is low active"
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bitfld.long 0x4 1. "ABORT,AHB Bus ERROR Response. This bit indicates there is an ERROR response received in AHB bus." "0: No ERROR response received,1: ERROR response received"
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40040000
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group.long 0x0++0x7
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line.long 0x0 "WDT_CTL,WDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control (Write Protect). WDT up counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect). These three bits select the time-out interval period for the WDT.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "WDTEN,WDT Enable Control (Write Protect). Note1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111 this bit is forced as 1 and user cannot.." "0: WDT Disabled (This action will reset the..,1: This bit is write protected"
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bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Control (Write Protect). If this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU. . Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag (Write Protect). This bit indicates the interrupt wake-up flag status of WDT. Note1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note2: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: This bit is write protected"
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bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect). If this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT time-out..,1: This bit is write protected"
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bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag. This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval. Note: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag. This bit indicates the system has been reset by WDT time-out reset or not.. Note: This bit is cleared by writing 1 to it." "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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newline
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bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Control (Write Protect). Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.. Note: This bit is write protected." "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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bitfld.long 0x0 0. "RSTCNT,Reset WDT Up Counter (Write Protect). Note1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note2: This bit will be automatically cleared by hardware." "0: No effect,1: This bit is write protected"
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line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect). When WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened. User can select a suitable setting of.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
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tree.end
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tree "WWDT (Window Watchdog Timer)"
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base ad:0x40040100
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wgroup.long 0x0++0x3
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line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register. Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x4++0x7
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line.long 0x0 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control. WWDT down counter will keep going no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare Register. Set this register to adjust the valid reload window. . Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT. If user writes WWDT_RLDCNT.."
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
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bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Control Bit. If this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Control Bit. Set this bit to enable WWDT counter counting." "0: WWDT counter is stopped,1: WWDT counter is starting counting"
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line.long 0x4 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset Flag. This bit indicates the system has been reset by WWDT time-out reset or not.. Note: This bit is cleared by writing 1 to it." "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag. This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).. Note: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0xC++0x3
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line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
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hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value. CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value."
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tree.end
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AUTOINDENT.OFF
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