8879 lines
952 KiB
Plaintext
8879 lines
952 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: M253 On-Chip Peripherals
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; @Props: Released
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; @Author: PIW
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; @Changelog: 2022-03-01 PIW
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: SVD generated, based on: M253.svd (Ver. 1.0)
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; @Core: Cortex-M23
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; @Chip: M253LD3AE, M253LE3AE, M253ZE3AE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm253.per 14426 2022-03-02 15:35:57Z kwisniewski $
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config 16. 8.
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main extension,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "BPWM"
|
|
base ad:0x4005A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
|
|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
|
|
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nNote: It is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x03
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line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: \nIn this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD"
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repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
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group.long ($2+0x50)++0x03
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line.long 0x00 "BPWM_CMPDAT$1,BPWM Comparator Register $1"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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repeat.end
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rgroup.long 0x90++0x03
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line.long 0x00 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is down counting,1: Counter is up counting"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period or Center Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter counts to 0" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin" "0: BPWM output pin polar inverse Disabled,1: BPWM output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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newline
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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newline
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM pin at tri-state,1: BPWM pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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newline
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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newline
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: Up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT is.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up counts and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC Enable Bit" "0: BPWM Channel 3 Trigger EADC function Disabled,1: BPWM Channel 3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC Enable Bit" "0: BPWM Channel 2 Trigger EADC function Disabled,1: BPWM Channel 2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count CMPDAT point,4: BPWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH3 up-count CMPDAT point,9: BPWM_CH3 down-count CMPDAT point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC Enable Bit" "0: BPWM Channel 1 Trigger EADC function Disabled,1: BPWM Channel 1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC Enable Bit" "0: BPWM Channel 0 Trigger EADC function Disabled,1: BPWM Channel 0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count CMPDAT point,4: BPWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH1 up-count CMPDAT point,9: BPWM_CH1 down-count CMPDAT point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC Enable Bit" "0: BPWM Channel 5 Trigger EADC function Disabled,1: BPWM Channel 5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC Enable Bit" "0: BPWM Channel 4 Trigger EADC function Disabled,1: BPWM Channel 4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count CMPDAT point,4: BPWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: BPWM_CH5 up-count CMPDAT point,9: BPWM_CH5 down-count CMPDAT point,?..."
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 20. "EADCTRG4,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 19. "EADCTRG3,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 18. "EADCTRG2,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 17. "EADCTRG1,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 16. "EADCTRG0,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event..,1: An EADC start of conversion trigger event.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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newline
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x250++0x03
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line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
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group.long 0x254++0x03
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line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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|
rgroup.long 0x304++0x03
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|
line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
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|
rgroup.long 0x31C++0x03
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|
line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x320++0x03
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|
line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x324++0x03
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|
line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x328++0x03
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|
line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x32C++0x03
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|
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
group.long 0x330++0x03
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|
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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|
tree.end
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|
tree "CANFD"
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|
base ad:0x40020000
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|
rgroup.long 0x0C++0x03
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|
line.long 0x00 "CANFD_DBTP,Data Bit Timing Prescaler Register (P*)"
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|
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation Disabled,1: Transmitter Delay Compensation Enabled"
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|
bitfld.long 0x00 16.--20. "DBRP,Data Bit Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
newline
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bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 0.--3. "DSJW,Data Re-Synchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x10++0x03
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line.long 0x00 "CANFD_TEST,Test Register (P*)"
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bitfld.long 0x00 7. "RX,Receive Pin\nMonitors the actual value of pin CANx_RXD" "0: The CAN bus is dominant (CANx_RXD = 0),1: The CAN bus is recessive (CANx_RXD = 1)"
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bitfld.long 0x00 5.--6. "TX,Control of Transmit Pin" "0: Reset value CANx_TXD controlled by the CAN..,1: Sample Point can be monitored at pin CANx_TXD,2: Dominant ('0') level at pin CANx_TXD,3: Recessive ('1') level at pin CANx_TXD"
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newline
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bitfld.long 0x00 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode Disabled,1: Loop Back Mode Enabled (refer to TEST Mode in.."
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rgroup.long 0x14++0x03
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line.long 0x00 "CANFD_RWD,RAM Watchdog (P*)"
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hexmask.long.byte 0x00 8.--15. 1. "WDV,Watchdog Value \nActual Message RAM Watchdog Counter Value"
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|
hexmask.long.byte 0x00 0.--7. 1. "WDC,Watchdog Configuration \nStart value of the Message RAM Watchdog Counter"
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|
group.long 0x18++0x03
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|
line.long 0x00 "CANFD_CCCR,CC Control Register (Pp*)"
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|
bitfld.long 0x00 15. "NISO,Non ISO Operation\nIf this bit is set the CAN FD controller uses the CAN FD frame format as speci ed by the Bosch CAN FD Speci cation V1.0" "0: CAN FD frame format according to ISO..,1: CAN FD frame format according to Bosch CAN FD.."
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bitfld.long 0x00 14. "TXP,Transmit Pause\nIf this bit is set the CAN FD controller pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (refer to Tx Handling section)" "0: Transmit pause Disabled,1: Transmit pause Enabled"
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bitfld.long 0x00 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering Disabled,1: Two consecutive dominant tq required to.."
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bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable\nNote: When protocol exception handling is disabled the controller will transmit an error frame when it detects a protocol exception condition" "0: Protocol exception handling Enabled,1: Protocol exception handling Disabled"
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newline
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bitfld.long 0x00 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions Disabled,1: Bit rate switching for transmissions Enabled"
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bitfld.long 0x00 8. "FDOE,FD Operation Enable" "0: FD operation Disabled,1: FD operation Enabled"
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newline
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bitfld.long 0x00 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset..,1: Test Mode write access to register TEST enabled"
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bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission Disabled"
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newline
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bitfld.long 0x00 5. "MON,Bus Monitoring Mode\nBit MON can only be set by the Host when both CCE and INIT are set to 1" "0: Bus Monitoring Mode Disabled,1: Bus Monitoring Mode Enabled"
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bitfld.long 0x00 4. "CSR,Clock Stop Request" "0: No clock stop is requested,1: Clock stop requested"
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newline
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bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: The Controller may be set in power down by.."
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bitfld.long 0x00 2. "ASM,Restricted Operation Mode\nBit ASM can only be set by the Host when both CCE and INIT are set to 1" "0: Normal CAN operation,1: Restricted Operation Mode active"
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newline
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bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
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bitfld.long 0x00 0. "INIT,Initialization\nNote: Due to the synchronization mechanism between the two clock domains there may be a delay until the value written to INIT can be read back" "0: Normal Operation,1: Initialization is started"
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rgroup.long 0x1C++0x03
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line.long 0x00 "CANFD_NBTP,Nominal Bit Timing Prescaler Register (P*)"
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hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal Re-Synchronization Jump Width"
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hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler\nThe value by which the oscillator frequency is divided for generating the bit time quanta"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time Segment before Sample Point"
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hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal Time Segment after Sample Point\nNote: With a CAN Core clock (cclk) of 8 MHz the reset value of 0x06000A03 configures the controller for a bit rate of 500 kBit/s"
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rgroup.long 0x20++0x03
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line.long 0x00 "CANFD_TSCC,Timestamp Counter Configuration (P*)"
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bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler\nCon gures the timestamp and timeout counters time unit in multiples of CAN bit times [ 1...16 ]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according..,2: Reserved,3: Same as '00'"
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rgroup.long 0x24++0x03
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line.long 0x00 "CANFD_TSCV,Timestamp Counter Value (C*)"
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hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter\nNote: A 'wrap around' is a change of the Timestamp Counter value from non-zero to 0 not caused by write access to CANFD_TSCV"
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rgroup.long 0x28++0x03
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line.long 0x00 "CANFD_TOCC,Timeout Counter Configuration (P*)"
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hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period\nStart value of the Timeout Counter (down-counter)"
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bitfld.long 0x00 1.--2. "TOS,Timeout Select\nWhen operating in Continuous mode a write to CANFD_TOCV presets the counter to the value con gured by CANFD_TOP (TOCC[31:16]) and continues down-counting" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
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newline
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bitfld.long 0x00 0. "ETOC,Enable Timeout Counter\nNote: For use of timeout function with CAN FD refer to Timeout Counter section" "0: Timeout Counter Disabled,1: Timeout Counter Enabled"
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rgroup.long 0x2C++0x03
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line.long 0x00 "CANFD_TOCV,Timeout Counter Value (C*)"
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hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter\nThe filed is decremented in multiples of CAN bit times [ 1...16 ] depending on the configuration of TCP (CANFD_TSCC[19:16])"
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rgroup.long 0x40++0x03
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line.long 0x00 "CANFD_ECR,Error Counter Register (X*)"
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hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging\nThe counter is incremented each time when a CAN protocol error causes the 8-bit Transmit Error Counter TEC or the 7-bit Receive Error Counter REC to be incremented"
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bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the.."
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newline
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hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter values between 0 and 127"
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hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter values between 0 and 255.\nNote: When ASM (CANFD_CCCR[2]) is set the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected but CEL is still.."
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rgroup.long 0x44++0x03
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line.long 0x00 "CANFD_PSR,Protocol Status Register (XS*)"
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hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value\nPosition of the secondary sample point de ned by the sum of the measured delay from CANx_TXD to CANx_RXD and TDCO (TDCR[[14:8]). The SSP position is in the data phase the number of minimum time quata (mtq).."
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bitfld.long 0x00 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since..,1: Protocol exception event occurred"
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newline
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bitfld.long 0x00 13. "RFDF,Received a CAN FD Message\nThis bit is set independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RFDF reading bytes 3/2/1 has no impact" "0: Since this bit was reset by the CPU no CAN FD..,1: Message in CAN FD format with FDF flag set.."
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bitfld.long 0x00 12. "RBRS,BRS flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering.\nNote: Byte access: Reading byte 0 will reset RBRS reading bytes 3/2/1 has no impact" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag.."
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newline
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bitfld.long 0x00 11. "RESI,ESI flag of last received CAN FD Message\nThis bit is set together with RFDF independent of acceptance filtering" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag.."
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bitfld.long 0x00 8.--10. "DLEC,Data Phase Last Error Code\nType of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 7. "BO,Bus_Off Status" "0: The CAN FD controller is not Bus_Off,1: The CAN FD controller is in Bus_Off state"
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bitfld.long 0x00 6. "EW,Warning Status" "0: Both error counters are below the..,1: At least one of error counter has reached the.."
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newline
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bitfld.long 0x00 5. "EP,Error Passive" "0: The CAN FD controller is in the Error_Active..,1: The CAN FD controller is in the Error_Passive.."
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bitfld.long 0x00 3.--4. "ACT,Activity\nMonitors the module's CAN communication state" "0: Synchronizing - node is synchronizing on CAN..,1: Idle - node is neither receiver nor transmitter,2: Receiver - node is operating as receiver,3: Transmitter - node is operating as transmitter"
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newline
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bitfld.long 0x00 0.--2. "LEC,Last Error Code\nThe LEC indicates the type of the last error to occur on the CAN bus" "0: No Error,1: Stuff Error,2: Form Error,3: AckError,4: Bit1Error,5: Bit0Error,6: CRCError,7: NoChange"
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rgroup.long 0x48++0x03
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line.long 0x00 "CANFD_TDCR,Transmitter Delay Compensation Register (P*)"
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hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation SSP Offset\nOffset value de ning the distance between the measured delay from CANx_TXD to CANx_RXD and the secondary sample point"
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hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length\nDe nes the minimum value for the SSP position dominant edges on CANx_RXD that would result in an earlier SSP position are ignored for transmitter delay measurement"
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group.long 0x50++0x03
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line.long 0x00 "CANFD_IR,Interrupt Register"
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bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
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bitfld.long 0x00 28. "PED,Protocol Error in Data Phase\nNote: Data bit time is used" "0: No protocol error in data phase,1: Protocol error in data phase detected (DLEC.."
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newline
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bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase\nNote: Nominal bit time is used" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
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bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
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newline
|
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bitfld.long 0x00 25. "BO,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
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bitfld.long 0x00 24. "EW,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
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newline
|
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bitfld.long 0x00 23. "EP,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
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bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
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newline
|
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bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer\nThe flag is set whenever a received message has been stored into a dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into an.."
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bitfld.long 0x00 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
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newline
|
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bitfld.long 0x00 17. "MRAF,Message RAM Access Failure\nThe flag is set when the Rx Handler\n Has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
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bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
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newline
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bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after.."
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bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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newline
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bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO ll level below watermark,1: Tx Event FIFO ll level reached watermark"
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bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
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newline
|
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bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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newline
|
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bitfld.long 0x00 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
|
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bitfld.long 0x00 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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newline
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bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
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bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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newline
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bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 ll level below watermark,1: Rx FIFO 1 ll level reached watermark"
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bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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newline
|
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bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
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bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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newline
|
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bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 ll level below watermark,1: Rx FIFO 0 ll level reached watermark"
|
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bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
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group.long 0x54++0x03
|
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line.long 0x00 "CANFD_IE,Interrupt Enable"
|
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bitfld.long 0x00 29. "ARAE,Access to Reserved Address Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x00 28. "PEDE,Protocol Error in Data Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 26. "WDIE,Watchdog Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 25. "BOE,Bus_Off Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 24. "EWE,Warning Status Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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newline
|
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bitfld.long 0x00 23. "EPE,Error Passive Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 22. "ELOE,Error Logging Overflow Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 20. "BECE,Bit Error Corrected Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 18. "TOOE,Timeout Occurred Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 9. "TCE,Transmission Completed Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 8. "HPME,High Priority Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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newline
|
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bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CANFD_ILS,Interrupt Line Select"
|
|
bitfld.long 0x00 29. "ARAL,Access to Reserved Address Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 28. "PEDL,Protocol Error in Data Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 27. "PEAL,Protocol Error in Arbitration Phase Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 26. "WDIL,Watchdog Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
|
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bitfld.long 0x00 25. "BOL,Bus_Off Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 24. "EWL,Warning Status Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
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bitfld.long 0x00 23. "EPL,Error Passive Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 22. "ELOL,Error Logging Overflow Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
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bitfld.long 0x00 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 18. "TOOL,Timeout Occurred Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 16. "TSWL,Timestamp Wraparound Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
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bitfld.long 0x00 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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newline
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bitfld.long 0x00 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 11. "TFEL,Tx FIFO Empty Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
newline
|
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bitfld.long 0x00 9. "TCL,Transmission Completed Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 8. "HPML,High Priority Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
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|
newline
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bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0: Interrupt assigned to CAN interrupt line 0,1: Interrupt assigned to CAN interrupt line 1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CANFD_ILE,Interrupt Line Enable"
|
|
bitfld.long 0x00 1. "ENT1,Enable Interrupt Line 1" "0: Interrupt line canfd_int1 Disabled,1: Interrupt line canfd_int1 Enabled"
|
|
bitfld.long 0x00 0. "ENT0,Enable Interrupt Line 0" "0: Interrupt line canfd_int0 Disabled,1: Interrupt line canfd_int0 Enabled"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "CANFD_GFC,Global Filter Configuration (P*)"
|
|
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard\nDe nes how received messages with 11-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended\nDe nes how received messages with 29-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
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bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard.."
|
|
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended.."
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "CANFD_SIDFC,Standard ID Filter Configuration (P*)"
|
|
hexmask.long.byte 0x00 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address\nStart address of standard Message ID filter list (32-bit word address refer to Figure 6.2011)"
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "CANFD_XIDFC,Extended ID Filter Configuration (P*)"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address\nStart address of extended Message ID filter list (32-bit word address refer to Figure 6.2011)"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "CANFD_XIDAM,Extended ID AND Mask (P*)"
|
|
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask\nFor acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
|
|
rgroup.long 0x94++0x03
|
|
line.long 0x00 "CANFD_HPMS,High Priority Message Status"
|
|
bitfld.long 0x00 15. "FLST,Filter List\nIndicates the filter list of the matching filter element" "0: Standard Filter List,1: Extended Filter List"
|
|
hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter Index\nIndex of matching filter element"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x00 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CANFD_NDAT1,New Data 1"
|
|
hexmask.long 0x00 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 0 to 31"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CANFD_NDAT2,New Data 2"
|
|
hexmask.long 0x00 0.--31. 1. "NDn,New Data\nThe register holds the New Data flags of Rx Buffers 32 to 63"
|
|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "CANFD_RXF0C,Rx FIFO 0 Configuration (P*)"
|
|
bitfld.long 0x00 31. "F0OM,FIFO 0 Operation Mode\nFIFO 0 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
|
|
hexmask.long.byte 0x00 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
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hexmask.long.byte 0x00 16.--22. 1. "F0S,Rx FIFO 0 Size\nThe Rx FIFO 0 elements are indexed from 0 to F0S-1"
|
|
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address\nStart address of Rx FIFO 0 in Message RAM (32-bit word address)"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "CANFD_RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost" "?,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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|
newline
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bitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 Put Index\nRx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 Get Index\nRx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level\nNumber of elements stored in Rx FIFO 0 range 0 to 64"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CANFD_RXF0A,Rx FIFO 0 Acknowledge"
|
|
bitfld.long 0x00 0.--5. "F0A,Rx FIFO 0 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CANFD_RXBC,Rx Buffer Configuration (P*)"
|
|
hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address\nCon gures the start address of the Rx Buffers section in the Message RAM (32-bit word address)"
|
|
rgroup.long 0xB0++0x03
|
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line.long 0x00 "CANFD_RXF1C,Rx FIFO 1 Configuration (P*)"
|
|
bitfld.long 0x00 31. "F1OM,FIFO 1 Operation Mode\nFIFO 1 can be operated in blocking or in overwrite mode (refer to Rx FIFOs)" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
|
|
hexmask.long.byte 0x00 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
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hexmask.long.byte 0x00 16.--22. 1. "F1S,Rx FIFO 1 Size\nThe Rx FIFO 1 elements are indexed from 0 to F1S - 1"
|
|
hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address\nStart address of Rx FIFO 1 in Message RAM (32-bit word address refer to Figure 6.2011)"
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "CANFD_RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x00 25. "RF1L,Rx FIFO 1 Message Lost" "?,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
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bitfld.long 0x00 16.--21. "F1P,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "F1G,Rx FIFO 1 Get Index\nRx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
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hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level\nNumber of elements stored in Rx FIFO 1 range 0 to 64"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CANFD_RXF1A,Rx FIFO 1 Acknowledge"
|
|
bitfld.long 0x00 0.--5. "F1A,Rx FIFO 1 Acknowledge Index\nAfter the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "CANFD_RXESC,Rx Buffer / FIFO Element Size Configuration (P*)"
|
|
bitfld.long 0x00 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "F0DS,Rx FIFO 0 Data Field Size\nNote: In case the data field size of an accepted CAN frame exceeds the data field size configured for the matching Rx Buffer or Rx FIFO only the number of bytes as configured by CANFD_RXESC are stored to the Rx Buffer resp" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "CANFD_TXBC,Tx Buffer Configuration (P*)"
|
|
bitfld.long 0x00 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
|
|
bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/Queue Size" "0: No Tx FIFO/Queue,?..."
|
|
newline
|
|
bitfld.long 0x00 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0: No Dedicated Tx Buffers,?..."
|
|
hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address\nStart address of Tx Buffers section in Message RAM (32-bit word address refer to Figure 6.2011).\nNote: The sum of TFQS and NDTB may be not greater than 32"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CANFD_TXFQS,Tx FIFO/Queue Status"
|
|
bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
|
|
bitfld.long 0x00 16.--20. "TFQP,Tx FIFO/Queue Put Index\nTx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 8.--12. "TFG,Tx FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--5. "TFFL,Tx FIFO Free Level\nNote: In case of mixed configurations where dedicated Tx Buffers are combined with a Tx FIFO or a Tx Queue the Put and Get Indices indicate the number of the Tx Buffer starting with the first dedicated Tx Buffers.\nExample: For.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "CANFD_TXESC,Tx Buffer Element Size Configuration (P*)"
|
|
bitfld.long 0x00 0.--2. "TBDS,Tx Buffer Data Field Size\nNote: In case the data length code DLC of a Tx Buffer element is configured to a value higher than the Tx Buffer data field size CANFD_TXESC.TBDS the bytes not defined by the Tx Buffer are transmitted as 0xCC (padding.." "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
rgroup.long 0xCC++0x03
|
|
line.long 0x00 "CANFD_TXBRP,Tx Buffer Request Pending"
|
|
hexmask.long 0x00 0.--31. 1. "TRPn,Transmission Request PendingEach Tx Buffer has its own Transmission Request Pending bit The bits are set via register CANFD_TXBAR The bits are reset after a requested transmission has completed or has been cancelled via register.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CANFD_TXBAR,Tx Buffer Add Request"
|
|
hexmask.long 0x00 0.--31. 1. "ARn,Add RequestEach Tx Buffer has its own Add Request bit Writing a 1 will set the corresponding Add Request bit writing a 0 has no impact This enables the Host to set transmission requests for multiple Tx Buffers with one write to CANFD_TXBAR.."
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CANFD_TXBCR,Tx Buffer Cancellation Request"
|
|
hexmask.long 0x00 0.--31. 1. "CRn,Cancellation Request\nEach Tx Buffer has its own Cancellation Request bit"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "CANFD_TXBTO,Tx Buffer Transmission Occurred"
|
|
hexmask.long 0x00 0.--31. 1. "TOn,Transmission Occurred\nEach Tx Buffer has its own Transmission Occurred bit"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "CANFD_TXBCF,Tx Buffer Cancellation Finished"
|
|
hexmask.long 0x00 0.--31. 1. "CFn,Cancellation Finished\nEach Tx Buffer has its own Cancellation Finished bit"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CANFD_TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
hexmask.long 0x00 0.--31. 1. "TIEn,Transmission Interrupt Enable\nEach Tx Buffer has its own Transmission Interrupt Enable bit"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CANFD_TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
hexmask.long 0x00 0.--31. 1. "CFIEn,Cancellation Finished Interrupt Enable\nEach Tx Buffer has its own Cancellation Finished Interrupt Enable bit"
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "CANFD_TXEFC,Tx Event FIFO Configuration (P*)"
|
|
bitfld.long 0x00 24.--29. "EFWN,Event FIFO Watermark" "0: Watermark interrupt Disabled,?..."
|
|
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size\nThe Tx Event FIFO elements are indexed from 0 to EFS - 1" "0: Tx Event FIFO Disabled,?..."
|
|
newline
|
|
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address\nStart address of Tx Event FIFO in Message RAM (32-bit word address refer to Figure 6.2011)"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "CANFD_TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost\nThis bit is a copy of interrupt flag TEFL (CANFD_IR[15])" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after.."
|
|
bitfld.long 0x00 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "EFP,Event FIFO Put Index\nTx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--12. "EFG,Event FIFO Get Index\nTx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "EFFL,Event FIFO Fill Level\nNumber of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CANFD_TXEFA,Tx Event FIFO Acknowledge"
|
|
bitfld.long 0x00 0.--4. "EFA,Event FIFO Acknowledge Index\nAfter the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
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tree "CLK"
|
|
base ad:0x40000200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x00 20.--22. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nThis is a protected register" "0: HXT frequency 1~4 MHz,1: HXT frequency 4~8 MHz,2: HXT frequency 8~12 MHz,3: HXT frequency 12~ 16 MHz,4: HXT frequency 16~24 MHz,5: HXT frequency 24~32 MHz,6: HXT frequency 24~32 MHz,7: HXT frequency 24~32 MHz"
|
|
bitfld.long 0x00 19. "MIRCEN,MIRC Enable Bit (Write Protect)" "0: 4 MHz internal high speed RC oscillator..,1: 4 MHz internal high speed RC oscillator.."
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|
newline
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bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled chip enters Power-down mode immediately after the PDEN bit set" "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instantly or wait.."
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|
bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred" "0,1"
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newline
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bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\n" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
|
|
bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~32.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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newline
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bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\n" "0: 38.4 kHz internal low speed RC oscillator..,1: 38.4 kHz internal low speed RC oscillator.."
|
|
bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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|
newline
|
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bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\n" "0: 32.768 kHz external low speed crystal (LXT)..,1: 32.768 kHz external low speed crystal (LXT).."
|
|
bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\n" "0: 4~32 MHz external high speed crystal (HXT)..,1: 4~32 MHz external high speed crystal (HXT).."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x00 29. "GPFCKEN,GPIOF Clock Enable Bit" "0: GPIOF port clock Disabled,1: GPIOF port clock Enabled"
|
|
bitfld.long 0x00 26. "GPCCKEN,GPIOC Clock Enable Bit" "0: GPIOC port clock Disabled,1: GPIOC port clock Enabled"
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|
newline
|
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bitfld.long 0x00 25. "GPBCKEN,GPIOB Clock Enable Bit" "0: GPIOB port clock Disabled,1: GPIOB port clock Enabled"
|
|
bitfld.long 0x00 24. "GPACKEN,GPIOA Clock Enable Bit" "0: GPIOA port clock Disabled,1: GPIOA port clock Enabled"
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|
newline
|
|
bitfld.long 0x00 23. "CANFD0CKEN,CANFD0 Clock Enable Bit" "0: CANFD0 clock Disabled,1: CANFD0 clock Enabled"
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|
bitfld.long 0x00 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE..,1: FMC clock Enabled when chip is under IDLE.."
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newline
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bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
|
|
bitfld.long 0x00 4. "EXSTCKEN,External System Tick Clock Enable Bit" "0: External System tick clock Disabled,1: External System tick clock Enabled"
|
|
newline
|
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bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
|
|
bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
|
|
bitfld.long 0x00 28. "EADCCKEN,Enhanced Analog-digital-converter (EADC) Clock Enable Bit" "0: EADC clock Disabled,1: EADC clock Enabled"
|
|
bitfld.long 0x00 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
|
|
bitfld.long 0x00 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
|
|
newline
|
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bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
|
|
bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
|
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newline
|
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bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
|
|
bitfld.long 0x00 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
|
|
newline
|
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bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
|
|
bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
|
|
newline
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bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
|
|
bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
|
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newline
|
|
bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
|
|
bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
|
|
newline
|
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bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
|
|
bitfld.long 0x00 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock" "0: RTC clock Disabled,1: RTC clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\n" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
|
|
bitfld.long 0x00 18. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
|
|
bitfld.long 0x00 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
|
|
bitfld.long 0x00 24. "CANFD0SEL,CANFD0 Clock Source Selection" "0: Clock source from HCLK,1: Clock source from HXT"
|
|
bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M23 SysTick Clock Source Selection (Write Protect)\n" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2"
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|
newline
|
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\n" "0: Clock source from HXT,1: Clock source from LXT,?,3: Clock source from LIRC,?,5: Clock source from MIRC,?,7: Clock source from HIRC"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
|
|
bitfld.long 0x00 28.--30. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,?,2: Clock source from 32.768 kHz external low..,3: Clock source from 48 MHz internal high speed..,4: Clock source from PCLK1,5: Clock source from 38.4 kHz internal low speed..,?..."
|
|
bitfld.long 0x00 24.--26. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,?,2: Clock source from 32.768 kHz external low..,3: Clock source from 48 MHz internal high speed..,4: Clock source from PCLK0,5: Clock source from 38.4 kHz internal low speed..,?..."
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|
newline
|
|
bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock T3 pin,?,5: Clock source from 38.4 kHz internal low speed..,?,7: Clock source from 48 MHz internal high speed.."
|
|
bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock T2 pin,?,5: Clock source from 38.4 kHz internal low speed..,?,7: Clock source from 48 MHz internal high speed.."
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|
newline
|
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock T1 pin,?,5: Clock source from 38.4 kHz internal low speed..,?,7: Clock source from 48 MHz internal high speed.."
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|
bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock T0 pin,?,5: Clock source from 38.4 kHz internal low speed..,?,7: Clock source from 48 MHz internal high speed.."
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newline
|
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bitfld.long 0x00 4.--6. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from 48 MHz internal high speed..,4: Clock source from 38.4 kHz internal low speed..,5: Clock source from 4 MHz internal medium speed..,?,7: Clock source from USB SOF"
|
|
bitfld.long 0x00 2.--3. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)" "?,?,2: Clock source from HCLK/2048,3: Clock source from 38.4 kHz internal low speed.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\n" "0: Reserved,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK/2048,3: Clock source from 38.4 kHz internal low speed.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
|
|
bitfld.long 0x00 4.--5. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,1: Reserved,2: Clock source from PCLK1,3: Clock source from 48 MHz internal high speed.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
|
|
bitfld.long 0x00 28.--30. "UART3SEL,UART3 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,?,2: Clock source from 32.768 kHz external low..,3: Clock source from 48 MHz internal high speed..,4: Clock source from PCLK1,5: Clock source from 38.4 kHz internal low speed..,?..."
|
|
bitfld.long 0x00 24.--26. "UART2SEL,UART2 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,?,2: Clock source from 32.768 kHz external low..,3: Clock source from 48 MHz internal high speed..,4: Clock source from PCLK0,5: Clock source from 38.4 kHz internal low speed..,?..."
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|
newline
|
|
bitfld.long 0x00 4.--6. "UART4SEL,UART4 Clock Source Selection" "0: Clock source from 4~32 MHz external high..,?,2: Clock source from 32.768 kHz external low..,3: Clock source from 48 MHz internal high speed..,4: Clock source from PCLK0,5: Clock source from 38.4 kHz internal low speed..,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "EADCDIV,EADC Clock Divide Number From EADC Clock Source"
|
|
bitfld.long 0x00 12.--15. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source\nNote: This field is only reset by power on reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CLK_CLKDIV4,Clock Divider Number Register 4"
|
|
bitfld.long 0x00 16.--17. "CANFD0DIV,CANFD0 Clock Divide Number From CANFD0 Clock Source" "0,1,2,3"
|
|
bitfld.long 0x00 8.--11. "UART4DIV,UART4 Clock Divide Number From UART4 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "UART3DIV,UART3 Clock Divide Number From UART3 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "UART2DIV,UART2 Clock Divide Number From UART2 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register"
|
|
bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
|
|
bitfld.long 0x00 6. "MIRCSTB,MIRC Clock Source Stable Flag (Read Only)" "0: 4 MHz internal mid speed RC oscillator (MIRC)..,1: 4 MHz internal mid speed RC oscillator (MIRC).."
|
|
newline
|
|
bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
|
|
bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 38.4 kHz internal low speed RC oscillator..,1: 38.4 kHz internal low speed RC oscillator.."
|
|
newline
|
|
bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register"
|
|
bitfld.long 0x00 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
|
|
bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
|
|
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
newline
|
|
bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
|
bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register"
|
|
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
|
bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: 4~32 MHz external high speed crystal..,1: 4~32 MHz external high speed crystal.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag will.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CLK_PMUCTL,Power Manager Control Register"
|
|
bitfld.long 0x00 0.--2. "PDMSEL,Power-down Mode Selection (Write Protect)\nThis is a protected register" "0: Power-down mode is selected,?,2: fast wake up,?,?,?,6: Deep Power-down mode is selected (DPD),?..."
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CLK_HXTFSEL,HXT Filter Select Control Register"
|
|
bitfld.long 0x00 0. "HXTFSEL,HXT Filter Select \n" "0: HXT frequency is greater than 12 MHz,1: HXT frequency is less than or equal to 12 MHz"
|
|
tree.end
|
|
tree "CRC"
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.."
|
|
newline
|
|
bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result"
|
|
tree.end
|
|
tree "EADC"
|
|
base ad:0x40043000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "EADC_DAT0,ADC Data Register 0 for Sample Module 0"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EADC_DAT1,ADC Data Register 1 for Sample Module 1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EADC_DAT2,ADC Data Register 2 for Sample Module 2"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "EADC_DAT3,ADC Data Register 3 for Sample Module 3"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EADC_DAT16,ADC Data Register 16 for Sample Module 16"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EADC_DAT17,ADC Data Register 17 for Sample Module 17"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
|
|
rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "EADC_CURDAT,EADC PDMA Current Transfer Data Register"
|
|
hexmask.long.tbyte 0x00 0.--18. 1. "CURDAT,EADC PDMA Current Transfer Data (Read Only)\nNote: After PDMA reads this register the VAILD of the shadow EADC_DAT register will be automatically cleared"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "EADC_CTL,ADC Control Register"
|
|
bitfld.long 0x00 5. "EADCIEN3,Specific Sample Module ADC ADINT3 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT3 interrupt..,1: Specific sample module ADC ADINT3 interrupt.."
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|
bitfld.long 0x00 4. "EADCIEN2,Specific Sample Module ADC ADINT2 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT2 interrupt..,1: Specific sample module ADC ADINT2 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 3. "EADCIEN1,Specific Sample Module ADC ADINT1 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT1 interrupt..,1: Specific sample module ADC ADINT1 interrupt.."
|
|
bitfld.long 0x00 2. "EADCIEN0,Specific Sample Module ADC ADINT0 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT0 interrupt..,1: Specific sample module ADC ADINT0 interrupt.."
|
|
newline
|
|
bitfld.long 0x00 1. "EADCRST,EADC ADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset" "0: No effect,1: Cause EADC control circuits reset to initial.."
|
|
bitfld.long 0x00 0. "EADCEN,ADC Converter Enable Bit\nNote: Before starting ADC conversion function this bit should be set to 1" "0: Disabled EADC,1: Enabled EADC"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "EADC_SWTRG,ADC Sample Module Software Start Register"
|
|
bitfld.long 0x00 16.--17. "INTSWTRG,ADC Sample Module 16 17 Software Force to Start EADC Conversion\nNote: INTSWTRG is only for internal channels" "0: No effect,1: Cause an EADC conversion when the priority is..,?..."
|
|
bitfld.long 0x00 0.--3. "SWTRG,ADC Sample Module 0~3 Sample Module 16 17 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion the EADC_PENDSTS register will show which sample module will conversion" "0: No effect,1: Cause an EADC conversion when the priority is..,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "EADC_PENDSTS,ADC Sample Module Start of Conversion Pending Flag Register"
|
|
bitfld.long 0x00 16.--17. "INTSTPF,ADC Sample Module 17 16 Start of Conversion Pending Flag\nRead Operation" "0: There is no pending conversion for sample..,1: Sample module EADC start of conversion is..,?..."
|
|
bitfld.long 0x00 0.--3. "STPF,ADC Sample Module 0~3 Start of Conversion Pending Flag\nRead Operation" "0: There is no pending conversion for sample..,1: Sample module EADC start of conversion is..,?..."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "EADC_OVSTS,ADC Sample Module Start of Conversion Overrun Flag Register"
|
|
bitfld.long 0x00 16.--17. "INTSPOVF,ADC SAMPLE16 17 Overrun Flag\nNote: This bit is cleared by writing 1 to it" "0: No sample module event overrun,1: Indicates a new sample module event is..,?..."
|
|
bitfld.long 0x00 0.--3. "SPOVF,ADC SAMPLE0~3 Overrun Flag\nNote: This bit is cleared by writing 1 to it" "0: No sample module event overrun,1: Indicates a new sample module event is..,?..."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "EADC_SCTL0,ADC Sample Module 0 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1 trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "EADC_SCTL1,ADC Sample Module 1 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1 trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "EADC_SCTL2,ADC Sample Module 2 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1 trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "EADC_SCTL3,ADC Sample Module 3 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
|
bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time\nNote: If TRGDLYCNT is set to 1 trigger delay time is actually the same as TRGDLYCNT is set to 2 for hardware operation"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: EADC_CLK/1,1: EADC_CLK/2,2: EADC_CLK/4,3: EADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "EADC_SCTL16,ADC Sample Module 16 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "EADC_SCTL17,ADC Sample Module 17 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,EADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "EADC_INTSRC0,EADC Interrupt 0 Source Enable Control Register"
|
|
bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
|
|
bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "EADC_INTSRC1,EADC Interrupt 1 Source Enable Control Register"
|
|
bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
|
|
bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "EADC_INTSRC2,EADC Interrupt 2 Source Enable Control Register"
|
|
bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
|
|
bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "EADC_INTSRC3,EADC Interrupt 3 Source Enable Control Register"
|
|
bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
|
|
bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0xE0)++0x03
|
|
line.long 0x00 "EADC_CMP$1,ADC Result Compare Register $1"
|
|
hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
|
|
bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: EADCMPF0 (EADC_STATUS2[4]) will be set when..,1: EADCMPF0 (EADC_STATUS2[4]) will be set when.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
|
|
bitfld.long 0x00 1. "EADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "EADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
|
|
repeat.end
|
|
rgroup.long 0xF0++0x03
|
|
line.long 0x00 "EADC_STATUS0,ADC Status Register 0"
|
|
bitfld.long 0x00 16.--19. "OV,EADC_DAT0~3 Overrun Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "VALID,EADC_DAT0~3 Data Valid Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xF4++0x03
|
|
line.long 0x00 "EADC_STATUS1,ADC Status Register 1"
|
|
bitfld.long 0x00 16.--17. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3"
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bitfld.long 0x00 0.--2. "VALID,EADC_DAT16~17 Data Valid Flag" "0,1,2,3,4,5,6,7"
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group.long 0xF8++0x03
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line.long 0x00 "EADC_STATUS2,ADC Status Register 2"
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bitfld.long 0x00 27. "AOV,All Sample Module ADC Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVn Flag is equal to 1" "0: None of sample module data register overrun..,1: Any one of sample module data register.."
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bitfld.long 0x00 26. "AVALID,All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1" "0: None of sample module data register valid..,1: Any one of sample module data register valid.."
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bitfld.long 0x00 25. "STOVF,All ADC Sample Module Start of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFn or INTSPOVFn Flag is equal to 1" "0: None of sample module event overrun flag..,1: Any one of sample module event overrun flag.."
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bitfld.long 0x00 24. "ADOVIF,All ADC Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1" "0: None of ADINT interrupt flag ADOVIFn..,1: Any one of ADINT interrupt flag ADOVIFn.."
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rbitfld.long 0x00 23. "BUSY,ADC Converter Busy/Idle Status (Read Only)\nNote: Once a trigger source is coming this bit must wait 2 EADC_CLK synchronization then the BUSY status will be high" "0: EADC is in idle state,1: EADC is busy for sample or conversion"
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rbitfld.long 0x00 16.--20. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 15. "EADCMPO3,EADC Compare 3 Output Status\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT is less than..,1: Conversion result in EADC_DAT is greater than.."
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bitfld.long 0x00 14. "EADCMPO2,EADC Compare 2 Output Status\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT is less than..,1: Conversion result in EADC_DAT is greater than.."
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bitfld.long 0x00 13. "EADCMPO1,EADC Compare 1 Output Status\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT is less than..,1: Conversion result in EADC_DAT is greater than.."
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bitfld.long 0x00 12. "EADCMPO0,EADC Compare 0 Output Status\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT is less than..,1: Conversion result in EADC_DAT is greater than.."
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bitfld.long 0x00 11. "ADOVIF3,ADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x00 10. "ADOVIF2,ADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is overwritten to 1"
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bitfld.long 0x00 9. "ADOVIF1,ADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x00 8. "ADOVIF0,ADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x00 7. "EADCMPF3,EADC Compare 3 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x00 6. "EADCMPF2,EADC Compare 2 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x00 5. "EADCMPF1,EADC Compare 1 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x00 4. "EADCMPF0,EADC Compare 0 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x00 3. "ADIF3,ADC ADINT3 Interrupt Flag\n" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse has been received"
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bitfld.long 0x00 2. "ADIF2,ADC ADINT2 Interrupt Flag\n" "0: No ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse has been received"
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bitfld.long 0x00 1. "ADIF1,ADC ADINT1 Interrupt Flag\n" "0: No ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
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bitfld.long 0x00 0. "ADIF0,ADC ADINT0 Interrupt Flag\n" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse has been received"
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rgroup.long 0xFC++0x03
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line.long 0x00 "EADC_STATUS3,ADC Status Register 3"
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bitfld.long 0x00 0.--4. "CURSPL,EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle the bit filed will be set to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x110++0x03
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line.long 0x00 "EADC_PWRCTL,EADC Power Management Control Register"
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bitfld.long 0x00 20.--23. "AUTOPDTHT,Auto Power Down Threshold Time" "?,?,?,?,?,?,?,7: 8 EADC clock for power down threshold time,8: 16 EADC clock for power down threshold time,9: 32 EADC clock for power down threshold time,10: 64 EADC clock for power down threshold time,11: 128 EADC clock for power down threshold time,12: 256 EADC clock for power down threshold time,?..."
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hexmask.long.word 0x00 8.--19. 1. "STUPT,EADC Start-up Time\nSet this bit fields to adjust start-up time"
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bitfld.long 0x00 5. "AUTOFF,Auto Off Mode" "0: Auto off function Disabled,1: Auto off function Enabled"
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rbitfld.long 0x00 0. "READY,EADC Start-up Completely and Ready for Conversion (Read Only)" "0: Power-on sequence is still in progress,1: EADC is ready for conversion"
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group.long 0x130++0x03
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line.long 0x00 "EADC_PDMACTL,EADC PDMA Control Register"
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bitfld.long 0x00 16.--17. "INTPDMATEN,PDMA Transfer Enable Bit for Internal Channel\nWhen EADC conversion is completed the converted data is loaded into EADC_DATn (n:17 16) register user can enable this bit to generate a PDMA data transfer request" "0: PDMA data transfer Disabled,1: PDMA data transfer Enabled,?..."
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bitfld.long 0x00 0.--3. "PDMATEN,PDMA Transfer Enable Bit for External Channel\nWhen EADC conversion is completed the converted data is loaded into EADC_DATn (n:0 ~ 3) register user can enable this bit to generate a PDMA data transfer request" "0: PDMA data transfer Disabled,1: PDMA data transfer Enabled,?..."
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group.long 0x140++0x03
|
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line.long 0x00 "EADC_M0CTL1,EADC Sample Module0 Control Register 1"
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bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
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group.long 0x144++0x03
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line.long 0x00 "EADC_M1CTL1,EADC Sample Module1 Control Register 1"
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bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
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group.long 0x148++0x03
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line.long 0x00 "EADC_M2CTL1,EADC Sample Module2 Control Register 1"
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bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
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group.long 0x14C++0x03
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line.long 0x00 "EADC_M3CTL1,EADC Sample Module3 Control Register 1"
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bitfld.long 0x00 4.--7. "ACU,Number of Accumulated Conversion Results Selection" "0: 1 conversion result will be accumulated,1: 2 conversion result will be accumulated,2: 4 conversion result will be accumulated,3: 8 conversion result will be accumulated,4: 16 conversion result will be accumulated,5: 32 conversion result will be accumulated,6: 64 conversion result will be accumulated,7: 128 conversion result will be accumulated,8: 256 conversion result will be accumulated,?..."
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bitfld.long 0x00 1. "AVG,Average Mode Selection" "0: Conversion results will be stored in data..,1: Conversion results in data register will be.."
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bitfld.long 0x00 0. "ALIGN,Alignment Selection" "0: The conversion result will be right aligned..,1: The conversion result will be left aligned in.."
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group.long 0x208++0x03
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line.long 0x00 "EADC_OFFSETCAL,ADC Result Offset Cancellation Register"
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bitfld.long 0x00 0.--4. "OFFSETCANCEL,ADC Offset Cancellation Trim Bits\nWhen CALEN(EADC_CTL[8]) is set to 1 the offset cancellation trim bits will compensate ADC result offset" "?,1: These 5 bits trim value wouldn't latched into,2: OFFSETCANCEL is signed format,?..."
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tree.end
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tree "FMC"
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base ad:0x4000C000
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group.long 0x00++0x03
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line.long 0x00 "FMC_ISPCTL,ISP Control Register"
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bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself.." "0,1"
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bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
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newline
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bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\n/clear this bit to select next booting from LDROM/APROM respectively" "0: Booting from APROM,1: Booting from LDROM"
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bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "FMC_ISPADDR,ISP Address Register"
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hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe NuMicro M23 series is equipped with embedded Flash"
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group.long 0x08++0x03
|
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line.long 0x00 "FMC_ISPDAT,ISP Data Register"
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hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
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group.long 0x0C++0x03
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line.long 0x00 "FMC_ISPCMD,ISP Command Register"
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hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid"
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group.long 0x10++0x03
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line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register"
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bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write-protected" "0: ISP operation is finished,1: ISP is progressed"
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group.long 0x18++0x03
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line.long 0x00 "FMC_FTCTL,Flash Access Time Control Register"
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bitfld.long 0x00 9. "CACHEINV,Flash Cache Invalidation (Write Protect)\n" "0: Flash Cache Invalidation finished (default),1: Flash Cache Invalidation"
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group.long 0x40++0x03
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line.long 0x00 "FMC_ISPSTS,ISP Status Register"
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hexmask.long.tbyte 0x00 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF}.\nVECMAP [18:12] should be 0"
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bitfld.long 0x00 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash.."
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newline
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bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
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rbitfld.long 0x00 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification" "0: Flash Program is success,1: Flash Program is fail"
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rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset or system reset is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode"
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rbitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])" "0: ISP operation is finished,1: ISP is progressed"
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group.long 0x4C++0x03
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line.long 0x00 "FMC_CYCCTL,Flash Access Cycle Control Register"
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bitfld.long 0x00 0.--3. "CYCLE,Flash Access Cycle Control (Write Protect) \nThe optimized HCLK working frequency range is 33~50 MHz\nNote: This bit is write protected" "?,1: CPU access with zero wait cycle if cache hit..,2: CPU access with one wait cycles if cache miss..,3: CPU access with two wait cycles if cahce miss..,?..."
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group.long 0x80++0x03
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line.long 0x00 "FMC_MPDAT0,ISP Data0 Register"
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hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data"
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group.long 0x84++0x03
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line.long 0x00 "FMC_MPDAT1,ISP Data1 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for multi-word programming"
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group.long 0x88++0x03
|
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line.long 0x00 "FMC_MPDAT2,ISP Data2 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming"
|
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group.long 0x8C++0x03
|
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line.long 0x00 "FMC_MPDAT3,ISP Data3 Register"
|
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hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming"
|
|
rgroup.long 0xC0++0x03
|
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line.long 0x00 "FMC_MPSTS,ISP Multi-program Status Register"
|
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bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
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bitfld.long 0x00 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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bitfld.long 0x00 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
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rgroup.long 0xC4++0x03
|
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line.long 0x00 "FMC_MPADDR,ISP Multi-program Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete"
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rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FMC_XOMR0STS0,XOM Region 0 Status Register 0"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "BASE,XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "FMC_XOMR0STS1,XOM Region 0 Status Register 1"
|
|
hexmask.long.word 0x00 0.--8. 1. "SIZE,XOM Region 0 Size Page-aligned)\nSIZE is the page number of XOM Region 0"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "FMC_XOMSTS,XOM Status Register"
|
|
bitfld.long 0x00 4. "XOMPEF,XOM Page Erase Function Fail\nXOM page erase function status" "0: Success,1: Fail"
|
|
bitfld.long 0x00 0. "XOMR0ON,XOM Region 0 On\nXOM Region 0 active status" "0: No active,1: XOM region 0 is active"
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tree.end
|
|
tree "GPIO"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA_MODE,PA I/O Mode Control"
|
|
bitfld.long 0x00 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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bitfld.long 0x00 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PA_PUSEL,PA Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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group.long 0x40++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x44++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x48++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x4C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x50++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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group.long 0x54++0x03
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line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x5C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x60++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x64++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x68++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x70++0x03
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line.long 0x00 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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group.long 0x80++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x84++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x88++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x8C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x90++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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group.long 0x94++0x03
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line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x98++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x9C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0xA0++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0xA4++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xA8++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0xB0++0x03
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line.long 0x00 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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group.long 0x140++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x144++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x148++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x14C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x150++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 14. "PIN14,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 13. "PIN13,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 12. "PIN12,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 11. "PIN11,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 10. "PIN10,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 9. "PIN9,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 8. "PIN8,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 7. "PIN7,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 6. "PIN6,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 5. "PIN5,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 4. "PIN4,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 3. "PIN3,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 2. "PIN2,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 1. "PIN1,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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rbitfld.long 0x00 0. "PIN0,Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high"
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group.long 0x154++0x03
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line.long 0x00 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x158++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x15C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x160++0x03
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x164++0x03
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.12~15/PB.8~11/PC.6~13/PC.15/PF.6~14 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x168++0x03
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-F Pin[n] High Slew Rate Control\n" "0: Px.n output with normal slew rate mode,1: Px.n output with high slew rate mode,2: Reserved,3: Reserved"
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group.long 0x170++0x03
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line.long 0x00 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "PUSEL11,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 20.--21. "PUSEL10,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "PUSEL9,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 16.--17. "PUSEL8,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PUSEL7,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 12.--13. "PUSEL6,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "PUSEL5,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 8.--9. "PUSEL4,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "PUSEL3,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 4.--5. "PUSEL2,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "PUSEL1,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
bitfld.long 0x00 0.--1. "PUSEL0,Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\n" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull- down disable"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control Register"
|
|
bitfld.long 0x00 16.--21. "ICLKONx,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always..,?..."
|
|
bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x870++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x874++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x878++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x87C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
group.long 0x880++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x884++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x888++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x88C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x894++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x8B8++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
group.long 0x940++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x944++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x948++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x94C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x950++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x954++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
group.long 0x97C++0x03
|
|
line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
tree.end
|
|
tree "I2C"
|
|
repeat 2. (list 0. 1.) (list ad:0x40080000 ad:0x40081000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or Repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x24)++0x03
|
|
line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
repeat.end
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not cleared" "0: I2C holds bus after wake-up,1: I2C does not hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
rbitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only)\nNote: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit cannot release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "NMI"
|
|
base ad:0x40000300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "UART1_INT,UART1 NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x00 14. "UART0_INT,UART0 NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PF.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PF.0 pin NMI source..,1: External interrupt from PF.0 pin NMI source.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PE.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PE.0 pin NMI source..,1: External interrupt from PE.0 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PD.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PD.0 pin NMI source..,1: External interrupt from PD.0 pin NMI source.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PC.0 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.0 pin NMI source..,1: External interrupt from PC.0 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PB.0 PD.3 or PE.5 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.0 PD.3 or PE.5 pin..,1: External interrupt from PB.0 PD.3 or PE.5 pin.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.0 PD.2 or PE.4 Pin NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.0 PD.2 or PE.4 pin..,1: External interrupt from PA.0 PD.2 or PE.4 pin.."
|
|
newline
|
|
bitfld.long 0x00 6. "RTC_INT,RTC NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Clock fail detected interrupt NMI source..,1: Clock fail detected interrupt NMI source.."
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
bitfld.long 0x00 1. "IRC_INT,IRC TRIM NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable Bit (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x00 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x00 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PF.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PF.0 interrupt is..,1: External Interrupt from PF.0 interrupt is.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PE.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PE.0 interrupt is..,1: External Interrupt from PE.0 interrupt is.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PD.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PD.0 interrupt is..,1: External Interrupt from PD.0 interrupt is.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PC.0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.0 interrupt is..,1: External Interrupt from PC.0 interrupt is.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PB.0 PD.3 or PE.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.0 PD.3 or PE.5..,1: External Interrupt from PB.0 PD.3 or PE.5.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.0 PD.2 or PE.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.0 PD.2 or PE.4..,1: External Interrupt from PA.0 PD.2 or PE.4.."
|
|
newline
|
|
bitfld.long 0x00 6. "RTC_INT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
bitfld.long 0x00 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC"
|
|
base ad:0xE000E100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "NVIC_ISER1,IRQ32 ~ IRQ63 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER2 registers enable interrupts and show which interrupts are enabled\nWrite Operation"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "NVIC_ICER1,IRQ32 ~ IRQ63 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER2 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "NVIC_ISPR1,IRQ32 ~ IRQ63 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "NVIC_ICPR1,IRQ32 ~ IRQ63 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "NVIC_IABR1,IRQ32 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active"
|
|
tree.end
|
|
tree "PDMA"
|
|
base ad:0x40008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-gather mode,3: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-gather mode,3: Reserved"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-gather mode,3: Reserved"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-gather mode,3: Reserved"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function do not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the current task is complete" "0: Idle state,1: Basic mode,2: Scatter-gather mode,3: Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMA_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMA_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMA_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMA_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMA_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filled transfer task in the.."
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external.."
|
|
repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external.."
|
|
repeat.end
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x00 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register"
|
|
bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register"
|
|
bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
|
|
bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
newline
|
|
bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
newline
|
|
bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
wgroup.long 0x414++0x03
|
|
line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
|
|
bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
newline
|
|
bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
newline
|
|
bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register"
|
|
bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register"
|
|
bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear this bit.\nNote: Please disable time-out function before clear this bit" "0: No request time-out,1: Peripheral request time-out"
|
|
bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear this bit.\nNote: Please disable time-out function before clear this bit" "0: No request time-out,1: Peripheral request time-out"
|
|
newline
|
|
rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
|
|
newline
|
|
rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
|
|
bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
|
|
bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
|
|
newline
|
|
bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
|
|
bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
|
|
newline
|
|
bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
|
|
bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
newline
|
|
bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "PDMA_ALIGN,PDMA Transfer Alignment Status Register"
|
|
bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
newline
|
|
bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
newline
|
|
bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
|
|
bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
newline
|
|
bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
newline
|
|
bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register"
|
|
bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
|
|
bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register"
|
|
bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
|
|
bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
|
|
bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode this is the base address for calculating the next link - list address"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "PDMA_CHRST,PDMA Channel Reset Register"
|
|
bitfld.long 0x00 0.--4. "CHnRST,Channel n Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset,?..."
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3"
|
|
hexmask.long.byte 0x00 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1"
|
|
abitfld.long 0x00 0.--6. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0x01=1: A peripheral cannot be assigned to two..,0x02=2: This field is useless when transfer.."
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "PDMA_REQSEL4,PDMA Request Source Select Register 1"
|
|
hexmask.long.byte 0x00 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4"
|
|
tree.end
|
|
tree "RTC"
|
|
base ad:0x40041000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_INIT,RTC Initiation Register"
|
|
hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation (Write Only)\nWhen RTC block is powered on RTC is at reset state"
|
|
rbitfld.long 0x00 0. "ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
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rbitfld.long 0x00 31. "FCRBUSY,Frequency Compensation Register Write Operation Busy (Read Only)\nNote: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) enabled" "0: The new register write operation is acceptable,1: The last write operation is in progress and.."
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bitfld.long 0x00 8.--12. "INTEGER,Integer Part" "0: Integer part of detected value is 32752,1: Integer part of detected value is 32753,2: Integer part of detected value is 32754,3: Integer part of detected value is 32755,4: Integer part of detected value is 32756,5: Integer part of detected value is 32757,6: Integer part of detected value is 32758,7: Integer part of detected value is 32759,8: Integer part of detected value is 32760,9: Integer part of detected value is 32761,10: Integer part of detected value is 32762,11: Integer part of detected value is 32763,12: Integer part of detected value is 32764,13: Integer part of detected value is 32765,14: Integer part of detected value is 32766,15: Integer part of detected value is 32767,16: Integer part of detected value is 32768,17: Integer part of detected value is 32769,18: Integer part of detected value is 32770,19: Integer part of detected value is 32771,20: Integer part of detected value is 32772,21: Integer part of detected value is 32773,22: Integer part of detected value is 32774,23: Integer part of detected value is 32775,24: Integer part of detected value is 32776,25: Integer part of detected value is 32777,26: Integer part of detected value is 32778,27: Integer part of detected value is 32779,28: Integer part of detected value is 32780,29: Integer part of detected value is 32781,30: Integer part of detected value is 32782,31: Integer part of detected value is 32783"
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bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x0C++0x03
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line.long 0x00 "RTC_TIME,RTC Time Loading Register"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x14++0x03
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line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
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bitfld.long 0x00 16. "DCOMPEN,Dynamic Compensation Enable Bit" "0: Dynamic Compensation Disabled,1: Dynamic Compensation Enabled"
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bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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group.long 0x18++0x03
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line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
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group.long 0x1C++0x03
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line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x20++0x03
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line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x24++0x03
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line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
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bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
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group.long 0x28++0x03
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line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
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bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
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bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
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group.long 0x2C++0x03
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line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
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bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit" "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit" "0: Alarm condition is not matched,1: Alarm condition is matched"
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group.long 0x30++0x03
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line.long 0x00 "RTC_TICK,RTC Time Tick Register"
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bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
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group.long 0x34++0x03
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line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
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bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
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bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
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bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
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bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x100++0x03
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line.long 0x00 "RTC_LXTCTL,RTC 32.768 kHz Oscillator Control Register"
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bitfld.long 0x00 7. "C32KS,Clock 32K Source Selection" "0: Internal 32K clock is from 32K crystal,1: Internal 32K clock is from LIRC32K"
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bitfld.long 0x00 1.--2. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range" "0: L0 mode,1: L1 mode,?..."
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group.long 0x110++0x03
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line.long 0x00 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
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bitfld.long 0x00 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
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bitfld.long 0x00 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted.."
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bitfld.long 0x00 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one.."
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tree.end
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tree "SPI"
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base ad:0x40061000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\n" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatched with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 31. "SLVERRIEN,Bit Number Error Interrupt Enable Bit for Slave Mode\nInterrupt occurs if this bit is set to 1 and bit number error event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\n" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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bitfld.long 0x00 25. "I2SSLAVE,I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode\nUser sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set.\nI2SSLAVE needs to set before.." "0: The frequency of peripheral clock is set to..,1: The frequency of peripheral clock is set to.."
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bitfld.long 0x00 24. "I2SMODE,I2S Clock Divider Number Selection for I2S Mode and SPI Mode\nUser sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set.\nUser needs to set I2SMODE before.." "0: The frequency of peripheral clock is set to..,1: The frequency of peripheral clock is set to.."
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 22. "SLVERRIF,Bit Number Error Interrupt Flag for Slave Mode\nNote: This bit will be cleared by writing 1 to it" "0: No bit number error event occurred,1: Bit number error event occurred"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SYS"
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base ad:0x40000000
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rgroup.long 0x00++0x03
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line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
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group.long 0x04++0x03
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line.long 0x00 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\n" "0: No reset from CPU lockup happened,1: The Cortex-M23 lockup happened and chip is.."
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bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M23 Core and FMC are reset by.."
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bitfld.long 0x00 6. "PMURF,PMU Reset Flag \nThe PMU reset flag is set by any reset signal when MCU is in power down state.\nNote: Write 1 to clear this bit to 0" "0: No reset in power down state,1: Any reset signal happens in power down state"
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bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the CortexM23Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M23,1: The Cortex- M23 had issued the reset signal.."
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bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: BOD had issued the reset signal to reset the.."
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\n" "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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bitfld.long 0x00 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
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bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
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group.long 0x08++0x03
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line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
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bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset"
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group.long 0x0C++0x03
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line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x00 28. "EADCRST,EADC Controller Reset" "0: EADC controller normal operation,1: EADC controller reset"
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bitfld.long 0x00 27. "USBDRST,USBD Controller Reset" "0: USBD controller normal operation,1: USBD controller reset"
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bitfld.long 0x00 24. "CANFD0RST,CANFD0 Controller Reset" "0: CANFD0 controller normal operation,1: CANFD0 controller reset"
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bitfld.long 0x00 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x00 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
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bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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group.long 0x10++0x03
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line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0x00 18. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0x00 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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group.long 0x14++0x03
|
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line.long 0x00 "SYS_ALTCTL,Miscellaneous Control Register"
|
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rbitfld.long 0x00 7. "CANFD0CKSTP,CANFD0 Clock Stop Acknowledgement (Read Only)" "0: CANFD0 clock didn't stop,1: CANFD0 clock stop"
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bitfld.long 0x00 6. "CANFD0_PDEN,CANFD0 Power Down Enable Bit" "0: CANFD0 Power-down mode Disabled,1: CANFD0 Power-down mode Enabled"
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group.long 0x18++0x03
|
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line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
|
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bitfld.long 0x00 16.--18. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\n" "0: Reserved,1: Brown-Out Detector threshold voltage is 1.8V,2: Brown-Out Detector threshold voltage is 2.0V,3: Brown-Out Detector threshold voltage is 2.4V,4: Brown-Out Detector threshold voltage is 2.7V,5: Brown-Out Detector threshold voltage is 3.0V,6: Brown-Out Detector threshold voltage is 3.7V,7: Brown-Out Detector threshold voltage is 4.4V"
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bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\n" "0: Without de-glitch function,1: 4 MIRC clock (4 MHz) 1 us,2: 8 MIRC clock (4 MHz) 2 us,3: 16 MIRC clock (4 MHz) 4 us,4: 32 MIRC clock (4 MHz) 8 us,5: 64 MIRC clock (4 MHz) 16 us,6: 128 MIRC clock (4 MHz) 32 us,7: 256 MIRC clock (4 MHz) 64 us"
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bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by LIRC,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
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bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\n" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\n" "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\n" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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group.long 0x1C++0x03
|
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line.long 0x00 "SYS_IVSCTL,Internal Voltage Source Control Register"
|
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bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\n" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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|
group.long 0x24++0x03
|
|
line.long 0x00 "SYS_PORCTL0,Power-On-reset Controller Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "PORMASK,Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
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|
group.long 0x30++0x03
|
|
line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
|
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bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x34++0x03
|
|
line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
|
|
bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x38++0x03
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line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x3C++0x03
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line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x40++0x03
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line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x44++0x03
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line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PC15MFP,PC.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PC14MFP,PC.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 20.--23. "PC13MFP,PC.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PC12MFP,PC.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 12.--15. "PC11MFP,PC.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PC10MFP,PC.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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bitfld.long 0x00 4.--7. "PC9MFP,PC.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PC8MFP,PC.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x58++0x03
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line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x5C++0x03
|
|
line.long 0x00 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
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|
bitfld.long 0x00 28.--31. "PF15MFP,PF.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PF14MFP,PF.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 20.--23. "PF13MFP,PF.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. "PF12MFP,PF.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 12.--15. "PF11MFP,PF.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "PF10MFP,PF.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 4.--7. "PF9MFP,PF.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "PF8MFP,PF.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x80++0x03
|
|
line.long 0x00 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
|
|
bitfld.long 0x00 15. "MFOS15,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 13. "MFOS13,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 11. "MFOS11,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 9. "MFOS9,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 7. "MFOS7,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 5. "MFOS5,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 3. "MFOS3,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 1. "MFOS1,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x84++0x03
|
|
line.long 0x00 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
|
|
bitfld.long 0x00 15. "MFOS15,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
bitfld.long 0x00 14. "MFOS14,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 13. "MFOS13,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 11. "MFOS11,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
bitfld.long 0x00 10. "MFOS10,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 9. "MFOS9,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
bitfld.long 0x00 8. "MFOS8,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 7. "MFOS7,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
bitfld.long 0x00 6. "MFOS6,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 5. "MFOS5,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 3. "MFOS3,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 2. "MFOS2,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
newline
|
|
bitfld.long 0x00 1. "MFOS1,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 0. "MFOS0,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
|
|
bitfld.long 0x00 15. "MFOS15,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 14. "MFOS14,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 13. "MFOS13,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 12. "MFOS12,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 11. "MFOS11,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 10. "MFOS10,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 9. "MFOS9,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 8. "MFOS8,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 7. "MFOS7,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 6. "MFOS6,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 5. "MFOS5,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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|
bitfld.long 0x00 4. "MFOS4,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 3. "MFOS3,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
bitfld.long 0x00 2. "MFOS2,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
|
|
newline
|
|
bitfld.long 0x00 1. "MFOS1,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0x94++0x03
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line.long 0x00 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 13. "MFOS13,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 11. "MFOS11,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 9. "MFOS9,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 7. "MFOS7,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 5. "MFOS5,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 3. "MFOS3,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 1. "MFOS1,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple function pin output mode type is..,1: Multiple function pin output mode type is.."
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group.long 0xC0++0x03
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line.long 0x00 "SYS_MODCTL,Modulation Control Register"
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group.long 0xD0++0x03
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line.long 0x00 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register"
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bitfld.long 0x00 7. "PDMABIST,PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM.\nNote: This bit is write protected" "0: System PDMA BIST Disabled,1: System PDMA BIST Enabled"
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bitfld.long 0x00 6. "CANFD0BIST,CANFD0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CANFD0 RAM.\nNote: This bit is write protected" "0: System CANFD0 BIST Disabled,1: System CANFD0 BIST Enabled"
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bitfld.long 0x00 4. "USBBIST,USB BIST Enable Bit (Write Protect) \nThis bit enables BIST test for USB RAM\nNote: This bit is write protected" "0: System USB BIST Disabled,1: System USB BIST Enabled"
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bitfld.long 0x00 2. "FMCBIST,FMC CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM.\nNote: This bit is write protected" "0: System CACHE BIST Disabled,1: System CACHE BIST Enabled"
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bitfld.long 0x00 0. "SRBIST,SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM.\nNote: This bit is write protected" "0: System SRAM BIST Disabled,1: System SRAM BIST Enabled"
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rgroup.long 0xD4++0x03
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line.long 0x00 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register"
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bitfld.long 0x00 23. "PDMAEND,PDMA SRAM BIST Test Finish" "0: PDMA SRAM BIST is active,1: PDMA SRAM BIST test finished"
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bitfld.long 0x00 22. "CANFD0END,CANFD0 SRAM BIST Test Finish" "0: CANFD0 SRAM BIST is active,1: CANFD0 SRAM BIST test finished"
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bitfld.long 0x00 20. "USBBEND,USB SRAM BIST Test Finish" "0: USB SRAM BIST is active,1: USB SRAM BIST test finished"
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bitfld.long 0x00 18. "CR1BEND,CACHE 1 SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finished"
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bitfld.long 0x00 17. "CR0BEND,CACHE 0 SRAM BIST Test Finish" "0: System CACHE RAM BIST is active,1: System CACHE RAM BIST test finished"
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bitfld.long 0x00 16. "SRBEND,SRAM BIST Test Finish" "0: System SRAM BIST active,1: system SRAM BIST finished"
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bitfld.long 0x00 7. "PDMABISTF,PDMA SRAM BIST Failed Flag" "0: PDMA SRAM BIST passed,1: PDMA SRAM BIST failed"
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bitfld.long 0x00 6. "CANFD0BISTF,CANFD0 SRAM BIST Failed Flag" "0: CANFD0 SRAM BIST passed,1: CANFD0 SRAM BIST failed"
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bitfld.long 0x00 4. "USBBEF,USB SRAM BIST Fail Flag" "0: USB SRAM BIST test passed,1: USB SRAM BIST test failed"
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bitfld.long 0x00 2. "CR1BISTEF,CACHE1 SRAM BIST Fail Flag" "0: System CACHE RAM BIST test passed,1: System CACHE RAM BIST test failed"
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bitfld.long 0x00 1. "CR0BISTEF,CACHE0 SRAM BIST Fail Flag" "0: System CACHE RAM BIST test passed,1: System CACHE RAM BIST test failed"
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bitfld.long 0x00 0. "SRBISTEF,System SRAM BIST Fail Flag" "0: System SRAM BIST test passed,1: System SRAM BIST test failed"
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group.long 0xF0++0x03
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line.long 0x00 "SYS_HIRCTRIMCTL,HIRC Trim Control Register"
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bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768..,1: HIRC trim reference clock is from internal.."
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bitfld.long 0x00 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation keeps going if clock is..,1: The trim operation stops if clock is inaccurate"
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
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group.long 0xF4++0x03
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line.long 0x00 "SYS_HIRCTRIMIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status..,1: Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to.."
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bitfld.long 0x00 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency is still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf.." "0: Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to.."
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group.long 0xF8++0x03
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line.long 0x00 "SYS_HIRCTRIMSTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag" "0: Over boundary condition did not occur,1: Over boundary condition occurred"
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bitfld.long 0x00 2. "CLKERIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked" "0: Trim value update limitation count not reached,1: Trim value update limitation count reached.."
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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group.long 0x100++0x03
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line.long 0x00 "SYS_REGLCTL,Register Lock Control Register"
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hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code \nSome registers have write-protection function"
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group.long 0x104++0x03
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line.long 0x00 "SYS_MIRCTRIMCTL,MIRC Trim Control Register"
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bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: MIRC trim reference clock is from LXT (32.768..,1: MIRC trim reference clock is from internal.."
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bitfld.long 0x00 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation keeps going if clock is..,1: The trim operation stops if clock is inaccurate"
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Reserved,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached this field.." "0: Disable HIRC auto trim function,1: Reserved,2: Enable HIRC auto trim function and trim MIRC..,?..."
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group.long 0x108++0x03
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line.long 0x00 "SYS_MIRCTRIMIEN,MIRC Trim Interrupt Enable Register"
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bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccurate during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_MIRCTRIMSTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERRIF(SYS_MIRCTRIMSTS[2]) status..,1: Enable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to.."
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bitfld.long 0x00 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRTRIMCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_MIRCTRIMSTS[1]) status to..,1: Enable TFAILIF(SYS_MIRCTRIMSTS[1]) status to.."
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group.long 0x10C++0x03
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line.long 0x00 "SYS_MIRCTRIMSTS,MIRC Trim Interrupt Status Register"
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bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag" "0: Over boundary condition did not occur,1: Over boundary condition occurred"
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bitfld.long 0x00 2. "CLKERIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value this bit will be set and be an indicate that clock.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency is still not locked" "0: Trim value update limitation count not reached,1: Trim value update limitation count reached.."
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bitfld.long 0x00 0. "FREQLOCK,MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0" "0: The internal medium-speed oscillator..,1: The internal medium-speed oscillator.."
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group.long 0x1EC++0x03
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line.long 0x00 "SYS_PORCTL1,Power-On-reset Controller Register 1"
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hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nAfter powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or chip.."
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group.long 0x1F8++0x03
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line.long 0x00 "SYS_PLCTL,Power Level Control Register"
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bitfld.long 0x00 0.--1. "PLSEL,Power Level Select(Write Protect)\nNote : When system is at PL3 HCLK clock has to come from LXT or LIRC" "0: Set to power level 0 (PL0),?,?,3: Set to power level 3 (PL3)"
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group.long 0x1FC++0x03
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line.long 0x00 "SYS_PLSTS,Power Level Status Register"
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rbitfld.long 0x00 8.--9. "CURPL,Current Power Level (Read Only)\nThis bit field reflect the current power level.\nNote : When system is at PL3 HCLK clock has to come from LXT or LIRC" "0: Current power level is PL0,?,?,3: Current power level is PL3"
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rbitfld.long 0x00 0. "PLCBUSY,Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing" "0: Power level change is completed,1: Power level change is ongoing"
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tree.end
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tree "SYST_SCR"
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base ad:0xE000E000
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group.long 0x10++0x03
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line.long 0x00 "SYST_CTRL,SysTick Control and Status Register"
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bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
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bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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group.long 0x14++0x03
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line.long 0x00 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0"
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group.long 0x18++0x03
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line.long 0x00 "SYST_VAL,SysTick Current Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
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group.long 0xD04++0x03
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
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bitfld.long 0x00 30. "NMIPENDCLR,NMI Bit-pending Bit\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state" "0: No effect,1: Clear pending status"
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bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x00 12.--19. 1. "VECTPENDING,Number of the Highest Pended Exception (Read Only)"
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hexmask.long.byte 0x00 0.--7. 1. "VECTACTIVE,Number of the Current Active Exception (Read Only)"
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group.long 0xD08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long.tbyte 0x00 9.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state"
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group.long 0xD0C++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the.."
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rbitfld.long 0x00 15. "ENDIANNESS,Data Endianness (Read Only)" "0: Little-endian,1: Big-endian"
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bitfld.long 0x00 14. "PRIS,Priority Secure Exceptions Bit" "0: Priority ranges of Secure and Non-secure..,?..."
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bitfld.long 0x00 3. "SYSRESETREQS,System Reset Request Secure Only Bit" "0: SYSRESETREQ functionality is available to..,?..."
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bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1"
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bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
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group.long 0xD10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep"
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an.."
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group.long 0xD14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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group.long 0xD1C++0x03
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3"
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|
group.long 0xD20++0x03
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line.long 0x00 "SHPR3,System Handler Priority Register 3"
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|
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3"
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bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3"
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group.long 0xD24++0x03
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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|
bitfld.long 0x00 21. "HARDFAULTPENDED,HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state of\nthe HardFault exception corresponding to the selected Security state.\nThis bit is banked between Security states.\nThe possible.." "0: HardFault exception not pending for the..,1: HardFault exception pending for the selected.."
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tree.end
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tree "TIMER"
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tree "TMR01"
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base ad:0x40050000
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group.long 0x00++0x03
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line.long 0x00 "TIMER0_CTL,Timer0 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x08++0x03
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line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Capture Function source is from MIRC,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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newline
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
|
|
group.long 0x18++0x03
|
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line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x1C++0x03
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line.long 0x00 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as BPWM counter clock source" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x100++0x03
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line.long 0x00 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x108++0x03
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line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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group.long 0x110++0x03
|
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line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x114++0x03
|
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line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Capture Function source is from MIRC,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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newline
|
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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newline
|
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
|
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line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x11C++0x03
|
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line.long 0x00 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as BPWM counter clock source" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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tree.end
|
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tree "TMR23"
|
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base ad:0x40051000
|
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group.long 0x00++0x03
|
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line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
|
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
|
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
|
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
|
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group.long 0x04++0x03
|
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line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
|
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x08++0x03
|
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Capture Function source is from MIRC,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x1C++0x03
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line.long 0x00 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as BPWM counter clock source" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x100++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
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abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.."
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group.long 0x108++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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group.long 0x110++0x03
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.."
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group.long 0x114++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 28.--31. "CAPDIVSCL,Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source/1,1: Capture source/2,2: Capture source/4,3: Capture source/8,4: Capture source/16,5: Capture source/32,6: Capture source/64,7: Capture source/128,8: Capture source/256,?..."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL.." "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,2: Capture Function source is from HXT,3: Capture Function source is from LXT,4: Capture Function source is from HIRC,5: Capture Function source is from LIRC,6: Capture Function source is from MIRC,7: Reserved"
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1 user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source" "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin ACMP internal clock or..,1: TMx_EXT (x= 0~3) pin ACMP internal clock or.."
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group.long 0x11C++0x03
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line.long 0x00 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger BPWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as BPWM counter clock source" "0: Timer interrupt trigger BPWM Disabled,1: Timer interrupt trigger BPWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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tree.end
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tree.end
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tree "UART"
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tree "UART0"
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base ad:0x40070000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\n" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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repeat 3. (list 1. 2. 3.) (list ad:0x40071000 ad:0x40072000 ad:0x40073000)
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tree "UART$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\n" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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repeat.end
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tree "UART4"
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base ad:0x40074000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,PARITY Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the PARITY bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Interrupt Disabled,1: Single-wire Bit Error Detect Interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\n" "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\n" "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\n" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\n" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,PARITY Bit Source Selection\nThe PARITY bit can be selected to be generated and checked automatically or by software.\n" "0: PARITY bit is generated by EPE (UART_LINE[4])..,1: PARITY bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the PARITY bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,PARITY Bit Enable Bit\nNote: PARITY bit is generated on each outgoing character and is checked on each incoming data" "0: PARITY bit generated Disabled,1: PARITY bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\n" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS Signal Control\nThis bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\n" "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'START bit' + data bits + parity + STOP.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'STOP bit' (that is the STOP bit following the last data bit or PARITY bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'PARITY bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\n" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.."
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state is not equal to UART controller TX state in Single-wire mode.\n" "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.."
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to program the transfer delay time between the last STOP bit and next START bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from START bit to the 1st rising..,1: 2-bit time from START bit to the 1st rising..,2: 4-bit time from START bit to the 1st rising..,3: 8-bit time from START bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode\nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\n" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not be disabled immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,?,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..."
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\n" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit\n" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote: When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote: When the system is in Power-down mode an external nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\n" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,START Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (START bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree.end
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tree "USBD"
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base ad:0x400C0000
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group.long 0x00++0x03
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line.long 0x00 "USBD_INTEN,USB Device Interrupt Enable Register"
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bitfld.long 0x00 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When the device responds NAK after receiving..,1: IN NAK status will be updated to USBD_EPSTS0.."
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bitfld.long 0x00 8. "WKEN,Wake-up Function Enable Bit\nNote: If woken up by any change by VBUS state VBDETIEN must be enabled" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x00 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
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bitfld.long 0x00 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x00 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
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bitfld.long 0x00 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x00 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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group.long 0x04++0x03
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line.long 0x00 "USBD_INTSTS,USB Device Interrupt Event Status Register"
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bitfld.long 0x00 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred and it is cleared by.."
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bitfld.long 0x00 30. "EPEVT14,Endpoint 14's USB Event Status" "0: No event occurred in endpoint 14,1: USB event occurred on Endpoint 14 check.."
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bitfld.long 0x00 29. "EPEVT13,Endpoint 13's USB Event Status" "0: No event occurred in endpoint 13,1: USB event occurred on Endpoint 13 check.."
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bitfld.long 0x00 28. "EPEVT12,Endpoint 12's USB Event Status" "0: No event occurred in endpoint 12,1: USB event occurred on Endpoint 12 check.."
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bitfld.long 0x00 27. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11 check.."
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bitfld.long 0x00 26. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10 check.."
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bitfld.long 0x00 25. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9 check.."
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bitfld.long 0x00 24. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8 check.."
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bitfld.long 0x00 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
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bitfld.long 0x00 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
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bitfld.long 0x00 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x00 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
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bitfld.long 0x00 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x00 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
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bitfld.long 0x00 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x00 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
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bitfld.long 0x00 9. "EPEVT16,Endpoint 16's USB Event Status" "0: No event occurred in endpoint 16,1: USB event occurred on Endpoint 16 check.."
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bitfld.long 0x00 8. "EPEVT15,Endpoint 15's USB Event Status" "0: No event occurred in endpoint 15,1: USB event occurred on Endpoint 15 check.."
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bitfld.long 0x00 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event did not occur,1: SOF event occurred and it is cleared by.."
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bitfld.long 0x00 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event did not occur,1: No-event-wake-up event occurred and it is.."
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bitfld.long 0x00 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB.."
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bitfld.long 0x00 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus" "0: No USB event occurred,1: USB event occurred check EPSTS0~11[3:0] to.."
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bitfld.long 0x00 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus" "0: No BUS event occurred,1: Bus event occurred check USBD_ATTR[3:0] to.."
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group.long 0x08++0x03
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line.long 0x00 "USBD_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Device Function Address"
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rgroup.long 0x0C++0x03
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line.long 0x00 "USBD_EPSTS,USB Device Endpoint Status Register"
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bitfld.long 0x00 7. "OV,Overrun\nIt indicates that the received data is more than the maximum payload number or not" "0: No overrun,1: Out Data is more than the Max Payload in.."
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group.long 0x10++0x03
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line.long 0x00 "USBD_ATTR,USB Device Bus Status and Attribution Register"
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rbitfld.long 0x00 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus has no LPM L1 state resume,1: LPM L1 state resume from LPM L1 state suspend"
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rbitfld.long 0x00 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus has no L1 state suspend,1: This bit is set by the hardware when LPM.."
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bitfld.long 0x00 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: The valid LPM Token will be NYET,1: The valid LPM Token will be ACK"
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bitfld.long 0x00 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode,1: Byte mode"
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bitfld.long 0x00 9. "PWRDN,Power-down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
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bitfld.long 0x00 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x00 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x00 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).."
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bitfld.long 0x00 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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rbitfld.long 0x00 3. "TOUT,Time-out Status (Read Only)" "0: No time-out,1: No Bus response more than 18 bits time ("
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rbitfld.long 0x00 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend"
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rbitfld.long 0x00 1. "SUSPEND,Suspend Status (Read Only)" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
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rbitfld.long 0x00 0. "USBRST,USB Reset Status (Read Only)" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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rgroup.long 0x14++0x03
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line.long 0x00 "USBD_VBUSDET,USB Device VBUS Detection Register"
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bitfld.long 0x00 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
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group.long 0x18++0x03
|
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line.long 0x00 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
|
|
bitfld.long 0x00 28.--31. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
bitfld.long 0x00 24.--27. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
newline
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bitfld.long 0x00 20.--23. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "USBD_EPSTS1,USB Device Endpoint Status Register 1"
|
|
bitfld.long 0x00 28.--31. "EPSTS15,Endpoint 15 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
bitfld.long 0x00 24.--27. "EPSTS14,Endpoint 14 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
newline
|
|
bitfld.long 0x00 20.--23. "EPSTS13,Endpoint 13 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
bitfld.long 0x00 16.--19. "EPSTS12,Endpoint 12 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
newline
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|
bitfld.long 0x00 12.--15. "EPSTS11,Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
bitfld.long 0x00 8.--11. "EPSTS10,Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
newline
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|
bitfld.long 0x00 4.--7. "EPSTS9,Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
bitfld.long 0x00 0.--3. "EPSTS8,Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "USBD_EPSTS2,USB Device Endpoint Status Register 2"
|
|
bitfld.long 0x00 0.--3. "EPSTS16,Endpoint 16 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,?,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "USBD_LPMATTR,USB LPM Attribution Register"
|
|
bitfld.long 0x00 8. "LPMRWAKUP,LPM Remote Wake-up\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
|
|
bitfld.long 0x00 4.--7. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 0.--3. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "USBD_FN,USB Frame Number Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet.\nNote: Suggest to read USBD_FN after USBD_INTSTS[4] SOFIF interrupt is triggered and cleared"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "USBD_SE0,USB Device Drive SE0 Control Register"
|
|
bitfld.long 0x00 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low" "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "USBD_CFG0,Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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|
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "USBD_CFG1,Endpoint 1 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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|
newline
|
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bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x51C++0x03
|
|
line.long 0x00 "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "USBD_CFG2,Endpoint 2 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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|
newline
|
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bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "USBD_CFG3,Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "USBD_CFG4,Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
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bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "USBD_CFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "USBD_CFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "USBD_CFG7,Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "USBD_BUFSEG8,Endpoint 8 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "USBD_MXPLD8,Endpoint 8 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "USBD_CFG8,Endpoint 8 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "USBD_CFGP8,Endpoint 8 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "USBD_BUFSEG9,Endpoint 9 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "USBD_MXPLD9,Endpoint 9 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "USBD_CFG9,Endpoint 9 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "USBD_CFGP9,Endpoint 9 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "USBD_BUFSEG10,Endpoint 10 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "USBD_MXPLD10,Endpoint 10 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "USBD_CFG10,Endpoint 10 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "USBD_CFGP10,Endpoint 10 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "USBD_BUFSEG11,Endpoint 11 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "USBD_MXPLD11,Endpoint 11 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "USBD_CFG11,Endpoint 11 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "USBD_CFGP11,Endpoint 11 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "USBD_BUFSEG12,Endpoint 12 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5C4++0x03
|
|
line.long 0x00 "USBD_MXPLD12,Endpoint 12 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5C8++0x03
|
|
line.long 0x00 "USBD_CFG12,Endpoint 12 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5CC++0x03
|
|
line.long 0x00 "USBD_CFGP12,Endpoint 12 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5D0++0x03
|
|
line.long 0x00 "USBD_BUFSEG13,Endpoint 13 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5D4++0x03
|
|
line.long 0x00 "USBD_MXPLD13,Endpoint 13 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5D8++0x03
|
|
line.long 0x00 "USBD_CFG13,Endpoint 13 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5DC++0x03
|
|
line.long 0x00 "USBD_CFGP13,Endpoint 13 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5E0++0x03
|
|
line.long 0x00 "USBD_BUFSEG14,Endpoint 14 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5E4++0x03
|
|
line.long 0x00 "USBD_MXPLD14,Endpoint 14 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5E8++0x03
|
|
line.long 0x00 "USBD_CFG14,Endpoint 14 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5EC++0x03
|
|
line.long 0x00 "USBD_CFGP14,Endpoint 14 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5F0++0x03
|
|
line.long 0x00 "USBD_BUFSEG15,Endpoint 15 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5F4++0x03
|
|
line.long 0x00 "USBD_MXPLD15,Endpoint 15 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5F8++0x03
|
|
line.long 0x00 "USBD_CFG15,Endpoint 15 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5FC++0x03
|
|
line.long 0x00 "USBD_CFGP15,Endpoint 15 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "USBD_BUFSEG16,Endpoint 16 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "USBD_MXPLD16,Endpoint 16 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "USBD_CFG16,Endpoint 16 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "USBD_CFGP16,Endpoint 16 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLD0~16 register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
tree.end
|
|
tree "USCII2C"
|
|
repeat 3. (list 0. 1. 2.) (list ad:0x400D0000 ad:0x400D1000 ad:0x400D2000)
|
|
tree "UI2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UI2C_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
|
|
newline
|
|
bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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|
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
|
|
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions defined in I2C"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "UI2C_DEVADDR$1,USCI Device Address Register $1"
|
|
abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software sets 10'h000 the address.."
|
|
repeat.end
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x4C)++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK$1,USCI Device Address Mask Register $1"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI supports multiple address recognition with two address mask register"
|
|
repeat.end
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according to data toggle,1: The chip is woken up according to address match"
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
|
|
hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
|
|
newline
|
|
bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
|
|
bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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|
newline
|
|
bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
|
|
bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
|
|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
|
|
bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
|
|
bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
|
|
bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
|
|
bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
|
|
bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
|
|
newline
|
|
bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command is recorded on the address..,1: Read command is recorded on the address match.."
|
|
bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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|
newline
|
|
bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
|
|
bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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|
newline
|
|
bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
|
|
bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\n" "0: An I2C error has not been detected,1: An I2C error has been detected"
|
|
newline
|
|
bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
|
|
bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
|
|
newline
|
|
bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\n" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
|
|
bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
|
|
newline
|
|
bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
|
|
bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "USCISPI"
|
|
base ad:0x400D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USPI_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
|
|
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external.." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
|
|
bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
|
|
newline
|
|
bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
|
|
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
|
|
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift unit.\nNote: In SPI.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
|
|
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
|
|
newline
|
|
bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output values of USCIx_DAT0/1 pins are..,1: Data output values of USCIx_DAT0/1 pins are.."
|
|
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
|
|
bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
|
|
bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
|
|
bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
|
|
newline
|
|
bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
|
|
bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
|
|
bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
|
bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
|
|
bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
|
|
newline
|
|
bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
|
|
bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
|
|
bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring" "0: The output data level is 0 if TX under run..,1: The output data level is 1 if TX under run.."
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
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bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically" "0: TSMSEL,?,?,?,4: TSMSEL,?..."
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bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0: MODE0,1: MODE1,2: MODE2,3: MODE3"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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group.long 0x60++0x03
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line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])" "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
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bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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group.long 0x64++0x03
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line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote1: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree "USCIUART"
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base ad:0x400D0000
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group.long 0x00++0x03
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line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,2: fSAMP_CLK is selected to fSCLK,3: fSAMP_CLK is selected to fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0: The data word contains 16 bits located at bit..,1: Reserved,2: Reserved,3: Reserved,4: The data word contains 4 bits located at bit..,5: The data word contains 5 bits located at bit..,6: The data word contains 6 bits located at bit..,7: The data word contains 7 bits located at bit..,8: The data word contains 8 bits located at bit..,9: The data word contains 9 bits located at bit..,10: The data word contains 10 bits located at..,11: The data word contains 11 bits located at..,12: The data word contains 12 bits located at..,13: The data word contains 13 bits located at..,14: The data word contains 14 bits located at..,15: The data word contains 15 bits located at.."
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCI0_DAT1 pin" "0: The value of USCI0_DAT1 is equal to the data..,1: The value of USCI0_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\n" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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group.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 30. "DGE,Deglitch Enable Bit\n" "0: Deglitch Disabled,1: Deglitch Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the nRTS signal is inactive automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree "WDT"
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base ad:0x40040000
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group.long 0x00++0x03
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line.long 0x00 "WDT_CTL,WDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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bitfld.long 0x00 8.--11. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK,8: 220 * WDT_CLK,?..."
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bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
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bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect) \nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
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wgroup.long 0x08++0x03
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line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote1: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active"
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tree.end
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tree "WWDT"
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base ad:0x40040100
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wgroup.long 0x00++0x03
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line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x04++0x03
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line.long 0x00 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
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bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
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group.long 0x08++0x03
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line.long 0x00 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0x0C++0x03
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line.long 0x00 "WWDT_CNT,WWDT Counter Value Register"
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bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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autoindent.off
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newline
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