33530 lines
4.0 MiB
33530 lines
4.0 MiB
; --------------------------------------------------------------------------------
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; @Title: M2351 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-03-01 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: SVD generated, based on: M2531_v1.svd (Ver. 1.0)
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; @Core: Cortex-M23
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; @Chip: M2351CIAAE, M2351KIAAE, M2351SFSIAAP, M2351SIAAE, M2351ZIAAE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm2351.per 14428 2022-03-02 16:18:59Z kwisniewski $
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main extension,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ACMP"
|
|
tree "ACMP01"
|
|
base ad:0x40045000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x00 28.--29. "MODESEL,Propagation Delay Mode Selection" "0: Max propagation delay is 4.5uS operation..,1: Max propagation delay is 2uS operation..,2: Max propagation delay is 600nS operation..,3: Max propagation delay is 200nS operation.."
|
|
bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV"
|
|
newline
|
|
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
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bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
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bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs"
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newline
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bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.."
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bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3"
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bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: DAC output"
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bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
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bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
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group.long 0x04++0x03
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line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
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bitfld.long 0x00 28.--29. "MODESEL,Propagation Delay Mode Selection" "0: Max propagation delay is 4.5uS operation..,1: Max propagation delay is 2uS operation..,2: Max propagation delay is 600nS operation..,3: Max propagation delay is 200nS operation.."
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bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV"
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newline
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bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
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bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
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bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs"
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newline
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bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.."
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bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3"
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bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: DAC output"
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newline
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bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
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bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
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group.long 0x08++0x03
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line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
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bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the..,1: The positive input voltage is in the window"
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bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1"
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newline
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bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1"
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bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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newline
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bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
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newline
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bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
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bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output" "0,1"
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newline
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bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output" "0,1"
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group.long 0x0C++0x03
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line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
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bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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tree.end
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tree "ACMP01_NS"
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base ad:0x50045000
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group.long 0x00++0x03
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line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
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bitfld.long 0x00 28.--29. "MODESEL,Propagation Delay Mode Selection" "0: Max propagation delay is 4.5uS operation..,1: Max propagation delay is 2uS operation..,2: Max propagation delay is 600nS operation..,3: Max propagation delay is 200nS operation.."
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bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV"
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newline
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bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
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|
bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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|
newline
|
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bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs"
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newline
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bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.."
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bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3"
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bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: DAC output"
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|
newline
|
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bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
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bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
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group.long 0x04++0x03
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line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
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bitfld.long 0x00 28.--29. "MODESEL,Propagation Delay Mode Selection" "0: Max propagation delay is 4.5uS operation..,1: Max propagation delay is 2uS operation..,2: Max propagation delay is 600nS operation..,3: Max propagation delay is 200nS operation.."
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bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,1: Hysteresis is 10mV,2: Hysteresis is 20mV,3: Hysteresis is 30mV"
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newline
|
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bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode is Selected"
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bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled"
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newline
|
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bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs"
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newline
|
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bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.."
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bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3"
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bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: DAC output"
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newline
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bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
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bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
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group.long 0x08++0x03
|
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line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
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bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the..,1: The positive input voltage is in the window"
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bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1"
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newline
|
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bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1"
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bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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newline
|
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bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
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bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
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newline
|
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bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
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bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output" "0,1"
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newline
|
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bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output" "0,1"
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group.long 0x0C++0x03
|
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line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
|
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bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV source voltage,1: The reference voltage defined by SYS_VREFCTL.."
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bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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tree.end
|
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tree.end
|
|
tree "BPWM"
|
|
tree "BPWM0"
|
|
base ad:0x4005A000
|
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group.long 0x00++0x03
|
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line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
|
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
|
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
|
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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|
newline
|
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
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newline
|
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
|
|
bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
|
|
bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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|
group.long 0x14++0x03
|
|
line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
|
|
bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
|
|
bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: \nIn this mode BPWM counter counts from 0 to PERIOD and restarts from 0"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "BPWM_CMPDAT0,BPWM Comparator Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "BPWM_CMPDAT1,BPWM Comparator Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "BPWM_CMPDAT2,BPWM Comparator Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "BPWM_CMPDAT3,BPWM Comparator Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "BPWM_CMPDAT4,BPWM Comparator Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "BPWM_CMPDAT5,BPWM Comparator Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
|
|
rgroup.long 0x90++0x03
|
|
line.long 0x00 "BPWM_CNT,BPWM Counter Register"
|
|
bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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group.long 0x110++0x03
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line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRG4,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRG3,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRG2,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRG1,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRG0,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x250++0x03
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line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
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group.long 0x254++0x03
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line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
|
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line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
|
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line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x320++0x03
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line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x324++0x03
|
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line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x328++0x03
|
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line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
|
|
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
tree.end
|
|
tree "BPWM0_NS"
|
|
base ad:0x5005A000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
|
|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x03
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line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: \nIn this mode BPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x54++0x03
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line.long 0x00 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x58++0x03
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line.long 0x00 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x5C++0x03
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line.long 0x00 "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x60++0x03
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line.long 0x00 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x64++0x03
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line.long 0x00 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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rgroup.long 0x90++0x03
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line.long 0x00 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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group.long 0x110++0x03
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line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRG4,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRG3,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRG2,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRG1,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRG0,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x250++0x03
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line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
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group.long 0x254++0x03
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line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
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line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
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line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x320++0x03
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line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x324++0x03
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line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x328++0x03
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line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
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line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x330++0x03
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line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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tree.end
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tree "BPWM1"
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base ad:0x4005B000
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group.long 0x00++0x03
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line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x03
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line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: \nIn this mode BPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x54++0x03
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line.long 0x00 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x58++0x03
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line.long 0x00 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x5C++0x03
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line.long 0x00 "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x60++0x03
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line.long 0x00 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x64++0x03
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line.long 0x00 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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rgroup.long 0x90++0x03
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line.long 0x00 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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group.long 0x110++0x03
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line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRG4,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRG3,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRG2,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRG1,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRG0,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x218++0x03
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|
line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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|
line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x220++0x03
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|
line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x224++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x228++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x22C++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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group.long 0x230++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x234++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x238++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
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|
group.long 0x250++0x03
|
|
line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
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|
group.long 0x254++0x03
|
|
line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
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line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
|
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line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x320++0x03
|
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line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x324++0x03
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line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x328++0x03
|
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line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
|
|
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x330++0x03
|
|
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
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tree.end
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tree "BPWM1_NS"
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base ad:0x5005B000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects BPWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bit(S)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is Enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
|
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line.long 0x00 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x00 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0" "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x00 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x00 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR0,Clear BPWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x03
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line.long 0x00 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,BPWM Period Register\nUp-Count mode: \nIn this mode BPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
|
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line.long 0x00 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x54++0x03
|
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line.long 0x00 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x58++0x03
|
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line.long 0x00 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x5C++0x03
|
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line.long 0x00 "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x60++0x03
|
|
line.long 0x00 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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group.long 0x64++0x03
|
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line.long 0x00 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMPDAT,BPWM Comparator Register\nCMPDAT use to compare with CNTR to generate BPWM waveform interrupt and trigger EADC.\nIn independent mode CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point"
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rgroup.long 0x90++0x03
|
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line.long 0x00 "BPWM_CNT,BPWM Counter Register"
|
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bitfld.long 0x00 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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newline
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bitfld.long 0x00 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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newline
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bitfld.long 0x00 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,2: BPWM period (center) point output High,3: BPWM period (center) point output Toggle"
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newline
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bitfld.long 0x00 10.--11. "ZPCTL5,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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newline
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bitfld.long 0x00 6.--7. "ZPCTL3,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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newline
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bitfld.long 0x00 2.--3. "ZPCTL1,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,BPWM Zero Point Control\nBPWM can control output level when BPWM counter count to zero.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM zero point output Low,2: BPWM zero point output High,3: BPWM zero point output Toggle"
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group.long 0xB4++0x03
|
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line.long 0x00 "BPWM_WGCTL1,BPWM Generation Register 1"
|
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bitfld.long 0x00 26.--27. "CMPDCTL5,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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newline
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bitfld.long 0x00 22.--23. "CMPDCTL3,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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newline
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bitfld.long 0x00 18.--19. "CMPDCTL1,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,BPWM Compare Down Point Control\nBPWM can control output level when BPWM counter down count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare down point output Low,2: BPWM compare down point output High,3: BPWM compare down point output Toggle"
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newline
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bitfld.long 0x00 10.--11. "CMPUCTL5,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,BPWM Compare Up Point Control\nBPWM can control output level when BPWM counter up count to CMPDAT.\nEach bit n controls the corresponding BPWM channel n" "0: Do nothing,1: BPWM compare up point output Low,2: BPWM compare up point output High,3: BPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled" "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 4. "MSKDAT4,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 3. "MSKDAT3,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 2. "MSKDAT2,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 1. "MSKDAT1,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0x00 0. "MSKDAT0,BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if corresponding mask function is enabled" "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x03
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line.long 0x00 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWMx_CHn output pin" "0: BPWMx_CHn output pin polar inverse Disabled,1: BPWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x03
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line.long 0x00 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x00 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x00 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "PIF0,BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0 software can write 1 to clear this bit to 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0 software can write 1 to clear this bit to 0" "0,1"
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group.long 0xF8++0x03
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line.long 0x00 "BPWM_EADCTS0,BPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,BPWM_CH3 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,BPWM_CH3 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 23. "TRGEN2,BPWM_CH2 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,BPWM_CH2 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH2 zero point,1: BPWM_CH2 period point,2: BPWM_CH2 zero or period point,3: BPWM_CH2 up-count compared point,4: BPWM_CH2 down-count compared point,?,?,?,8: BPWM_CH3 up-count compared point,9: BPWM_CH3 down-count compared point,?..."
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bitfld.long 0x00 15. "TRGEN1,BPWM_CH1 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,BPWM_CH1 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN0,BPWM_CH0 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,BPWM_CH0 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH0 zero point,1: BPWM_CH0 period point,2: BPWM_CH0 zero or period point,3: BPWM_CH0 up-count compared point,4: BPWM_CH0 down-count compared point,?,?,?,8: BPWM_CH1 up-count compared point,9: BPWM_CH1 down-count compared point,?..."
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group.long 0xFC++0x03
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line.long 0x00 "BPWM_EADCTS1,BPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,BPWM_CH5 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,BPWM_CH5 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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bitfld.long 0x00 7. "TRGEN4,BPWM_CH4 Trigger EADC Enable Bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,BPWM_CH4 Trigger EADC Source Select\nOthers reserved" "0: BPWM_CH4 zero point,1: BPWM_CH4 period point,2: BPWM_CH4 zero or period point,3: BPWM_CH4 up-count compared point,4: BPWM_CH4 down-count compared point,?,?,?,8: BPWM_CH5 up-count compared point,9: BPWM_CH5 down-count compared point,?..."
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group.long 0x110++0x03
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line.long 0x00 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)" "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit(Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x03
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line.long 0x00 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x00 21. "EADCTRG5,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRG4,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRG3,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRG2,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRG1,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRG0,EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Status\nNote: This bit can be cleared by software write 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x200++0x03
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line.long 0x00 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: BPWM Channel capture input path Disabled,1: BPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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|
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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newline
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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|
bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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|
newline
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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|
bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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|
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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|
rgroup.long 0x208++0x03
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|
line.long 0x00 "BPWM_CAPSTS,BPWM Capture Status Register"
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|
bitfld.long 0x00 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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newline
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bitfld.long 0x00 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
|
|
bitfld.long 0x00 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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|
newline
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bitfld.long 0x00 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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bitfld.long 0x00 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1" "0,1"
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newline
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bitfld.long 0x00 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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newline
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bitfld.long 0x00 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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newline
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bitfld.long 0x00 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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bitfld.long 0x00 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1" "0,1"
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rgroup.long 0x20C++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
|
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
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rgroup.long 0x210++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
|
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
|
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
|
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
|
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
|
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x22C++0x03
|
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line.long 0x00 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
|
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened the BPWM counter value will be saved in this register"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
|
|
bitfld.long 0x00 8.--13. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled,?..."
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|
bitfld.long 0x00 0.--5. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled,?..."
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
|
|
bitfld.long 0x00 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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|
bitfld.long 0x00 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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|
newline
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bitfld.long 0x00 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "BPWM_PBUF,BPWM PERIOD Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only)\nUsed as PERIOD active register"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only)\nUsed as CMP active register"
|
|
tree.end
|
|
tree.end
|
|
tree "CAN"
|
|
tree "CAN"
|
|
base ad:0x400A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CAN_CON,Control Register"
|
|
bitfld.long 0x00 7. "Test,Test Mode Enable Bit" "0: Normal Operation,1: Test Mode"
|
|
bitfld.long 0x00 6. "CCE,Configuration Change Enable Bit" "0: No write access to the Bit Timing Register,1: Write access to the Bit Timing Register.."
|
|
newline
|
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bitfld.long 0x00 5. "DAR,Automatic Re-transmission Disable Bit" "0: Automatic Retransmission of disturbed..,1: Automatic Retransmission Disabled"
|
|
bitfld.long 0x00 3. "EIE,Error Interrupt Enable Bit" "0: Disabled - No Error Status Interrupt will be..,1: Enabled - A change in the bits BOff.."
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|
newline
|
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bitfld.long 0x00 2. "SIE,Status Change Interrupt Enable Bit" "0: Disabled - No Status Change Interrupt will be..,1: Enabled - An interrupt will be generated when.."
|
|
bitfld.long 0x00 1. "IE,Module Interrupt Enable Bit" "0: Funcrion interrupt Disabled,1: Funcrion interrupt Enabled"
|
|
newline
|
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bitfld.long 0x00 0. "Init,Init Initialization" "0: Normal Operation,1: Initialization is started"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CAN_STATUS,Status Register"
|
|
rbitfld.long 0x00 7. "BOff,Bus-off Status (Read Only)" "0: The CAN module is not in bus-off state,1: The CAN module is in bus-off state"
|
|
rbitfld.long 0x00 6. "EWarn,Error Warning Status (Read Only)" "0: Both error counters are below the error..,1: At least one of the error counters in the EML.."
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newline
|
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rbitfld.long 0x00 5. "EPass,Error Passive (Read Only)" "0: The CAN Core is error active,1: The CAN Core is in the error passive state as.."
|
|
bitfld.long 0x00 4. "RxOK,Received a Message Successfully" "0: No message has been successfully received..,1: A message has been successfully received.."
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newline
|
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bitfld.long 0x00 3. "TxOK,Transmitted a Message Successfully" "0: Since this bit was reset by the CPU no..,1: Since this bit was last reset by the CPU a.."
|
|
bitfld.long 0x00 0.--2. "LEC,Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code which indicates the type of the last error to occur on the CAN bus" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CAN_ERR,Error Counter Register"
|
|
bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the.."
|
|
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CAN_BTIME,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. "TSeg2,Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0...7]" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 8.--11. "TSeg1,Time Segment Before the Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1...15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
bitfld.long 0x00 6.--7. "SJW,(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0...3]" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "BRP,Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CAN_IIDR,Interrupt Identifier Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntId,Interrupt Identifier (Indicates the Source of the Interrupt)\nIf several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest priority disregarding their chronological order"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAN_TEST,Test Register (Register Map Note 1)"
|
|
rbitfld.long 0x00 7. "Rx,Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)" "0: The CAN bus is dominant (CAN_RX = '0'),1: The CAN bus is recessive (CAN_RX = '1')"
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|
bitfld.long 0x00 5.--6. "Tx,Tx[1:0]: Control of CAN_TX Pin" "0: Reset value CAN_TX pin is controlled by the..,1: Sample Point can be monitored at CAN_TX pin,2: CAN_TX pin drives a dominant ('0') value,3: CAN_TX pin drives a recessive ('1') value"
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|
newline
|
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bitfld.long 0x00 4. "LBack,Loop Back Mode Enable Bit" "0: Loop Back Mode Disabled,1: Loop Back Mode Enabled"
|
|
bitfld.long 0x00 3. "Silent,Silent Mode" "0: Normal operation,1: The module is in Silent Mode"
|
|
newline
|
|
bitfld.long 0x00 2. "Basic,Basic Mode" "0: Basic Mode Disabled,1: IF1 Registers used as Tx Buffer IF2 Registers.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CAN_BRPE,Baud Rate Prescaler Extension Register"
|
|
bitfld.long 0x00 0.--3. "BRPE,BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CAN_IF1_CREQ,IFn (Register Map Note 2) Command Request Registers"
|
|
bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
|
|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CAN_IF2_CREQ,IFn (Register Map Note 2) Command Request Registers"
|
|
bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
|
|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CAN_IF1_CMASK,IFn Command Mask Registers"
|
|
bitfld.long 0x00 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
|
|
bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
|
|
newline
|
|
bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
|
|
bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
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|
newline
|
|
bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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|
bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
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|
bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
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group.long 0x84++0x03
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|
line.long 0x00 "CAN_IF2_CMASK,IFn Command Mask Registers"
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bitfld.long 0x00 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
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bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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|
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bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
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bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
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bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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|
bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
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bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
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|
group.long 0x28++0x03
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|
line.long 0x00 "CAN_IF1_MASK1,IFn Mask 1 Registers"
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|
hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x88++0x03
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|
line.long 0x00 "CAN_IF2_MASK1,IFn Mask 1 Registers"
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hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x2C++0x03
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line.long 0x00 "CAN_IF1_MASK2,IFn Mask 2 Registers"
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|
bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16"
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group.long 0x8C++0x03
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line.long 0x00 "CAN_IF2_MASK2,IFn Mask 2 Registers"
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bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16"
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|
group.long 0x30++0x03
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|
line.long 0x00 "CAN_IF1_ARB1,IFn Arbitration 1 Registers"
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hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x90++0x03
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line.long 0x00 "CAN_IF2_ARB1,IFn Arbitration 1 Registers"
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|
hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x34++0x03
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|
line.long 0x00 "CAN_IF1_ARB2,IFn Arbitration 2 Registers"
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|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
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bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.."
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bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
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hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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group.long 0x94++0x03
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line.long 0x00 "CAN_IF2_ARB2,IFn Arbitration 2 Registers"
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|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
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bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.."
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bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
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|
hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x38++0x03
|
|
line.long 0x00 "CAN_IF1_MCON,IFn Message Control Registers"
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bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.."
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bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
|
|
bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
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|
bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x98++0x03
|
|
line.long 0x00 "CAN_IF2_MCON,IFn Message Control Registers"
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|
bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.."
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bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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|
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bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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|
bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
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|
newline
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
|
|
bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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newline
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bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
|
|
bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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|
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|
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bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
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bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x3C++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CAN_IF2_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame"
|
|
group.long 0x40++0x03
|
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line.long 0x00 "CAN_IF1_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CAN_IF2_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame"
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|
group.long 0x44++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame"
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|
group.long 0xA4++0x03
|
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line.long 0x00 "CAN_IF2_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame"
|
|
group.long 0x48++0x03
|
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line.long 0x00 "CAN_IF1_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame"
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|
hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame"
|
|
group.long 0xA8++0x03
|
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line.long 0x00 "CAN_IF2_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame"
|
|
rgroup.long 0x100++0x03
|
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line.long 0x00 "CAN_TXREQ1,Transmission Request Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxRqst16_1,Transmission Request Bits 16-1 (of All Message Objects) (Read Only)"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAN_TXREQ2,Transmission Request Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxRqst32_17,Transmission Request Bits 32-17 (of All Message Objects) (Read Only)"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CAN_NDAT1,New Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "NewData16_1,New Data Bits 16-1 (of All Message Objects)"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CAN_NDAT2,New Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "NewData32_17,New Data Bits 32-17 (of All Message Objects)"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "CAN_IPND1,Interrupt Pending Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntPnd16_1,Interrupt Pending Bits 16-1 (of All Message Objects)"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "CAN_IPND2,Interrupt Pending Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntPnd32_17,Interrupt Pending Bits 32-17 (of All Message Objects)"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CAN_MVLD1,Message Valid Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MsgVal16_1,Message Valid Bits 16-1 (of All Message Objects) (Read Only)\nNote: CAN_MVLD1[0] means Message object No.1 is valid or not"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "CAN_MVLD2,Message Valid Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "MsgVal32_17,Message Valid Bits 32-17 (of All Message Objects) (Read Only)\nNote: CAN_MVLD2[15] means Message object No.32 is valid or not"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CAN_WU_EN,Wake-up Enable Control Register"
|
|
bitfld.long 0x00 0. "WAKUP_EN,Wake-up Enable Bit\nNote: User can wake up system when there is a falling edge in the CAN_Rx pin" "0: The wake-up function Disabled,1: The wake-up function Enabled"
|
|
group.long 0x16C++0x03
|
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line.long 0x00 "CAN_WU_STATUS,Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WAKUP_STS,Wake-up Status \nNote: This bit can be cleared by writing '0' to it" "0: No wake-up event occurred,1: Wake-up event occurred"
|
|
tree.end
|
|
tree "CAN_NS"
|
|
base ad:0x500A0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CAN_CON,Control Register"
|
|
bitfld.long 0x00 7. "Test,Test Mode Enable Bit" "0: Normal Operation,1: Test Mode"
|
|
bitfld.long 0x00 6. "CCE,Configuration Change Enable Bit" "0: No write access to the Bit Timing Register,1: Write access to the Bit Timing Register.."
|
|
newline
|
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bitfld.long 0x00 5. "DAR,Automatic Re-transmission Disable Bit" "0: Automatic Retransmission of disturbed..,1: Automatic Retransmission Disabled"
|
|
bitfld.long 0x00 3. "EIE,Error Interrupt Enable Bit" "0: Disabled - No Error Status Interrupt will be..,1: Enabled - A change in the bits BOff.."
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|
newline
|
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bitfld.long 0x00 2. "SIE,Status Change Interrupt Enable Bit" "0: Disabled - No Status Change Interrupt will be..,1: Enabled - An interrupt will be generated when.."
|
|
bitfld.long 0x00 1. "IE,Module Interrupt Enable Bit" "0: Funcrion interrupt Disabled,1: Funcrion interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 0. "Init,Init Initialization" "0: Normal Operation,1: Initialization is started"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CAN_STATUS,Status Register"
|
|
rbitfld.long 0x00 7. "BOff,Bus-off Status (Read Only)" "0: The CAN module is not in bus-off state,1: The CAN module is in bus-off state"
|
|
rbitfld.long 0x00 6. "EWarn,Error Warning Status (Read Only)" "0: Both error counters are below the error..,1: At least one of the error counters in the EML.."
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|
newline
|
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rbitfld.long 0x00 5. "EPass,Error Passive (Read Only)" "0: The CAN Core is error active,1: The CAN Core is in the error passive state as.."
|
|
bitfld.long 0x00 4. "RxOK,Received a Message Successfully" "0: No message has been successfully received..,1: A message has been successfully received.."
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|
newline
|
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bitfld.long 0x00 3. "TxOK,Transmitted a Message Successfully" "0: Since this bit was reset by the CPU no..,1: Since this bit was last reset by the CPU a.."
|
|
bitfld.long 0x00 0.--2. "LEC,Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code which indicates the type of the last error to occur on the CAN bus" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CAN_ERR,Error Counter Register"
|
|
bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the.."
|
|
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CAN_BTIME,Bit Timing Register"
|
|
bitfld.long 0x00 12.--14. "TSeg2,Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0...7]" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 8.--11. "TSeg1,Time Segment Before the Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1...15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "SJW,(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0...3]" "0,1,2,3"
|
|
bitfld.long 0x00 0.--5. "BRP,Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CAN_IIDR,Interrupt Identifier Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntId,Interrupt Identifier (Indicates the Source of the Interrupt)\nIf several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest priority disregarding their chronological order"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CAN_TEST,Test Register (Register Map Note 1)"
|
|
rbitfld.long 0x00 7. "Rx,Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)" "0: The CAN bus is dominant (CAN_RX = '0'),1: The CAN bus is recessive (CAN_RX = '1')"
|
|
bitfld.long 0x00 5.--6. "Tx,Tx[1:0]: Control of CAN_TX Pin" "0: Reset value CAN_TX pin is controlled by the..,1: Sample Point can be monitored at CAN_TX pin,2: CAN_TX pin drives a dominant ('0') value,3: CAN_TX pin drives a recessive ('1') value"
|
|
newline
|
|
bitfld.long 0x00 4. "LBack,Loop Back Mode Enable Bit" "0: Loop Back Mode Disabled,1: Loop Back Mode Enabled"
|
|
bitfld.long 0x00 3. "Silent,Silent Mode" "0: Normal operation,1: The module is in Silent Mode"
|
|
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|
|
bitfld.long 0x00 2. "Basic,Basic Mode" "0: Basic Mode Disabled,1: IF1 Registers used as Tx Buffer IF2 Registers.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CAN_BRPE,Baud Rate Prescaler Extension Register"
|
|
bitfld.long 0x00 0.--3. "BRPE,BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CAN_IF1_CREQ,IFn (Register Map Note 2) Command Request Registers"
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bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
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|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x80++0x03
|
|
line.long 0x00 "CAN_IF2_CREQ,IFn (Register Map Note 2) Command Request Registers"
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|
bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.."
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|
bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x24++0x03
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|
line.long 0x00 "CAN_IF1_CMASK,IFn Command Mask Registers"
|
|
bitfld.long 0x00 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
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bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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newline
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bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
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bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
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|
newline
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bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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newline
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
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bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
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group.long 0x84++0x03
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line.long 0x00 "CAN_IF2_CMASK,IFn Command Mask Registers"
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bitfld.long 0x00 7. "WR_RD,Write / Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.."
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bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.."
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|
newline
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bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).."
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bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.."
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newline
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bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object"
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|
bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.."
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|
newline
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bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.."
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|
bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CAN_IF1_MASK1,IFn Mask 1 Registers"
|
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hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x88++0x03
|
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line.long 0x00 "CAN_IF2_MASK1,IFn Mask 1 Registers"
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hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0"
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group.long 0x2C++0x03
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line.long 0x00 "CAN_IF1_MASK2,IFn Mask 2 Registers"
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bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
|
|
bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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newline
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16"
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group.long 0x8C++0x03
|
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line.long 0x00 "CAN_IF2_MASK2,IFn Mask 2 Registers"
|
|
bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.."
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bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.."
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newline
|
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hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CAN_IF1_ARB1,IFn Arbitration 1 Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CAN_IF2_ARB1,IFn Arbitration 1 Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x34++0x03
|
|
line.long 0x00 "CAN_IF1_ARB2,IFn Arbitration 2 Registers"
|
|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
|
|
bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.."
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|
newline
|
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bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
|
|
hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x94++0x03
|
|
line.long 0x00 "CAN_IF2_ARB2,IFn Arbitration 2 Registers"
|
|
bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.."
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|
bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.."
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newline
|
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bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit"
|
|
hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')"
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|
group.long 0x38++0x03
|
|
line.long 0x00 "CAN_IF1_MCON,IFn Message Control Registers"
|
|
bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.."
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bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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|
newline
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bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
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newline
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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newline
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bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
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bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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newline
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bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
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bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x98++0x03
|
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line.long 0x00 "CAN_IF2_MCON,IFn Message Control Registers"
|
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bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.."
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bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.."
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|
newline
|
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bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.."
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|
bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.."
|
|
newline
|
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bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
|
|
bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.."
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newline
|
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bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.."
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|
bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.."
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|
newline
|
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bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.."
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|
bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x3C++0x03
|
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line.long 0x00 "CAN_IF1_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
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|
hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame"
|
|
group.long 0x9C++0x03
|
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line.long 0x00 "CAN_IF2_DAT_A1,IFn Data A1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
|
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hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame"
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group.long 0xA0++0x03
|
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line.long 0x00 "CAN_IF2_DAT_A2,IFn Data A2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CAN_IF2_DAT_B1,IFn Data B1 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CAN_IF1_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CAN_IF2_DAT_B2,IFn Data B2 Registers (Register Map Note 3)"
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame"
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CAN_TXREQ1,Transmission Request Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxRqst16_1,Transmission Request Bits 16-1 (of All Message Objects) (Read Only)"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CAN_TXREQ2,Transmission Request Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "TxRqst32_17,Transmission Request Bits 32-17 (of All Message Objects) (Read Only)"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CAN_NDAT1,New Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "NewData16_1,New Data Bits 16-1 (of All Message Objects)"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CAN_NDAT2,New Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "NewData32_17,New Data Bits 32-17 (of All Message Objects)"
|
|
rgroup.long 0x140++0x03
|
|
line.long 0x00 "CAN_IPND1,Interrupt Pending Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntPnd16_1,Interrupt Pending Bits 16-1 (of All Message Objects)"
|
|
rgroup.long 0x144++0x03
|
|
line.long 0x00 "CAN_IPND2,Interrupt Pending Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "IntPnd32_17,Interrupt Pending Bits 32-17 (of All Message Objects)"
|
|
rgroup.long 0x160++0x03
|
|
line.long 0x00 "CAN_MVLD1,Message Valid Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "MsgVal16_1,Message Valid Bits 16-1 (of All Message Objects) (Read Only)\nNote: CAN_MVLD1[0] means Message object No.1 is valid or not"
|
|
rgroup.long 0x164++0x03
|
|
line.long 0x00 "CAN_MVLD2,Message Valid Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "MsgVal32_17,Message Valid Bits 32-17 (of All Message Objects) (Read Only)\nNote: CAN_MVLD2[15] means Message object No.32 is valid or not"
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CAN_WU_EN,Wake-up Enable Control Register"
|
|
bitfld.long 0x00 0. "WAKUP_EN,Wake-up Enable Bit\nNote: User can wake up system when there is a falling edge in the CAN_Rx pin" "0: The wake-up function Disabled,1: The wake-up function Enabled"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CAN_WU_STATUS,Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WAKUP_STS,Wake-up Status \nNote: This bit can be cleared by writing '0' to it" "0: No wake-up event occurred,1: Wake-up event occurred"
|
|
tree.end
|
|
tree.end
|
|
tree "CLK"
|
|
base ad:0x40000200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
|
|
bitfld.long 0x00 18. "HIRC48EN,HIRC48 Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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|
bitfld.long 0x00 13. "HXTTBEN,HXT Crystal TURBO Mode (Write Protect)\nNote: This bit is write protected" "0: HXT Crystal TURBO mode disabled,1: HXT Crystal TURBO mode enabled"
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|
newline
|
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bitfld.long 0x00 12. "HXTSELTYP,HXT Crystal Type Select Bit (Write Protect)\nNote: This bit is write protected" "0: Select INV type,1: Select GM type"
|
|
bitfld.long 0x00 10.--11. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally" "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,2: HXT frequency is from 12 MHz to 16 MHz,3: HXT frequency is higher than 16 MHz"
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|
newline
|
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bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then.."
|
|
bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if the EINT7~0 GPIO UART0~5 USBH USBD OTG CAN0 BOD ACMP WDT SDH0 TMR0~3 I2C0~2 USCI0~1 SPI4 RTC wake-up.." "0,1"
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|
newline
|
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bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high after resume from Power-down mode.\nNote2: This bit is write protected" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
|
|
bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
|
|
newline
|
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bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nThe HCLK default clock source is from HIRC and this bit default value is 1.\nNote1: This bit is write protected" "0: 12 MHz internal high speed RC oscillator..,1: 12 MHz internal high speed RC oscillator.."
|
|
bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
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bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: 4~24 MHz external high speed crystal (HXT)..,1: 4~24 MHz external high speed crystal (HXT).."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
|
|
bitfld.long 0x00 16. "USBHCKEN,USB HOST 1.1 Controller Clock Enable Bit" "0: USB HOST 1.1 peripheral clock Disabled,1: USB HOST 1.1 peripheral clock Enabled"
|
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bitfld.long 0x00 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC clock Disabled when chip is under IDLE mode,1: FMC clock Enabled when chip is under IDLE mode"
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bitfld.long 0x00 12. "CRPTCKEN,Cryptographic Accelerator Clock Enable Bit" "0: Cryptographic Accelerator clock Disabled,1: Cryptographic Accelerator clock Enabled"
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bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
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bitfld.long 0x00 6. "SDH0CKEN,SDHOST0 Controller Clock Enable Bit" "0: SDHOST0 peripheral clock Disabled,1: SDHOST0 peripheral clock Enabled"
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bitfld.long 0x00 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
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bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x00 1. "PDMA1CKEN,PDMA1 Controller Clock Enable Bit" "0: PDMA1 peripheral clock Disabled,1: PDMA1 peripheral clock Enabled"
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bitfld.long 0x00 0. "PDMA0CKEN,PDMA0 Controller Clock Enable Bit (Secure)" "0: PDMA0 peripheral clock Disabled,1: PDMA0 peripheral clock Enabled"
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group.long 0x08++0x03
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line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x00 29. "I2S0CKEN,I2S0 Clock Enable Bit" "0: I2S0 Clock Disabled,1: I2S0 Clock Enabled"
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bitfld.long 0x00 28. "EADCCKEN,Enhanced Analog-digital-converter (EADC) Clock Enable Bit" "0: EADC clock Disabled,1: EADC clock Enabled"
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bitfld.long 0x00 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled"
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bitfld.long 0x00 26. "OTGCKEN,USB OTG Clock Enable Bit" "0: USB OTG clock Disabled,1: USB OTG clock Enabled"
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bitfld.long 0x00 24. "CAN0CKEN,CAN0 Clock Enable Bit" "0: CAN0 clock Disabled,1: CAN0 clock Enabled"
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bitfld.long 0x00 21. "UART5CKEN,UART5 Clock Enable Bit" "0: UART5 clock Disabled,1: UART5 clock Enabled"
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bitfld.long 0x00 20. "UART4CKEN,UART4 Clock Enable Bit" "0: UART4 clock Disabled,1: UART4 clock Enabled"
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bitfld.long 0x00 19. "UART3CKEN,UART3 Clock Enable Bit" "0: UART3 clock Disabled,1: UART3 clock Enabled"
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bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x00 15. "SPI2CKEN,SPI2 Clock Enable Bit" "0: SPI2 clock Disabled,1: SPI2 clock Enabled"
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bitfld.long 0x00 14. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 clock Disabled,1: SPI1 clock Enabled"
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bitfld.long 0x00 13. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 clock Disabled,1: SPI0 clock Enabled"
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bitfld.long 0x00 12. "QSPI0CKEN,QSPI0 Clock Enable Bit" "0: QSPI0 clock Disabled,1: QSPI0 clock Enabled"
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bitfld.long 0x00 10. "I2C2CKEN,I2C2 Clock Enable Bit" "0: I2C2 clock Disabled,1: I2C2 clock Enabled"
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bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 clock Disabled,1: I2C1 clock Enabled"
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bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 clock Disabled,1: I2C0 clock Enabled"
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bitfld.long 0x00 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled"
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bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled"
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bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled"
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bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled"
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bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled"
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bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled"
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bitfld.long 0x00 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only" "0: RTC clock Disabled,1: RTC clock Enabled"
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bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled"
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group.long 0x0C++0x03
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line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
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bitfld.long 0x00 27. "ECAP1CKEN,ECAP1 Clock Enable Bit" "0: ECAP1 clock Disabled,1: ECAP1 clock Enabled"
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bitfld.long 0x00 26. "ECAP0CKEN,ECAP0 Clock Enable Bit" "0: ECAP0 clock Disabled,1: ECAP0 clock Enabled"
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bitfld.long 0x00 25. "TRNGCKEN,TRNG Clock Enable Bit" "0: TRNG clock Disabled,1: TRNG clock Enabled"
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bitfld.long 0x00 23. "QEI1CKEN,QEI1 Clock Enable Bit" "0: QEI1 clock Disabled,1: QEI1 clock Enabled"
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bitfld.long 0x00 22. "QEI0CKEN,QEI0 Clock Enable Bit" "0: QEI0 clock Disabled,1: QEI0 clock Enabled"
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bitfld.long 0x00 19. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
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bitfld.long 0x00 18. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
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bitfld.long 0x00 17. "EPWM1CKEN,EPWM1 Clock Enable Bit" "0: EPWM1 clock Disabled,1: EPWM1 clock Enabled"
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bitfld.long 0x00 16. "EPWM0CKEN,EPWM0 Clock Enable Bit" "0: EPWM0 clock Disabled,1: EPWM0 clock Enabled"
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bitfld.long 0x00 12. "DACCKEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled"
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bitfld.long 0x00 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
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bitfld.long 0x00 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
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bitfld.long 0x00 6. "SPI3CKEN,SPI3 Clock Enable Bit" "0: SPI3 clock Disabled,1: SPI3 clock Enabled"
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bitfld.long 0x00 2. "SC2CKEN,Smart Card 2 (SC2) Clock Enable Bit" "0: SC2 clock Disabled,1: SC2 clock Enabled"
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bitfld.long 0x00 1. "SC1CKEN,Smart Card 1 (SC1) Clock Enable Bit" "0: SC1 clock Disabled,1: SC1 clock Enabled"
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bitfld.long 0x00 0. "SC0CKEN,Smart Card 0 (SC0) Clock Enable Bit" "0: SC0 clock Disabled,1: SC0 clock Enabled"
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group.long 0x10++0x03
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line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x00 20.--21. "SDH0SEL,SDHOST0 Peripheral Clock Source Selection (Write Protect)\nNote: These bits are write protected" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from HCLK,3: Clock source from HIRC clock"
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bitfld.long 0x00 8. "USBSEL,USB Clock Source Selection (Write Protect)" "0: Reserved,1: Clock source from PLL"
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bitfld.long 0x00 3.--5. "STCLKSEL,SysTick Clock Source Selection (Write Protect)\nNote2: These bits are write protected" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2"
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from PLL,3: Clock source from LIRC,4: Reserved,5: Clock source from HIRC48,?,7: Clock source from HIRC"
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group.long 0x14++0x03
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line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x00 30.--31. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected" "?,?,2: Clock source from HCLK/2048,3: Clock source from 10 kHz internal low speed.."
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bitfld.long 0x00 28.--29. "CLKOSEL,Clock Output Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 26.--27. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 24.--25. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock TM3 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock TM2 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock TM1 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock TM0 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected" "0: Reserved,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK/2048,3: Clock source from 10 kHz internal low speed.."
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group.long 0x18++0x03
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line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x00 12.--13. "SPI3SEL,SPI3 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 10.--11. "SPI2SEL,SPI2 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from 12 MHz internal high speed.."
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rbitfld.long 0x00 9. "BPWM1SEL,BPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL" "?,1: Clock source from PCLK1"
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rbitfld.long 0x00 8. "BPWM0SEL,BPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL" "?,1: Clock source from PCLK0"
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bitfld.long 0x00 6.--7. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 4.--5. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 2.--3. "QSPI0SEL,QSPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 12 MHz internal high speed.."
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rbitfld.long 0x00 1. "EPWM1SEL,EPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL" "?,1: Clock source from PCLK1"
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rbitfld.long 0x00 0. "EPWM0SEL,EPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL" "?,1: Clock source from PCLK0"
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group.long 0x1C++0x03
|
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line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
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bitfld.long 0x00 30.--31. "UART5SEL,UART5 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 28.--29. "UART4SEL,UART4 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 26.--27. "UART3SEL,UART3 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 24.--25. "UART2SEL,UART2 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from 32.768 kHz external low..,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 16.--17. "I2S0SEL,I2S0 Clock Source Selection" "0: Clock source from HXT clock,1: Clock source from PLL clock,2: Clock source from PCLK0,3: Clock source from HIRC clock"
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bitfld.long 0x00 8. "RTCSEL,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low..,1: Clock source from 10 kHz internal low speed.."
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bitfld.long 0x00 4.--5. "SC2SEL,Smart Card 2 (SC2) Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 2.--3. "SC1SEL,Smart Card 1 (SC1) Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK1,3: Clock source from 12 MHz internal high speed.."
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bitfld.long 0x00 0.--1. "SC0SEL,Smart Card 0 (SC0) Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 12 MHz internal high speed.."
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group.long 0x20++0x03
|
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line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
|
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hexmask.long.byte 0x00 24.--31. 1. "SDH0DIV,SDHOST0 Clock Divide Number From SDHOST0 Clock Source"
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hexmask.long.byte 0x00 16.--23. 1. "EADCDIV,EADC Clock Divide Number From EADC Clock Source"
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bitfld.long 0x00 12.--15. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "USBDIV,USB Clock Divide Number From PLL Clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x24++0x03
|
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line.long 0x00 "CLK_CLKDIV1,Clock Divider Number Register 1"
|
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hexmask.long.byte 0x00 16.--23. 1. "SC2DIV,Smart Card 2 (SC2) Clock Divide Number From SC2 Clock Source"
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hexmask.long.byte 0x00 8.--15. 1. "SC1DIV,Smart Card 1 (SC1) Clock Divide Number From SC1 Clock Source"
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hexmask.long.byte 0x00 0.--7. 1. "SC0DIV,Smart Card 0 (SC0) Clock Divide Number From SC0 Clock Source"
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group.long 0x30++0x03
|
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line.long 0x00 "CLK_CLKDIV4,Clock Divider Number Register 4"
|
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bitfld.long 0x00 12.--15. "UART5DIV,UART5 Clock Divide Number From UART5 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "UART4DIV,UART4 Clock Divide Number From UART4 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "UART3DIV,UART3 Clock Divide Number From UART3 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "UART2DIV,UART2 Clock Divide Number From UART2 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x34++0x03
|
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line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register"
|
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bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock Divider\nAPB1 clock can be divided from HCLK" "0: PCLK1 frequency is HCLK,1: PCLK1 frequency is 1/2 HCLK,2: PCLK1 frequency is 1/4 HCLK,3: PCLK1 frequency is 1/8 HCLK,4: PCLK1 frequency is 1/16 HCLK,5: PCLK1 frequency is 1/32 HCLK,?..."
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bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock Divider\nAPB0 clock can be divided from HCLK" "0: PCLK0 frequency is HCLK,1: PCLK0 frequency is 1/2 HCLK,2: PCLK0 frequency is 1/4 HCLK,3: PCLK0 frequency is 1/8 HCLK,4: PCLK0 frequency is 1/16 HCLK,5: PCLK0 frequency is 1/32 HCLK,?..."
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group.long 0x40++0x03
|
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line.long 0x00 "CLK_PLLCTL,PLL Control Register"
|
|
bitfld.long 0x00 23. "STBSEL,PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected" "0: PLL stable time is 1200 PLL source clock..,1: PLL stable time is 2400 PLL source clock.."
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bitfld.long 0x00 19. "PLLSRC,PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected" "0: PLL source clock from 4~24 MHz external..,1: PLL source clock from 12 MHz internal.."
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Control (Write Protect)\nNote: This bit is write protected" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
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bitfld.long 0x00 17. "BP,PLL Bypass Control (Write Protect)\nNote: This bit is write protected" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
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bitfld.long 0x00 16. "PD,Power-down Mode (Write Protect)\nNote1: If set the PDEN bit to 1 in CLK_PWRCTL register the PLL will enter Power-down mode too.\nNote2: This bit is write protected" "0: PLL is enable (in normal mode),1: PLL is disable (in Power-down mode) (default)"
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bitfld.long 0x00 14.--15. "OUTDIV,PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected" "0,1,2,3"
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bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected"
|
|
rgroup.long 0x50++0x03
|
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line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x00 9. "LIRC32STB,LIRC32 Clock Source Stable Flag (Read Only)" "0: 32 kHz internal low speed RC oscillator..,1: 32 kHz internal low speed RC oscillator.."
|
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bitfld.long 0x00 8. "EXTLXTSTB,EXTLXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x00 6. "HIRC48STB,HIRC48 Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 12 MHz internal high speed RC oscillator..,1: 12 MHz internal high speed RC oscillator.."
|
|
bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
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bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
|
|
bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)\nLXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7])" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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|
group.long 0x60++0x03
|
|
line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register"
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|
bitfld.long 0x00 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz frequency..,1: 1 Hz clock output for 32.768 kHz frequency.."
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|
bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
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|
newline
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bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
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|
bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
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|
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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|
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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|
newline
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bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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|
newline
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bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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|
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit\n" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register"
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|
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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|
newline
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bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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|
group.long 0x78++0x03
|
|
line.long 0x00 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register"
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hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1"
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|
group.long 0x7C++0x03
|
|
line.long 0x00 "CLK_CDLOWB,Clock Frequency Detector Lower Boundary Register"
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|
hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will set to 1"
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|
group.long 0x90++0x03
|
|
line.long 0x00 "CLK_PMUCTL,Power Manager Control Register"
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|
bitfld.long 0x00 23. "RTCWKEN,RTC Wake-up Enable (Write Protect)\nNote: This bit is write protected" "0: RTC wake-up Disabled in Deep Power-down mode..,1: RTC wake-up Enabled at Deep Power-down mode.."
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bitfld.long 0x00 18. "ACMPSPWK,ACMP Standby Power-down Mode Wake-up Enable (Write Protect)\nNote: This bit is write protected" "0: ACMP wake-up Disabled in Standby Power-down..,1: ACMP wake-up Enabled in Standby Power-down mode"
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newline
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bitfld.long 0x00 16.--17. "WKPINEN,Wake-up Pin Enable (Write Protect)\nNote: These bits are write protected" "0: Wake-up pin Disabled in Deep Power-down mode,1: Wake-up pin rising edge Enabled in Deep..,2: Wake-up pin falling edge Enabled in Deep..,3: Wake-up pin both edge Enabled in Deep.."
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bitfld.long 0x00 9.--11. "WKTMRIS,Wake-up Timer Time-out Interval Select (Write Protect)\nThese bits control wake-up timer time-out interval when chip is under Deep Power-down mode or Standby Power-down mode.\nNote: These bits are write protected" "0: Time-out interval is 128 OSC10K clocks (12.8ms),1: Time-out interval is 256 OSC10K clocks (25.6ms),2: Time-out interval is 512 OSC10K clocks (51.2ms),3: Time-out interval is 1024 OSC10K clocks..,4: Time-out interval is 4096 OSC10K clocks..,5: Time-out interval is 8192 OSC10K clocks..,6: Time-out interval is 16384 OSC10K clocks..,7: Time-out interval is 65536 OSC10K clocks.."
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newline
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bitfld.long 0x00 8. "WKTMREN,Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Wake-up timer disabled at Deep Power-down..,1: Wake-up timer enabled at Deep Power-down mode.."
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bitfld.long 0x00 0.--2. "PDMSEL,Power-down Mode Selection (Write Protect)\nThese bits control chip Power-down mode grade selection when CPU executes WFI/WFE instruction.\nNote: These bits are write protected" "0: Power-down mode is selected (PD),1: Low leakage Power-down mode is selected (LLPD),2: Fast wake-up Power-down (FWPD),3: Ultra low leakage Power-down mode is selected..,4: Standby Power-down mode is selected (SPD),5: Reserved,6: Deep Power-down mode is selected (DPD),7: Reserved"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CLK_PMUSTS,Power Manager Status Register"
|
|
bitfld.long 0x00 31. "CLRWK,Clear Wake-up Flage\nNote: This bit is auto cleared by hardware" "0: No clear,1: Clear all of wake-up flag"
|
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rbitfld.long 0x00 14. "ACMPWK,ACMP Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition" "0,1"
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newline
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rbitfld.long 0x00 13. "BODWK,BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened" "0,1"
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rbitfld.long 0x00 12. "LVRWK,LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a LVR happened" "0,1"
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newline
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rbitfld.long 0x00 11. "GPDWK,GPD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins" "0,1"
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rbitfld.long 0x00 10. "GPCWK,GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins" "0,1"
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newline
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rbitfld.long 0x00 9. "GPBWK,GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins" "0,1"
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rbitfld.long 0x00 8. "GPAWK,GPA Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins" "0,1"
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newline
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rbitfld.long 0x00 2. "RTCWK,RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm tick time or tamper happened" "0,1"
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rbitfld.long 0x00 1. "TMRWK,Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out" "0,1"
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newline
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rbitfld.long 0x00 0. "PINWK,Pin Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0)" "0,1"
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|
group.long 0x9C++0x03
|
|
line.long 0x00 "CLK_SWKDBCTL,Standby Power-down Wake-up De-bounce Control Register"
|
|
bitfld.long 0x00 0.--3. "SWKDBCLKSEL,Standby Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC)" "0: Sample wake-up input once per 1 clocks,1: Sample wake-up input once per 2 clocks,2: Sample wake-up input once per 4 clocks,3: Sample wake-up input once per 8 clocks,4: Sample wake-up input once per 16 clocks,5: Sample wake-up input once per 32 clocks,6: Sample wake-up input once per 64 clocks,7: Sample wake-up input once per 128 clocks,8: Sample wake-up input once per 256 clocks,9: Sample wake-up input once per 2*256 clocks,10: Sample wake-up input once per 4*256 clocks,11: Sample wake-up input once per 8*256 clocks,12: Sample wake-up input once per 16*256 clocks,13: Sample wake-up input once per 32*256 clocks,14: Sample wake-up input once per 64*256 clocks,15: Sample wake-up input once per 128*256 clocks"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CLK_PASWKCTL,GPA Standby Power-down Wake-up Control Register"
|
|
bitfld.long 0x00 8. "DBEN,GPA Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO" "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
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bitfld.long 0x00 4.--7. "WKPSEL,GPA Standby Power-down Wake-up Pin Select" "0: GPA.0 wake-up function enabled,1: GPA.1 wake-up function enabled,2: GPA.2 wake-up function enabled,3: GPA.3 wake-up function enabled,4: GPA.4 wake-up function enabled,5: GPA.5 wake-up function enabled,6: GPA.6 wake-up function enabled,7: GPA.7 wake-up function enabled,8: GPA.8 wake-up function enabled,9: GPA.9 wake-up function enabled,10: GPA.10 wake-up function enabled,11: GPA.11 wake-up function enabled,12: GPA.12 wake-up function enabled,13: GPA.13 wake-up function enabled,14: GPA.14 wake-up function enabled,15: GPA.15 wake-up function enabled"
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newline
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bitfld.long 0x00 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPA group pin falling edge wake-up function..,1: GPA group pin falling edge wake-up function.."
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bitfld.long 0x00 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPA group pin rising edge wake-up function..,1: GPA group pin rising edge wake-up function.."
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newline
|
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bitfld.long 0x00 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPA group pin wake-up function Disabled,1: GPA group pin wake-up function Enabled"
|
|
group.long 0xA4++0x03
|
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line.long 0x00 "CLK_PBSWKCTL,GPB Standby Power-down Wake-up Control Register"
|
|
bitfld.long 0x00 8. "DBEN,GPB Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO" "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
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bitfld.long 0x00 4.--7. "WKPSEL,GPB Standby Power-down Wake-up Pin Select" "0: GPB.0 wake-up function enabled,1: GPB.1 wake-up function enabled,2: GPB.2 wake-up function enabled,3: GPB.3 wake-up function enabled,4: GPB.4 wake-up function enabled,5: GPB.5 wake-up function enabled,6: GPB.6 wake-up function enabled,7: GPB.7 wake-up function enabled,8: GPB.8 wake-up function enabled,9: GPB.9 wake-up function enabled,10: GPB.10 wake-up function enabled,11: GPB.11 wake-up function enabled,12: GPB.12 wake-up function enabled,13: GPB.13 wake-up function enabled,14: GPB.14 wake-up function enabled,15: GPB.15 wake-up function enabled"
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newline
|
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bitfld.long 0x00 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPB group pin falling edge wake-up function..,1: GPB group pin falling edge wake-up function.."
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bitfld.long 0x00 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPB group pin rising edge wake-up function..,1: GPB group pin rising edge wake-up function.."
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newline
|
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bitfld.long 0x00 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPB group pin wake-up function Disabled,1: GPB group pin wake-up function Enabled"
|
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group.long 0xA8++0x03
|
|
line.long 0x00 "CLK_PCSWKCTL,GPC Standby Power-down Wake-up Control Register"
|
|
bitfld.long 0x00 8. "DBEN,GPC Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO" "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
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bitfld.long 0x00 4.--7. "WKPSEL,GPC Standby Power-down Wake-up Pin Select" "0: GPC.0 wake-up function enabled,1: GPC.1 wake-up function enabled,2: GPC.2 wake-up function enabled,3: GPC.3 wake-up function enabled,4: GPC.4 wake-up function enabled,5: GPC.5 wake-up function enabled,6: GPC.6 wake-up function enabled,7: GPC.7 wake-up function enabled,8: GPC.8 wake-up function enabled,9: GPC.9 wake-up function enabled,10: GPC.10 wake-up function enabled,11: GPC.11 wake-up function enabled,12: GPC.12 wake-up function enabled,13: GPC.13 wake-up function enabled,14: Reserved,15: Reserved"
|
|
newline
|
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bitfld.long 0x00 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPC group pin falling edge wake-up function..,1: GPC group pin falling edge wake-up function.."
|
|
bitfld.long 0x00 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPC group pin rising edge wake-up function..,1: GPC group pin rising edge wake-up function.."
|
|
newline
|
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bitfld.long 0x00 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPC group pin wake-up function Disabled,1: GPC group pin wake-up function Enabled"
|
|
group.long 0xAC++0x03
|
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line.long 0x00 "CLK_PDSWKCTL,GPD Standby Power-down Wake-up Control Register"
|
|
bitfld.long 0x00 8. "DBEN,GPD Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO" "0: Standby power-down wake-up pin De-bounce..,1: Standby power-down wake-up pin De-bounce.."
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|
bitfld.long 0x00 4.--7. "WKPSEL,GPD Standby Power-down Wake-up Pin Select" "0: GPD.0 wake-up function enabled,1: GPD.1 wake-up function enabled,2: GPD.2 wake-up function enabled,3: GPD.3 wake-up function enabled,4: GPD.4 wake-up function enabled,5: GPD.5 wake-up function enabled,6: GPD.6 wake-up function enabled,7: GPD.7 wake-up function enabled,8: GPD.8 wake-up function enabled,9: GPD.9 wake-up function enabled,10: GPD.10 wake-up function enabled,11: GPD.11 wake-up function enabled,12: GPD.12 wake-up function enabled,13: GPD.13 wake-up function enabled,14: GPD.14 wake-up function enabled,15: Reserved"
|
|
newline
|
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bitfld.long 0x00 2. "PFWKEN,Pin Falling Edge Wake-up Enable Bit" "0: GPD group pin falling edge wake-up function..,1: GPD group pin falling edge wake-up function.."
|
|
bitfld.long 0x00 1. "PRWKEN,Pin Rising Edge Wake-up Enable Bit" "0: GPD group pin rising edge wake-up function..,1: GPD group pin rising edge wake-up function.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKEN,Standby Power-down Pin Wake-up Enable Bit" "0: GPD group pin wake-up function Disabled,1: GPD group pin wake-up function Enabled"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CLK_IOPDCTL,GPIO Standby Power-down Control Register"
|
|
bitfld.long 0x00 0. "IOHR,GPIO Hold Release\nWhen GPIO enters standby power-down mode all I/O status are hold to keep normal operating status" "0,1"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CLK_HXTFSEL,HXT Filter Select Control Register"
|
|
bitfld.long 0x00 0. "HXTFSEL,HXT Filter Select" "0: HXT frequency is larger than 12 MHz,1: HXT frequency is less than or equal to 12 MHz"
|
|
tree.end
|
|
tree "CRC"
|
|
tree "CRC"
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.."
|
|
newline
|
|
bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result"
|
|
tree.end
|
|
tree "CRC_NS"
|
|
base ad:0x50031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
|
bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.."
|
|
newline
|
|
bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result"
|
|
tree.end
|
|
tree.end
|
|
tree "CRYPTO"
|
|
tree "AES"
|
|
base ad:0x40032100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_AES_CTL,AES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT" "0: No effect,1: Protect the content of the AES key from reading"
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 24.--25. "CHANNEL,AES Engine Working Channel" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
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bitfld.long 0x00 23. "INSWAP,AES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
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newline
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bitfld.long 0x00 22. "OUTSWAP,AES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU outputs data from the.."
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bitfld.long 0x00 16. "ENCRYPTO,AES Encryption/Decryption" "0: AES engine executes decryption operation,1: AES engine executes encryption operation"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "OPMODE,AES Engine Operation Modes"
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bitfld.long 0x00 7. "DMAEN,AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: AES DMA engine Disabled,1: AES_DMA engine Enabled"
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newline
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bitfld.long 0x00 6. "DMACSCAD,AES Engine DMA with Cascade Mode" "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
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bitfld.long 0x00 5. "DMALAST,AES Last Block\nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set when feeding in the last block of data in ECB CBC CTR OFB and CFB mode and feeding in the (last-1) block of data at.." "0,1"
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newline
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bitfld.long 0x00 2.--3. "KEYSZ,AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1 updating this register has no effect" "0,1,2,3"
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bitfld.long 0x00 1. "STOP,AES Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop AES engine"
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newline
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bitfld.long 0x00 0. "START,AES Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start AES engine"
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rgroup.long 0x04++0x03
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line.long 0x00 "CRYPTO_AES_STS,AES Engine Flag"
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bitfld.long 0x00 20. "BUSERR,AES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and AES.."
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bitfld.long 0x00 18. "OUTBUFERR,AES Out Buffer Error Flag" "0: No error,1: Error happens during getting the result from.."
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newline
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bitfld.long 0x00 17. "OUTBUFFULL,AES Out Buffer Full Flag" "0: AES output buffer is not full,1: AES output buffer is full and software needs.."
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bitfld.long 0x00 16. "OUTBUFEMPTY,AES Out Buffer Empty" "0: AES output buffer is not empty,1: AES output buffer is empty"
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newline
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bitfld.long 0x00 12. "CNTERR,CRYPTO_AESn_CNT Setting Error" "0: No error in CRYPTO_AESn_CNT setting,1: CRYPTO_AESn_CNT is 0 or not a multiply of 16.."
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bitfld.long 0x00 10. "INBUFERR,AES Input Buffer Error Flag" "0: No error,1: Error happens during feeding data to the AES.."
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newline
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bitfld.long 0x00 9. "INBUFFULL,AES Input Buffer Full Flag" "0: AES input buffer is not full,1: AES input buffer is full"
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bitfld.long 0x00 8. "INBUFEMPTY,AES Input Buffer Empty" "0: There are some data in input buffer waiting..,1: AES input buffer is empty"
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newline
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bitfld.long 0x00 0. "BUSY,AES Engine Busy" "0: The AES engine is idle or finished,1: The AES engine is under processing"
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group.long 0x08++0x03
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line.long 0x00 "CRYPTO_AES_DATIN,AES Engine Data Input Port Register"
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hexmask.long 0x00 0.--31. 1. "DATIN,AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS"
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rgroup.long 0x0C++0x03
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line.long 0x00 "CRYPTO_AES_DATOUT,AES Engine Data Output Port Register"
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hexmask.long 0x00 0.--31. 1. "DATOUT,AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS"
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group.long 0x10++0x03
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line.long 0x00 "CRYPTO_AES0_KEY0,AES Key Word 0 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x14++0x03
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line.long 0x00 "CRYPTO_AES0_KEY1,AES Key Word 1 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x18++0x03
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line.long 0x00 "CRYPTO_AES0_KEY2,AES Key Word 2 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x1C++0x03
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line.long 0x00 "CRYPTO_AES0_KEY3,AES Key Word 3 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x20++0x03
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line.long 0x00 "CRYPTO_AES0_KEY4,AES Key Word 4 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x24++0x03
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line.long 0x00 "CRYPTO_AES0_KEY5,AES Key Word 5 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x28++0x03
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line.long 0x00 "CRYPTO_AES0_KEY6,AES Key Word 6 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x2C++0x03
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line.long 0x00 "CRYPTO_AES0_KEY7,AES Key Word 7 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x30++0x03
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line.long 0x00 "CRYPTO_AES0_IV0,AES Initial Vector Word 0 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
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group.long 0x34++0x03
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line.long 0x00 "CRYPTO_AES0_IV1,AES Initial Vector Word 1 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
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group.long 0x38++0x03
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line.long 0x00 "CRYPTO_AES0_IV2,AES Initial Vector Word 2 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
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group.long 0x3C++0x03
|
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line.long 0x00 "CRYPTO_AES0_IV3,AES Initial Vector Word 3 Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
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group.long 0x40++0x03
|
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line.long 0x00 "CRYPTO_AES0_SADDR,AES DMA Source Address Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
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group.long 0x44++0x03
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line.long 0x00 "CRYPTO_AES0_DADDR,AES DMA Destination Address Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
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group.long 0x48++0x03
|
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line.long 0x00 "CRYPTO_AES0_CNT,AES Byte Count Register for Channel 0"
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hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
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group.long 0x4C++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY0,AES Key Word 0 Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x50++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY1,AES Key Word 1 Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY2,AES Key Word 2 Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x58++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY3,AES Key Word 3 Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x5C++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY4,AES Key Word 4 Register for Channel 1"
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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|
group.long 0x60++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY5,AES Key Word 5 Register for Channel 1"
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|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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|
group.long 0x64++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY6,AES Key Word 6 Register for Channel 1"
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|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
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group.long 0x68++0x03
|
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line.long 0x00 "CRYPTO_AES1_KEY7,AES Key Word 7 Register for Channel 1"
|
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hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV0,AES Initial Vector Word 0 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV1,AES Initial Vector Word 1 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV2,AES Initial Vector Word 2 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV3,AES Initial Vector Word 3 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_SADDR,AES DMA Source Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CRYPTO_AES1_DADDR,AES DMA Destination Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRYPTO_AES1_CNT,AES Byte Count Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY0,AES Key Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY1,AES Key Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY2,AES Key Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY3,AES Key Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY4,AES Key Word 4 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY5,AES Key Word 5 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY6,AES Key Word 6 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY7,AES Key Word 7 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV0,AES Initial Vector Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV1,AES Initial Vector Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV2,AES Initial Vector Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV3,AES Initial Vector Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CRYPTO_AES2_SADDR,AES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CRYPTO_AES2_DADDR,AES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_CNT,AES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY0,AES Key Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY1,AES Key Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY2,AES Key Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY3,AES Key Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY4,AES Key Word 4 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY5,AES Key Word 5 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY6,AES Key Word 6 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY7,AES Key Word 7 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV0,AES Initial Vector Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV1,AES Initial Vector Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV2,AES Initial Vector Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV3,AES Initial Vector Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_SADDR,AES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_DADDR,AES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_CNT,AES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
tree.end
|
|
tree "AES_NS"
|
|
base ad:0x50032100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_AES_CTL,AES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT" "0: No effect,1: Protect the content of the AES key from reading"
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CHANNEL,AES Engine Working Channel" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
|
|
bitfld.long 0x00 23. "INSWAP,AES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 22. "OUTSWAP,AES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU outputs data from the.."
|
|
bitfld.long 0x00 16. "ENCRYPTO,AES Encryption/Decryption" "0: AES engine executes decryption operation,1: AES engine executes encryption operation"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "OPMODE,AES Engine Operation Modes"
|
|
bitfld.long 0x00 7. "DMAEN,AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: AES DMA engine Disabled,1: AES_DMA engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "DMACSCAD,AES Engine DMA with Cascade Mode" "0: DMA cascade function Disabled,1: In DMA cascade mode software can update DMA.."
|
|
bitfld.long 0x00 5. "DMALAST,AES Last Block\nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set when feeding in the last block of data in ECB CBC CTR OFB and CFB mode and feeding in the (last-1) block of data at.." "0,1"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "KEYSZ,AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1 updating this register has no effect" "0,1,2,3"
|
|
bitfld.long 0x00 1. "STOP,AES Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop AES engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,AES Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start AES engine"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_AES_STS,AES Engine Flag"
|
|
bitfld.long 0x00 20. "BUSERR,AES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and AES.."
|
|
bitfld.long 0x00 18. "OUTBUFERR,AES Out Buffer Error Flag" "0: No error,1: Error happens during getting the result from.."
|
|
newline
|
|
bitfld.long 0x00 17. "OUTBUFFULL,AES Out Buffer Full Flag" "0: AES output buffer is not full,1: AES output buffer is full and software needs.."
|
|
bitfld.long 0x00 16. "OUTBUFEMPTY,AES Out Buffer Empty" "0: AES output buffer is not empty,1: AES output buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 12. "CNTERR,CRYPTO_AESn_CNT Setting Error" "0: No error in CRYPTO_AESn_CNT setting,1: CRYPTO_AESn_CNT is 0 or not a multiply of 16.."
|
|
bitfld.long 0x00 10. "INBUFERR,AES Input Buffer Error Flag" "0: No error,1: Error happens during feeding data to the AES.."
|
|
newline
|
|
bitfld.long 0x00 9. "INBUFFULL,AES Input Buffer Full Flag" "0: AES input buffer is not full,1: AES input buffer is full"
|
|
bitfld.long 0x00 8. "INBUFEMPTY,AES Input Buffer Empty" "0: There are some data in input buffer waiting..,1: AES input buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,AES Engine Busy" "0: The AES engine is idle or finished,1: The AES engine is under processing"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_AES_DATIN,AES Engine Data Input Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_AES_DATOUT,AES Engine Data Output Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATOUT,AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY0,AES Key Word 0 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY1,AES Key Word 1 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY2,AES Key Word 2 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY3,AES Key Word 3 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY4,AES Key Word 4 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY5,AES Key Word 5 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY6,AES Key Word 6 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_AES0_KEY7,AES Key Word 7 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_AES0_IV0,AES Initial Vector Word 0 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_AES0_IV1,AES Initial Vector Word 1 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CRYPTO_AES0_IV2,AES Initial Vector Word 2 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CRYPTO_AES0_IV3,AES Initial Vector Word 3 Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRYPTO_AES0_SADDR,AES DMA Source Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRYPTO_AES0_DADDR,AES DMA Destination Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_AES0_CNT,AES Byte Count Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY0,AES Key Word 0 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY1,AES Key Word 1 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY2,AES Key Word 2 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY3,AES Key Word 3 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY4,AES Key Word 4 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY5,AES Key Word 5 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY6,AES Key Word 6 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRYPTO_AES1_KEY7,AES Key Word 7 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV0,AES Initial Vector Word 0 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV1,AES Initial Vector Word 1 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV2,AES Initial Vector Word 2 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CRYPTO_AES1_IV3,AES Initial Vector Word 3 Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CRYPTO_AES1_SADDR,AES DMA Source Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CRYPTO_AES1_DADDR,AES DMA Destination Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRYPTO_AES1_CNT,AES Byte Count Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY0,AES Key Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY1,AES Key Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY2,AES Key Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY3,AES Key Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY4,AES Key Word 4 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY5,AES Key Word 5 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY6,AES Key Word 6 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_AES2_KEY7,AES Key Word 7 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV0,AES Initial Vector Word 0 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV1,AES Initial Vector Word 1 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV2,AES Initial Vector Word 2 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CRYPTO_AES2_IV3,AES Initial Vector Word 3 Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CRYPTO_AES2_SADDR,AES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CRYPTO_AES2_DADDR,AES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CRYPTO_AES2_CNT,AES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY0,AES Key Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY1,AES Key Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY2,AES Key Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY3,AES Key Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY4,AES Key Word 4 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY5,AES Key Word 5 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY6,AES Key Word 6 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_KEY7,AES Key Word 7 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128 192 or 256 bits and four six or eight 32-bit registers are to store each security key"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV0,AES Initial Vector Word 0 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV1,AES Initial Vector Word 1 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV2,AES Initial Vector Word 2 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_AES3_IV3,AES Initial Vector Word 3 Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0 CRYPTO_AESn_IV1 CRYPTO_AESn_IV2 and CRYPTO_AESn_IV3) are for AES operating in CBC CFB and OFB mode"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CRYPTO_AES3_SADDR,AES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "CRYPTO_AES3_DADDR,AES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "CRYPTO_AES3_CNT,AES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode"
|
|
tree.end
|
|
tree "CRYPTO"
|
|
base ad:0x40032000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_INTEN,Crypto Interrupt Enable Control Register"
|
|
bitfld.long 0x00 25. "SHAEIEN,SHA Error Interrupt Enable Bit" "0: SHA error interrupt flag Disabled,1: SHA error interrupt flag Enabled"
|
|
bitfld.long 0x00 24. "SHAIEN,SHA Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine" "0: SHA interrupt Disabled,1: SHA interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. "ECCEIEN,ECC Error Interrupt Enable Bit" "0: ECC error interrupt flag Disabled,1: ECC error interrupt flag Enabled"
|
|
bitfld.long 0x00 22. "ECCIEN,ECC Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine" "0: ECC interrupt Disabled,1: ECC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIEN,PRNG Interrupt Enable Bit" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
|
|
bitfld.long 0x00 9. "TDESEIEN,TDES/DES Error Flag Enable Bit" "0: TDES/DES error interrupt flag Disabled,1: TDES/DES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIEN,TDES/DES Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine" "0: TDES/DES interrupt Disabled,1: TDES/DES interrupt Enabled"
|
|
bitfld.long 0x00 1. "AESEIEN,AES Error Flag Enable Bit" "0: AES error interrupt flag Disabled,1: AES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIEN,AES Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine" "0: AES interrupt Disabled,1: AES interrupt Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_INTSTS,Crypto Interrupt Flag"
|
|
bitfld.long 0x00 25. "SHAEIF,SHA Error Flag\nThis register includes operating and setting error" "0: No SHA error,1: SHA error interrupt"
|
|
bitfld.long 0x00 24. "SHAIF,SHA Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No SHA interrupt,1: SHA operation done interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. "ECCEIF,ECC Error Flag\nThis register includes operating and setting error" "0: No ECC error,1: ECC error interrupt"
|
|
bitfld.long 0x00 22. "ECCIF,ECC Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No ECC interrupt,1: ECC operation done interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIF,PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No PRNG interrupt,1: PRNG key generation done interrupt"
|
|
bitfld.long 0x00 9. "TDESEIF,TDES/DES Error Flag\nThis bit includes the operating and setting error" "0: No TDES/DES error,1: TDES/DES encryption/decryption error interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIF,TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No TDES/DES interrupt,1: TDES/DES encryption/decryption done interrupt"
|
|
bitfld.long 0x00 1. "AESEIF,AES Error Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No AES error,1: AES encryption/decryption error interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIF,AES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No AES interrupt,1: AES encryption/decryption done interrupt"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_CTL,PRNG Control Register"
|
|
rbitfld.long 0x00 8. "BUSY,PRNG Busy (Read Only)" "0: PRNG engine is idle,1: Indicate that the PRNG engine is generating.."
|
|
bitfld.long 0x00 2.--3. "KEYSZ,PRNG Generate Key Size" "0: 64 bits,1: 128 bits,2: 192 bits,3: 256 bits"
|
|
newline
|
|
bitfld.long 0x00 1. "SEEDRLD,Reload New Seed for PRNG Engine" "0: Generating key based on the current seed,1: Reload new seed"
|
|
bitfld.long 0x00 0. "START,Start PRNG Engine" "0: Stop PRNG engine,1: Generate new key and store the new key to.."
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_SEED,Seed for PRNG"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY0,PRNG Generated Key0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY1,PRNG Generated Key1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY2,PRNG Generated Key2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY3,PRNG Generated Key3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY4,PRNG Generated Key4"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY5,PRNG Generated Key5"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY6,PRNG Generated Key6"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY7,PRNG Generated Key7"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK0,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK1,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK2,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK3,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_TDES_FDBCKH,TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH CRYPTO_TDESn_IVL} for the next block in DMA cascade mode"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_TDES_FDBCKL,TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH CRYPTO_TDESn_IVL} for the next block in DMA cascade mode"
|
|
tree.end
|
|
tree "CRYPTO_NS"
|
|
base ad:0x50032000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_INTEN,Crypto Interrupt Enable Control Register"
|
|
bitfld.long 0x00 25. "SHAEIEN,SHA Error Interrupt Enable Bit" "0: SHA error interrupt flag Disabled,1: SHA error interrupt flag Enabled"
|
|
bitfld.long 0x00 24. "SHAIEN,SHA Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine" "0: SHA interrupt Disabled,1: SHA interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. "ECCEIEN,ECC Error Interrupt Enable Bit" "0: ECC error interrupt flag Disabled,1: ECC error interrupt flag Enabled"
|
|
bitfld.long 0x00 22. "ECCIEN,ECC Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine" "0: ECC interrupt Disabled,1: ECC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIEN,PRNG Interrupt Enable Bit" "0: PRNG interrupt Disabled,1: PRNG interrupt Enabled"
|
|
bitfld.long 0x00 9. "TDESEIEN,TDES/DES Error Flag Enable Bit" "0: TDES/DES error interrupt flag Disabled,1: TDES/DES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIEN,TDES/DES Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine" "0: TDES/DES interrupt Disabled,1: TDES/DES interrupt Enabled"
|
|
bitfld.long 0x00 1. "AESEIEN,AES Error Flag Enable Bit" "0: AES error interrupt flag Disabled,1: AES error interrupt flag Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIEN,AES Interrupt Enable Bit\nNote: In DMA mode an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine" "0: AES interrupt Disabled,1: AES interrupt Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_INTSTS,Crypto Interrupt Flag"
|
|
bitfld.long 0x00 25. "SHAEIF,SHA Error Flag\nThis register includes operating and setting error" "0: No SHA error,1: SHA error interrupt"
|
|
bitfld.long 0x00 24. "SHAIF,SHA Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No SHA interrupt,1: SHA operation done interrupt"
|
|
newline
|
|
bitfld.long 0x00 23. "ECCEIF,ECC Error Flag\nThis register includes operating and setting error" "0: No ECC error,1: ECC error interrupt"
|
|
bitfld.long 0x00 22. "ECCIF,ECC Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No ECC interrupt,1: ECC operation done interrupt"
|
|
newline
|
|
bitfld.long 0x00 16. "PRNGIF,PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No PRNG interrupt,1: PRNG key generation done interrupt"
|
|
bitfld.long 0x00 9. "TDESEIF,TDES/DES Error Flag\nThis bit includes the operating and setting error" "0: No TDES/DES error,1: TDES/DES encryption/decryption error interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "TDESIF,TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No TDES/DES interrupt,1: TDES/DES encryption/decryption done interrupt"
|
|
bitfld.long 0x00 1. "AESEIF,AES Error Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No AES error,1: AES encryption/decryption error interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "AESIF,AES Finish Interrupt Flag\nThis bit is cleared by writing 1 and it has no effect by writing 0" "0: No AES interrupt,1: AES encryption/decryption done interrupt"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_CTL,PRNG Control Register"
|
|
rbitfld.long 0x00 8. "BUSY,PRNG Busy (Read Only)" "0: PRNG engine is idle,1: Indicate that the PRNG engine is generating.."
|
|
bitfld.long 0x00 2.--3. "KEYSZ,PRNG Generate Key Size" "0: 64 bits,1: 128 bits,2: 192 bits,3: 256 bits"
|
|
newline
|
|
bitfld.long 0x00 1. "SEEDRLD,Reload New Seed for PRNG Engine" "0: Generating key based on the current seed,1: Reload new seed"
|
|
bitfld.long 0x00 0. "START,Start PRNG Engine" "0: Stop PRNG engine,1: Generate new key and store the new key to.."
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_SEED,Seed for PRNG"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY0,PRNG Generated Key0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY1,PRNG Generated Key1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY2,PRNG Generated Key2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY3,PRNG Generated Key3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY4,PRNG Generated Key4"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY5,PRNG Generated Key5"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY6,PRNG Generated Key6"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_PRNG_KEY7,PRNG Generated Key7"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK0,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK1,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK2,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_AES_FDBCK3,AES Engine Output Feedback Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for.."
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_TDES_FDBCKH,TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH CRYPTO_TDESn_IVL} for the next block in DMA cascade mode"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_TDES_FDBCKL,TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation"
|
|
hexmask.long 0x00 0.--31. 1. "FDBCK,TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH CRYPTO_TDESn_IVL} for the next block in DMA cascade mode"
|
|
tree.end
|
|
tree "ECC"
|
|
base ad:0x40032800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_ECC_CTL,ECC Control Register"
|
|
hexmask.long.word 0x00 22.--31. 1. "CURVEM,The key length of elliptic curve"
|
|
bitfld.long 0x00 21. "LDK,The Control Signal of Register for SCALARK" "0: The register for SCALARK is not modified by..,1: The register for SCALARK is modified by DMA.."
|
|
newline
|
|
bitfld.long 0x00 20. "LDN,The Control Signal of Register for the Parameter CURVEN of Elliptic Curve" "0: The register for CURVEN is not modified by..,1: The register for CURVEN is modified by DMA or.."
|
|
bitfld.long 0x00 19. "LDB,The Control Signal of Register for the Parameter CURVEB of Elliptic Curve" "0: The register for CURVEB is not modified by..,1: The register for CURVEB is modified by DMA or.."
|
|
newline
|
|
bitfld.long 0x00 18. "LDA,The Control Signal of Register for the Parameter CURVEA of Elliptic Curve" "0: The register for CURVEA is not modified by..,1: The register for CURVEA is modified by DMA or.."
|
|
bitfld.long 0x00 17. "LDP2,The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2 POINTY2)" "0: The register for POINTX2 and POINTY2 is not..,1: The register for POINTX2 and POINTY2 is.."
|
|
newline
|
|
bitfld.long 0x00 16. "LDP1,The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1 POINTY1)" "0: The register for POINTX1 and POINTY1 is not..,1: The register for POINTX1 and POINTY1 is.."
|
|
bitfld.long 0x00 11.--12. "MODOP,Modulus Operation for PF" "0: Division,1: Multiplication,2: Addition,3: Subtraction"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "ECCOP,Point Operation for BF and PF\nBesides above three input data point operations still need the parameters of elliptic curve (CURVEA CURVEB CURVEN and CURVEM) as shown in Figure 6.27-11" "0: Point multiplication,1: Modulus operation,2: Point addition,3: Point doubling"
|
|
bitfld.long 0x00 8. "FSEL,Field Selection" "0: Binary Field (GF(2m )),1: Prime Field (GF(p))"
|
|
newline
|
|
bitfld.long 0x00 7. "DMAEN,ECC Accelerator DMA Enable Bit\nOnly when START and DMAEN are 1 ECC DMA engine will be active" "0: ECC DMA engine Disabled,1: ECC DMA engine Enabled"
|
|
bitfld.long 0x00 1. "STOP,ECC Accelerator Stop\nThis bit is always 0 when it's read back.\nRemember to clear ECC interrupt flag after stopping ECC accelerator" "0: No effect,1: Abort ECC accelerator and make it into idle.."
|
|
newline
|
|
bitfld.long 0x00 0. "START,ECC Accelerator Start\nThis bit is always 0 when it's read back.\nECC accelerator will ignore this START signal when BUSY flag is 1" "0: No effect,1: Start ECC accelerator"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_ECC_STS,ECC Status Register"
|
|
bitfld.long 0x00 16. "BUSERR,ECC DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and ECC.."
|
|
bitfld.long 0x00 1. "DMABUSY,ECC DMA Busy Flag" "0: ECC DMA is idle or finished,1: ECC DMA is busy"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,ECC Accelerator Busy Flag\nRemember to clear ECC interrupt flag after ECC accelerator finished" "0: The ECC accelerator is idle or finished,1: The ECC accelerator is under processing and.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_00,ECC the X-coordinate Word0 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_01,ECC the X-coordinate Word1 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_02,ECC the X-coordinate Word2 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_03,ECC the X-coordinate Word3 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_04,ECC the X-coordinate Word4 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_05,ECC the X-coordinate Word5 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_06,ECC the X-coordinate Word6 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_07,ECC the X-coordinate Word7 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_08,ECC the X-coordinate Word8 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_09,ECC the X-coordinate Word9 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_10,ECC the X-coordinate Word10 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_11,ECC the X-coordinate Word11 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_12,ECC the X-coordinate Word12 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_13,ECC the X-coordinate Word13 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_14,ECC the X-coordinate Word14 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_15,ECC the X-coordinate Word15 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_16,ECC the X-coordinate Word16 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_17,ECC the X-coordinate Word17 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_00,ECC the Y-coordinate Word0 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_01,ECC the Y-coordinate Word1 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_02,ECC the Y-coordinate Word2 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_03,ECC the Y-coordinate Word3 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_04,ECC the Y-coordinate Word4 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_05,ECC the Y-coordinate Word5 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_06,ECC the Y-coordinate Word6 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_07,ECC the Y-coordinate Word7 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_08,ECC the Y-coordinate Word8 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_09,ECC the Y-coordinate Word9 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_10,ECC the Y-coordinate Word10 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_11,ECC the Y-coordinate Word11 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_12,ECC the Y-coordinate Word12 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_13,ECC the Y-coordinate Word13 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_14,ECC the Y-coordinate Word14 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_15,ECC the Y-coordinate Word15 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_16,ECC the Y-coordinate Word16 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_17,ECC the Y-coordinate Word17 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_00,ECC the X-coordinate Word0 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_01,ECC the X-coordinate Word1 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_02,ECC the X-coordinate Word2 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_03,ECC the X-coordinate Word3 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_04,ECC the X-coordinate Word4 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_05,ECC the X-coordinate Word5 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_06,ECC the X-coordinate Word6 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_07,ECC the X-coordinate Word7 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_08,ECC the X-coordinate Word8 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_09,ECC the X-coordinate Word9 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_10,ECC the X-coordinate Word10 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_11,ECC the X-coordinate Word11 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_12,ECC the X-coordinate Word12 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_13,ECC the X-coordinate Word13 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_14,ECC the X-coordinate Word14 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_15,ECC the X-coordinate Word15 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_16,ECC the X-coordinate Word16 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_17,ECC the X-coordinate Word17 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_00,ECC the Y-coordinate Word0 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_01,ECC the Y-coordinate Word1 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_02,ECC the Y-coordinate Word2 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_03,ECC the Y-coordinate Word3 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_04,ECC the Y-coordinate Word4 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_05,ECC the Y-coordinate Word5 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_08,ECC the Y-coordinate Word8 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_09,ECC the Y-coordinate Word9 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_10,ECC the Y-coordinate Word10 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_11,ECC the Y-coordinate Word11 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_12,ECC the Y-coordinate Word12 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_13,ECC the Y-coordinate Word13 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_14,ECC the Y-coordinate Word14 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_15,ECC the Y-coordinate Word15 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_16,ECC the Y-coordinate Word16 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_17,ECC the Y-coordinate Word17 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_00,ECC the Parameter CURVEA Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_01,ECC the Parameter CURVEA Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_02,ECC the Parameter CURVEA Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_03,ECC the Parameter CURVEA Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_04,ECC the Parameter CURVEA Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_05,ECC the Parameter CURVEA Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_06,ECC the Parameter CURVEA Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_07,ECC the Parameter CURVEA Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_08,ECC the Parameter CURVEA Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_09,ECC the Parameter CURVEA Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_10,ECC the Parameter CURVEA Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_11,ECC the Parameter CURVEA Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_12,ECC the Parameter CURVEA Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_13,ECC the Parameter CURVEA Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_14,ECC the Parameter CURVEA Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_15,ECC the Parameter CURVEA Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_16,ECC the Parameter CURVEA Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_17,ECC the Parameter CURVEA Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_00,ECC the Parameter CURVEB Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_01,ECC the Parameter CURVEB Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_02,ECC the Parameter CURVEB Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_03,ECC the Parameter CURVEB Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_04,ECC the Parameter CURVEB Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_05,ECC the Parameter CURVEB Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_06,ECC the Parameter CURVEB Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_07,ECC the Parameter CURVEB Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_08,ECC the Parameter CURVEB Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_09,ECC the Parameter CURVEB Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_10,ECC the Parameter CURVEB Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_11,ECC the Parameter CURVEB Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_12,ECC the Parameter CURVEB Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_13,ECC the Parameter CURVEB Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_14,ECC the Parameter CURVEB Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_15,ECC the Parameter CURVEB Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_16,ECC the Parameter CURVEB Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_17,ECC the Parameter CURVEB Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_00,ECC the Parameter CURVEN Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_01,ECC the Parameter CURVEN Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_02,ECC the Parameter CURVEN Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_03,ECC the Parameter CURVEN Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_04,ECC the Parameter CURVEN Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_05,ECC the Parameter CURVEN Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_06,ECC the Parameter CURVEN Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_07,ECC the Parameter CURVEN Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_08,ECC the Parameter CURVEN Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_09,ECC the Parameter CURVEN Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_10,ECC the Parameter CURVEN Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_11,ECC the Parameter CURVEN Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_12,ECC the Parameter CURVEN Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_13,ECC the Parameter CURVEN Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_14,ECC the Parameter CURVEN Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_15,ECC the Parameter CURVEN Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_16,ECC the Parameter CURVEN Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_17,ECC the Parameter CURVEN Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
wgroup.long 0x200++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_00,ECC the Scalar SCALARK Word0 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_01,ECC the Scalar SCALARK Word1 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_02,ECC the Scalar SCALARK Word2 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_03,ECC the Scalar SCALARK Word3 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_04,ECC the Scalar SCALARK Word4 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_05,ECC the Scalar SCALARK Word5 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_06,ECC the Scalar SCALARK Word6 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_07,ECC the Scalar SCALARK Word7 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_08,ECC the Scalar SCALARK Word8 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_09,ECC the Scalar SCALARK Word9 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_10,ECC the Scalar SCALARK Word10 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_11,ECC the Scalar SCALARK Word11 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_12,ECC the Scalar SCALARK Word12 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_13,ECC the Scalar SCALARK Word13 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_14,ECC the Scalar SCALARK Word14 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_15,ECC the Scalar SCALARK Word15 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_16,ECC the Scalar SCALARK Word16 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_17,ECC the Scalar SCALARK Word17 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CRYPTO_ECC_SADDR,ECC DMA Source Address Register"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_DADDR,ECC DMA Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,ECC DMA Destination Address \nThe ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CRYPTO_ECC_STARTREG,ECC Starting Address of Updated Registers"
|
|
hexmask.long 0x00 0.--31. 1. "STARTREG,ECC Starting Address of Updated Registers\nThe address of the updated registers that DMA feeds the first data or parameter to ECC engine"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CRYPTO_ECC_WORDCNT,ECC DMA Word Count"
|
|
hexmask.long 0x00 0.--31. 1. "WORDCNT,ECC DMA Word Count \nThe CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode"
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_06,ECC the Y-coordinate Word6 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_07,ECC the Y-coordinate Word7 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
tree.end
|
|
tree "ECC_NS"
|
|
base ad:0x50032800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_ECC_CTL,ECC Control Register"
|
|
hexmask.long.word 0x00 22.--31. 1. "CURVEM,The key length of elliptic curve"
|
|
bitfld.long 0x00 21. "LDK,The Control Signal of Register for SCALARK" "0: The register for SCALARK is not modified by..,1: The register for SCALARK is modified by DMA.."
|
|
newline
|
|
bitfld.long 0x00 20. "LDN,The Control Signal of Register for the Parameter CURVEN of Elliptic Curve" "0: The register for CURVEN is not modified by..,1: The register for CURVEN is modified by DMA or.."
|
|
bitfld.long 0x00 19. "LDB,The Control Signal of Register for the Parameter CURVEB of Elliptic Curve" "0: The register for CURVEB is not modified by..,1: The register for CURVEB is modified by DMA or.."
|
|
newline
|
|
bitfld.long 0x00 18. "LDA,The Control Signal of Register for the Parameter CURVEA of Elliptic Curve" "0: The register for CURVEA is not modified by..,1: The register for CURVEA is modified by DMA or.."
|
|
bitfld.long 0x00 17. "LDP2,The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2 POINTY2)" "0: The register for POINTX2 and POINTY2 is not..,1: The register for POINTX2 and POINTY2 is.."
|
|
newline
|
|
bitfld.long 0x00 16. "LDP1,The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1 POINTY1)" "0: The register for POINTX1 and POINTY1 is not..,1: The register for POINTX1 and POINTY1 is.."
|
|
bitfld.long 0x00 11.--12. "MODOP,Modulus Operation for PF" "0: Division,1: Multiplication,2: Addition,3: Subtraction"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "ECCOP,Point Operation for BF and PF\nBesides above three input data point operations still need the parameters of elliptic curve (CURVEA CURVEB CURVEN and CURVEM) as shown in Figure 6.27-11" "0: Point multiplication,1: Modulus operation,2: Point addition,3: Point doubling"
|
|
bitfld.long 0x00 8. "FSEL,Field Selection" "0: Binary Field (GF(2m )),1: Prime Field (GF(p))"
|
|
newline
|
|
bitfld.long 0x00 7. "DMAEN,ECC Accelerator DMA Enable Bit\nOnly when START and DMAEN are 1 ECC DMA engine will be active" "0: ECC DMA engine Disabled,1: ECC DMA engine Enabled"
|
|
bitfld.long 0x00 1. "STOP,ECC Accelerator Stop\nThis bit is always 0 when it's read back.\nRemember to clear ECC interrupt flag after stopping ECC accelerator" "0: No effect,1: Abort ECC accelerator and make it into idle.."
|
|
newline
|
|
bitfld.long 0x00 0. "START,ECC Accelerator Start\nThis bit is always 0 when it's read back.\nECC accelerator will ignore this START signal when BUSY flag is 1" "0: No effect,1: Start ECC accelerator"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_ECC_STS,ECC Status Register"
|
|
bitfld.long 0x00 16. "BUSERR,ECC DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and ECC.."
|
|
bitfld.long 0x00 1. "DMABUSY,ECC DMA Busy Flag" "0: ECC DMA is idle or finished,1: ECC DMA is busy"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSY,ECC Accelerator Busy Flag\nRemember to clear ECC interrupt flag after ECC accelerator finished" "0: The ECC accelerator is idle or finished,1: The ECC accelerator is under processing and.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_00,ECC the X-coordinate Word0 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_01,ECC the X-coordinate Word1 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_02,ECC the X-coordinate Word2 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_03,ECC the X-coordinate Word3 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_04,ECC the X-coordinate Word4 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_05,ECC the X-coordinate Word5 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_06,ECC the X-coordinate Word6 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_07,ECC the X-coordinate Word7 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_08,ECC the X-coordinate Word8 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_09,ECC the X-coordinate Word9 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_10,ECC the X-coordinate Word10 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_11,ECC the X-coordinate Word11 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_12,ECC the X-coordinate Word12 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_13,ECC the X-coordinate Word13 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_14,ECC the X-coordinate Word14 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_15,ECC the X-coordinate Word15 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_16,ECC the X-coordinate Word16 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X1_17,ECC the X-coordinate Word17 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX1,ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233 POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283 POINTX1 is stored.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_00,ECC the Y-coordinate Word0 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_01,ECC the Y-coordinate Word1 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_02,ECC the Y-coordinate Word2 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_03,ECC the Y-coordinate Word3 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_04,ECC the Y-coordinate Word4 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_05,ECC the Y-coordinate Word5 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_06,ECC the Y-coordinate Word6 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_07,ECC the Y-coordinate Word7 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_08,ECC the Y-coordinate Word8 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_09,ECC the Y-coordinate Word9 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_10,ECC the Y-coordinate Word10 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_11,ECC the Y-coordinate Word11 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_12,ECC the Y-coordinate Word12 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_13,ECC the Y-coordinate Word13 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_14,ECC the Y-coordinate Word14 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_15,ECC the Y-coordinate Word15 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_16,ECC the Y-coordinate Word16 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y1_17,ECC the Y-coordinate Word17 of the First Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY1,ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233 POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283 POINTY1 is stored.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_00,ECC the X-coordinate Word0 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_01,ECC the X-coordinate Word1 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_02,ECC the X-coordinate Word2 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_03,ECC the X-coordinate Word3 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_04,ECC the X-coordinate Word4 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_05,ECC the X-coordinate Word5 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_06,ECC the X-coordinate Word6 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_07,ECC the X-coordinate Word7 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_08,ECC the X-coordinate Word8 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_09,ECC the X-coordinate Word9 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_10,ECC the X-coordinate Word10 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_11,ECC the X-coordinate Word11 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_12,ECC the X-coordinate Word12 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_13,ECC the X-coordinate Word13 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_14,ECC the X-coordinate Word14 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_15,ECC the X-coordinate Word15 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_16,ECC the X-coordinate Word16 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_X2_17,ECC the X-coordinate Word17 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTX2,ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233 POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283 POINTX2 is stored.."
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_00,ECC the Y-coordinate Word0 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_01,ECC the Y-coordinate Word1 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_02,ECC the Y-coordinate Word2 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_03,ECC the Y-coordinate Word3 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_04,ECC the Y-coordinate Word4 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_05,ECC the Y-coordinate Word5 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_08,ECC the Y-coordinate Word8 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_09,ECC the Y-coordinate Word9 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_10,ECC the Y-coordinate Word10 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_11,ECC the Y-coordinate Word11 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_12,ECC the Y-coordinate Word12 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_13,ECC the Y-coordinate Word13 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_14,ECC the Y-coordinate Word14 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_15,ECC the Y-coordinate Word15 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_16,ECC the Y-coordinate Word16 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_17,ECC the Y-coordinate Word17 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_00,ECC the Parameter CURVEA Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_01,ECC the Parameter CURVEA Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_02,ECC the Parameter CURVEA Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_03,ECC the Parameter CURVEA Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_04,ECC the Parameter CURVEA Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_05,ECC the Parameter CURVEA Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_06,ECC the Parameter CURVEA Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_07,ECC the Parameter CURVEA Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_08,ECC the Parameter CURVEA Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_09,ECC the Parameter CURVEA Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_10,ECC the Parameter CURVEA Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_11,ECC the Parameter CURVEA Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_12,ECC the Parameter CURVEA Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_13,ECC the Parameter CURVEA Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_14,ECC the Parameter CURVEA Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_15,ECC the Parameter CURVEA Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_16,ECC the Parameter CURVEA Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_A_17,ECC the Parameter CURVEA Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEA,ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233 CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283 CURVEA is stored in.."
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_00,ECC the Parameter CURVEB Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_01,ECC the Parameter CURVEB Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_02,ECC the Parameter CURVEB Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_03,ECC the Parameter CURVEB Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_04,ECC the Parameter CURVEB Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_05,ECC the Parameter CURVEB Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_06,ECC the Parameter CURVEB Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_07,ECC the Parameter CURVEB Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_08,ECC the Parameter CURVEB Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_09,ECC the Parameter CURVEB Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_10,ECC the Parameter CURVEB Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_11,ECC the Parameter CURVEB Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_12,ECC the Parameter CURVEB Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_13,ECC the Parameter CURVEB Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_14,ECC the Parameter CURVEB Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_15,ECC the Parameter CURVEB Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_16,ECC the Parameter CURVEB Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_B_17,ECC the Parameter CURVEB Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEB,ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233 CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283 CURVEB is stored in.."
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_00,ECC the Parameter CURVEN Word0 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_01,ECC the Parameter CURVEN Word1 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_02,ECC the Parameter CURVEN Word2 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_03,ECC the Parameter CURVEN Word3 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_04,ECC the Parameter CURVEN Word4 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_05,ECC the Parameter CURVEN Word5 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_06,ECC the Parameter CURVEN Word6 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_07,ECC the Parameter CURVEN Word7 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_08,ECC the Parameter CURVEN Word8 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_09,ECC the Parameter CURVEN Word9 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_10,ECC the Parameter CURVEN Word10 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_11,ECC the Parameter CURVEN Word11 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_12,ECC the Parameter CURVEN Word12 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_13,ECC the Parameter CURVEN Word13 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_14,ECC the Parameter CURVEN Word14 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_15,ECC the Parameter CURVEN Word15 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_16,ECC the Parameter CURVEN Word16 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
group.long 0x1FC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_N_17,ECC the Parameter CURVEN Word17 of Elliptic Curve"
|
|
hexmask.long 0x00 0.--31. 1. "CURVEN,ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p) CURVEN is the prime p.\nIn GF(2m) CURVEN is the irreducible polynomial.\nFor B-163 or K-163 CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233 CURVEN is.."
|
|
wgroup.long 0x200++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_00,ECC the Scalar SCALARK Word0 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_01,ECC the Scalar SCALARK Word1 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_02,ECC the Scalar SCALARK Word2 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_03,ECC the Scalar SCALARK Word3 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_04,ECC the Scalar SCALARK Word4 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_05,ECC the Scalar SCALARK Word5 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_06,ECC the Scalar SCALARK Word6 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_07,ECC the Scalar SCALARK Word7 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_08,ECC the Scalar SCALARK Word8 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_09,ECC the Scalar SCALARK Word9 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_10,ECC the Scalar SCALARK Word10 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_11,ECC the Scalar SCALARK Word11 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_12,ECC the Scalar SCALARK Word12 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_13,ECC the Scalar SCALARK Word13 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_14,ECC the Scalar SCALARK Word14 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_15,ECC the Scalar SCALARK Word15 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_16,ECC the Scalar SCALARK Word16 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CRYPTO_ECC_K_17,ECC the Scalar SCALARK Word17 of Point Multiplication"
|
|
hexmask.long 0x00 0.--31. 1. "SCALARK,ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163 SCALARK is stored in.."
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CRYPTO_ECC_SADDR,ECC DMA Source Address Register"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CRYPTO_ECC_DADDR,ECC DMA Destination Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,ECC DMA Destination Address \nThe ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CRYPTO_ECC_STARTREG,ECC Starting Address of Updated Registers"
|
|
hexmask.long 0x00 0.--31. 1. "STARTREG,ECC Starting Address of Updated Registers\nThe address of the updated registers that DMA feeds the first data or parameter to ECC engine"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CRYPTO_ECC_WORDCNT,ECC DMA Word Count"
|
|
hexmask.long 0x00 0.--31. 1. "WORDCNT,ECC DMA Word Count \nThe CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode"
|
|
group.long 0x8F8++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_06,ECC the Y-coordinate Word6 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
group.long 0x8FC++0x03
|
|
line.long 0x00 "CRYPTO_ECC_Y2_07,ECC the Y-coordinate Word7 of the Second Point"
|
|
hexmask.long 0x00 0.--31. 1. "POINTY2,ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233 POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283 POINTY2 is stored.."
|
|
tree.end
|
|
tree "SHA"
|
|
base ad:0x40032300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_SHA_CTL,SHA Control Register"
|
|
bitfld.long 0x00 23. "INSWAP,SHA Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
bitfld.long 0x00 22. "OUTSWAP,SHA Engine Output Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "OPMODE,SHA Engine Operation Modes\n0x0xx: SHA160\n0x100: SHA256\n0x101: SHA224\n0x110: reservedReserved.\n0x111: SHA384" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "DMAEN,SHA Engine DMA Enable Bit\nSHA engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: SHA DMA engine Disabled,1: SHA DMA engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DMALAST,SHA Last Block\nThis bit must be set as feeding in last byte of data" "0,1"
|
|
bitfld.long 0x00 1. "STOP,SHA Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop SHA/SHA engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,SHA Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start SHA/SHA engine"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_SHA_STS,SHA Status Flag"
|
|
bitfld.long 0x00 16. "DATINREQ,SHA Non-dMA Mode Data Input Request" "0: No effect,1: Request SHA/SHA Non-DMA mode data input"
|
|
bitfld.long 0x00 8. "DMAERR,SHA Engine DMA Error Flag" "0: Show the SHA/SHA engine access normal,1: Show the SHA/SHA engine access error"
|
|
newline
|
|
bitfld.long 0x00 1. "DMABUSY,SHA Engine DMA Busy Flag" "0: SHA/SHA DMA engine is idle or finished,1: SHA/SHA DMA engine is busy"
|
|
bitfld.long 0x00 0. "BUSY,SHA Engine Busy" "0: SHA/SHA engine is idle or finished,1: SHA/SHA engine is busy"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST0,SHA Digest Message 0"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST1,SHA Digest Message 1"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST2,SHA Digest Message 2"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST3,SHA Digest Message 3"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST4,SHA Digest Message 4"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST5,SHA Digest Message 5"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST6,SHA Digest Message 6"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST7,SHA Digest Message 7"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST8,SHA Digest Message 8"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST9,SHA Digest Message 9"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST10,SHA Digest Message 10"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST11,SHA Digest Message 11"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_SHA_KEYCNT,SHA Key Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEYCNT,SHA Key Byte Count\nThe CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA/SHA engine operates"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_SADDR,SHA DMA Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DMACNT,SHA Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMACNT,SHA Operation Byte Count\nThe CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DATIN,SHA Engine Non-dMA Mode Data Input Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS"
|
|
tree.end
|
|
tree "SHA_NS"
|
|
base ad:0x50032300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_SHA_CTL,SHA Control Register"
|
|
bitfld.long 0x00 23. "INSWAP,SHA Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
bitfld.long 0x00 22. "OUTSWAP,SHA Engine Output Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "OPMODE,SHA Engine Operation Modes\n0x0xx: SHA160\n0x100: SHA256\n0x101: SHA224\n0x110: reserved\n0x111: SHA384" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "DMAEN,SHA Engine DMA Enable Bit\nSHA engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: SHA DMA engine Disabled,1: SHA DMA engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DMALAST,SHA Last Block\nThis bit must be set as feeding in last byte of data" "0,1"
|
|
bitfld.long 0x00 1. "STOP,SHA Engine Stop\nNote: This bit is always 0 when it's read back" "0: No effect,1: Stop SHA/SHA engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,SHA Engine Start\nNote: This bit is always 0 when it's read back" "0: No effect,1: Start SHA/SHA engine"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_SHA_STS,SHA Status Flag"
|
|
bitfld.long 0x00 16. "DATINREQ,SHA Non-dMA Mode Data Input Request" "0: No effect,1: Request SHA/SHA Non-DMA mode data input"
|
|
bitfld.long 0x00 8. "DMAERR,SHA Engine DMA Error Flag" "0: Show the SHA/SHA engine access normal,1: Show the SHA/SHA engine access error"
|
|
newline
|
|
bitfld.long 0x00 1. "DMABUSY,SHA Engine DMA Busy Flag" "0: SHA/SHA DMA engine is idle or finished,1: SHA/SHA DMA engine is busy"
|
|
bitfld.long 0x00 0. "BUSY,SHA Engine Busy" "0: SHA/SHA engine is idle or finished,1: SHA/SHA engine is busy"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST0,SHA Digest Message 0"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST1,SHA Digest Message 1"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST2,SHA Digest Message 2"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST3,SHA Digest Message 3"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST4,SHA Digest Message 4"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST5,SHA Digest Message 5"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST6,SHA Digest Message 6"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST7,SHA Digest Message 7"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST8,SHA Digest Message 8"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST9,SHA Digest Message 9"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST10,SHA Digest Message 10"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DGST11,SHA Digest Message 11"
|
|
hexmask.long 0x00 0.--31. 1. "DGST,SHA Digest Message Output Register\nFor SHA-160 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224 the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256 the digest is stored in CRYPTO_SHA_DGST0 ~.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_SHA_KEYCNT,SHA Key Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEYCNT,SHA Key Byte Count\nThe CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA/SHA engine operates"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_SHA_SADDR,SHA DMA Source Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DMACNT,SHA Byte Count Register"
|
|
hexmask.long 0x00 0.--31. 1. "DMACNT,SHA Operation Byte Count\nThe CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_SHA_DATIN,SHA Engine Non-dMA Mode Data Input Port Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS"
|
|
tree.end
|
|
tree "TDES"
|
|
base ad:0x40032200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_TDES_CTL,TDES/DES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT" "0: No effect,1: This bit is to protect the content of TDES.."
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_TDES_CTL [31] and '10110' to CRYPTO_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CHANNEL,TDES/DES Engine Working Channel" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
|
|
bitfld.long 0x00 23. "INSWAP,TDES/DES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 22. "OUTSWAP,TDES/DES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU outputs data from the.."
|
|
bitfld.long 0x00 21. "BLKSWAP,TDES/DES Engine Block Double Word Endian Swap" "0: Keep the original order e.g,1: When this bit is set to 1 the TDES engine.."
|
|
newline
|
|
bitfld.long 0x00 16. "ENCRYPTO,TDES/DES Encryption/Decryption" "0: TDES engine executes decryption operation,1: TDES engine executes encryption operation"
|
|
bitfld.long 0x00 8.--10. "OPMODE,TDES/DES Engine Operation Mode" "0: ECB (Electronic Codebook Mode),1: CBC (Cipher Block Chaining Mode),2: CFB (Cipher Feedback Mode),3: OFB (Output Feedback Mode),4: CTR (Counter Mode),?..."
|
|
newline
|
|
bitfld.long 0x00 7. "DMAEN,TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: TDES_DMA engine Disabled,1: TDES_DMA engine Enabled"
|
|
bitfld.long 0x00 6. "DMACSCAD,TDES/DES Engine DMA with Cascade Mode" "0: DMA cascade function Disabled,1: In DMA Cascade mode software can update DMA.."
|
|
newline
|
|
bitfld.long 0x00 5. "DMALAST,TDES/DES Engine Start for the Last Block \nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set as feeding in last block of data" "0,1"
|
|
bitfld.long 0x00 3. "_3KEYS,TDES/DES Key Number" "0: Select KEY1 and KEY2 in TDES/DES engine,1: Triple keys in TDES/DES engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TMODE,TDES/DES Engine Operating Mode" "0: Set DES mode for TDES/DES engine,1: Set Triple DES mode for TDES/DES engine"
|
|
bitfld.long 0x00 1. "STOP,TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back" "0: No effect,1: Stop TDES/DES engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,TDES/DES Engine Start\nNote: The bit is always 0 when it's read back" "0: No effect,1: Start TDES/DES engine"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_TDES_STS,TDES/DES Engine Flag"
|
|
bitfld.long 0x00 20. "BUSERR,TDES/DES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and.."
|
|
bitfld.long 0x00 18. "OUTBUFERR,TDES/DES Out Buffer Error Flag" "0: No error,1: Error happens during getting test result from.."
|
|
newline
|
|
bitfld.long 0x00 17. "OUTBUFFULL,TDES/DES Output Buffer Full Flag" "0: TDES/DES output buffer is not full,1: TDES/DES output buffer is full and software.."
|
|
bitfld.long 0x00 16. "OUTBUFEMPTY,TDES/DES Output Buffer Empty Flag" "0: TDES/DES output buffer is not empty,1: TDES/DES output buffer is empty Software.."
|
|
newline
|
|
bitfld.long 0x00 10. "INBUFERR,TDES/DES in Buffer Error Flag" "0: No error,1: Error happens during feeding data to the.."
|
|
bitfld.long 0x00 9. "INBUFFULL,TDES/DES in Buffer Full Flag" "0: TDES/DES input buffer is not full,1: TDES input buffer is full"
|
|
newline
|
|
bitfld.long 0x00 8. "INBUFEMPTY,TDES/DES in Buffer Empty" "0: There are some data in input buffer waiting..,1: TDES/DES input buffer is empty"
|
|
bitfld.long 0x00 0. "BUSY,TDES/DES Engine Busy" "0: TDES/DES engine is idle or finished,1: TDES/DES engine is under processing"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY1H,TDES/DES Key 1 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY1L,TDES/DES Key 1 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY2H,TDES Key 2 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY2L,TDES Key 2 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY3H,TDES Key 3 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY3L,TDES Key 3 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_IVH,TDES/DES Initial Vector High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_IVL,TDES/DES Initial Vector Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_SADDR,TDES/DES DMA Source Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_DADDR,TDES/DES DMA Destination Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_CNT,TDES/DES Byte Count Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_TDES_DATIN,TDES/DES Engine Input Data Word Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRYPTO_TDES_STS"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CRYPTO_TDES_DATOUT,TDES/DES Engine Output Data Word Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATOUT,TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRYPTO_TDES_STS"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY1H,TDES/DES Key 1 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY1L,TDES/DES Key 1 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY2H,TDES Key 2 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY2L,TDES Key 2 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY3H,TDES Key 3 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY3L,TDES Key 3 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_IVH,TDES/DES Initial Vector High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_IVL,TDES/DES Initial Vector Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_SADDR,TDES/DES DMA Source Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_DADDR,TDES/DES DMA Destination Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_CNT,TDES/DES Byte Count Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY1H,TDES/DES Key 1 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY1L,TDES/DES Key 1 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY2H,TDES Key 2 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY2L,TDES Key 2 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY3H,TDES Key 3 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY3L,TDES Key 3 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_IVH,TDES/DES Initial Vector High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_IVL,TDES/DES Initial Vector Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_SADDR,TDES/DES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_DADDR,TDES/DES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_CNT,TDES/DES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY1H,TDES/DES Key 1 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY1L,TDES/DES Key 1 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY2H,TDES Key 2 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY2L,TDES Key 2 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY3H,TDES Key 3 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY3L,TDES Key 3 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_IVH,TDES/DES Initial Vector High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_IVL,TDES/DES Initial Vector Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_SADDR,TDES/DES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_DADDR,TDES/DES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_CNT,TDES/DES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
tree.end
|
|
tree "TDES_NS"
|
|
base ad:0x50032200
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRYPTO_TDES_CTL,TDES/DES Control Register"
|
|
bitfld.long 0x00 31. "KEYPRT,Protect Key\nRead as a flag to reflect KEYPRT" "0: No effect,1: This bit is to protect the content of TDES.."
|
|
bitfld.long 0x00 26.--30. "KEYUNPRT,Unprotect Key\nWriting 0 to CRYPTO_TDES_CTL [31] and '10110' to CRYPTO_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "CHANNEL,TDES/DES Engine Working Channel" "0: Current control register setting is for..,1: Current control register setting is for..,2: Current control register setting is for..,3: Current control register setting is for.."
|
|
bitfld.long 0x00 23. "INSWAP,TDES/DES Engine Input Data Swap" "0: Keep the original order,1: The order that CPU feeds data to the.."
|
|
newline
|
|
bitfld.long 0x00 22. "OUTSWAP,TDES/DES Engine Output Data Swap" "0: Keep the original order,1: The order that CPU outputs data from the.."
|
|
bitfld.long 0x00 21. "BLKSWAP,TDES/DES Engine Block Double Word Endian Swap" "0: Keep the original order e.g,1: When this bit is set to 1 the TDES engine.."
|
|
newline
|
|
bitfld.long 0x00 16. "ENCRYPTO,TDES/DES Encryption/Decryption" "0: TDES engine executes decryption operation,1: TDES engine executes encryption operation"
|
|
bitfld.long 0x00 8.--10. "OPMODE,TDES/DES Engine Operation Mode" "0: ECB (Electronic Codebook Mode),1: CBC (Cipher Block Chaining Mode),2: CFB (Cipher Feedback Mode),3: OFB (Output Feedback Mode),4: CTR (Counter Mode),?..."
|
|
newline
|
|
bitfld.long 0x00 7. "DMAEN,TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode and data movement from/to the engine is done by DMA logic" "0: TDES_DMA engine Disabled,1: TDES_DMA engine Enabled"
|
|
bitfld.long 0x00 6. "DMACSCAD,TDES/DES Engine DMA with Cascade Mode" "0: DMA cascade function Disabled,1: In DMA Cascade mode software can update DMA.."
|
|
newline
|
|
bitfld.long 0x00 5. "DMALAST,TDES/DES Engine Start for the Last Block \nIn DMA mode this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode this bit must be set as feeding in last block of data" "0,1"
|
|
bitfld.long 0x00 3. "_3KEYS,TDES/DES Key Number" "0: Select KEY1 and KEY2 in TDES/DES engine,1: Triple keys in TDES/DES engine Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TMODE,TDES/DES Engine Operating Mode" "0: Set DES mode for TDES/DES engine,1: Set Triple DES mode for TDES/DES engine"
|
|
bitfld.long 0x00 1. "STOP,TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back" "0: No effect,1: Stop TDES/DES engine"
|
|
newline
|
|
bitfld.long 0x00 0. "START,TDES/DES Engine Start\nNote: The bit is always 0 when it's read back" "0: No effect,1: Start TDES/DES engine"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CRYPTO_TDES_STS,TDES/DES Engine Flag"
|
|
bitfld.long 0x00 20. "BUSERR,TDES/DES DMA Access Bus Error Flag" "0: No error,1: Bus error will stop DMA operation and.."
|
|
bitfld.long 0x00 18. "OUTBUFERR,TDES/DES Out Buffer Error Flag" "0: No error,1: Error happens during getting test result from.."
|
|
newline
|
|
bitfld.long 0x00 17. "OUTBUFFULL,TDES/DES Output Buffer Full Flag" "0: TDES/DES output buffer is not full,1: TDES/DES output buffer is full and software.."
|
|
bitfld.long 0x00 16. "OUTBUFEMPTY,TDES/DES Output Buffer Empty Flag" "0: TDES/DES output buffer is not empty,1: TDES/DES output buffer is empty Software.."
|
|
newline
|
|
bitfld.long 0x00 10. "INBUFERR,TDES/DES in Buffer Error Flag" "0: No error,1: Error happens during feeding data to the.."
|
|
bitfld.long 0x00 9. "INBUFFULL,TDES/DES in Buffer Full Flag" "0: TDES/DES input buffer is not full,1: TDES input buffer is full"
|
|
newline
|
|
bitfld.long 0x00 8. "INBUFEMPTY,TDES/DES in Buffer Empty" "0: There are some data in input buffer waiting..,1: TDES/DES input buffer is empty"
|
|
bitfld.long 0x00 0. "BUSY,TDES/DES Engine Busy" "0: TDES/DES engine is idle or finished,1: TDES/DES engine is under processing"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY1H,TDES/DES Key 1 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY1L,TDES/DES Key 1 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY2H,TDES Key 2 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY2L,TDES Key 2 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY3H,TDES Key 3 High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_KEY3L,TDES Key 3 Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_IVH,TDES/DES Initial Vector High Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_IVL,TDES/DES Initial Vector Low Word Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_SADDR,TDES/DES DMA Source Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_DADDR,TDES/DES DMA Destination Address Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CRYPTO_TDES0_CNT,TDES/DES Byte Count Register for Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CRYPTO_TDES_DATIN,TDES/DES Engine Input Data Word Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATIN,TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRYPTO_TDES_STS"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CRYPTO_TDES_DATOUT,TDES/DES Engine Output Data Word Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATOUT,TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRYPTO_TDES_STS"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY1H,TDES/DES Key 1 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY1L,TDES/DES Key 1 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY2H,TDES Key 2 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY2L,TDES Key 2 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY3H,TDES Key 3 High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_KEY3L,TDES Key 3 Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_IVH,TDES/DES Initial Vector High Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_IVL,TDES/DES Initial Vector Low Word Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_SADDR,TDES/DES DMA Source Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_DADDR,TDES/DES DMA Destination Address Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CRYPTO_TDES1_CNT,TDES/DES Byte Count Register for Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY1H,TDES/DES Key 1 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY1L,TDES/DES Key 1 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY2H,TDES Key 2 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY2L,TDES Key 2 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY3H,TDES Key 3 High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_KEY3L,TDES Key 3 Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_IVH,TDES/DES Initial Vector High Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_IVL,TDES/DES Initial Vector Low Word Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_SADDR,TDES/DES DMA Source Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_DADDR,TDES/DES DMA Destination Address Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CRYPTO_TDES2_CNT,TDES/DES Byte Count Register for Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY1H,TDES/DES Key 1 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY1L,TDES/DES Key 1 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY2H,TDES Key 2 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY2L,TDES Key 2 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY3H,TDES Key 3 High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_KEY3L,TDES Key 3 Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_IVH,TDES/DES Initial Vector High Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_IVL,TDES/DES Initial Vector Low Word Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "IV,TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC CFB and OFB mode"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_SADDR,TDES/DES DMA Source Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_DADDR,TDES/DES DMA Destination Address Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "CRYPTO_TDES3_CNT,TDES/DES Byte Count Register for Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode"
|
|
tree.end
|
|
tree.end
|
|
tree "DAC"
|
|
tree "DAC"
|
|
base ad:0x40047000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC0_CTL,DAC0 Control Register"
|
|
bitfld.long 0x00 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC0 and DAC1 are not grouped,1: DAC0 and DAC1 are grouped"
|
|
bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: data is 12 bits,1: data is 8 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger"
|
|
bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Control" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC0_ST trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: EPWM0 trigger,7: EPWM1 trigger"
|
|
newline
|
|
bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DAC0_SWTRG,DAC0 Software Trigger Control Register"
|
|
bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DAC0_DAT,DAC0 Data Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DAC0_DATOUT,DAC0 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAC0_STATUS,DAC0 Status Register"
|
|
rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAC0_TCTL,DAC0 Timing Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DAC1_CTL,DAC1 Control Register"
|
|
bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..."
|
|
bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger"
|
|
newline
|
|
bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Control" "0: Right alignment,1: Left alignment"
|
|
bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
newline
|
|
bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC1_ST trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: EPWM0 trigger,7: EPWM1 trigger"
|
|
bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "DAC1_SWTRG,DAC1 Software Trigger Control Register"
|
|
bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "DAC1_DAT,DAC1 Data Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "DAC1_DATOUT,DAC1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DAC1_STATUS,DAC1 Status Register"
|
|
rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "DAC1_TCTL,DAC1 Timing Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us.."
|
|
tree.end
|
|
tree "DAC_NS"
|
|
base ad:0x50047000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC0_CTL,DAC0 Control Register"
|
|
bitfld.long 0x00 16. "GRPEN,DAC Group Mode Enable Bit" "0: DAC0 and DAC1 are not grouped,1: DAC0 and DAC1 are grouped"
|
|
bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: data is 12 bits,1: data is 8 bits,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger"
|
|
bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Control" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
|
|
bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC0_ST trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: EPWM0 trigger,7: EPWM1 trigger"
|
|
newline
|
|
bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
|
|
bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
|
|
bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DAC0_SWTRG,DAC0 Software Trigger Control Register"
|
|
bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DAC0_DAT,DAC0 Data Holding Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "DAC0_DATOUT,DAC0 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "DAC0_STATUS,DAC0 Status Register"
|
|
rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
|
|
bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
|
|
newline
|
|
bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit is set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "DAC0_TCTL,DAC0 Timing Control Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DAC1_CTL,DAC1 Control Register"
|
|
bitfld.long 0x00 14.--15. "BWSEL,DAC Data Bit-width Selection" "0: Data is 12 bits,1: Data is 8 bits,?..."
|
|
bitfld.long 0x00 12.--13. "ETRGSEL,External Pin Trigger Selection" "0: Low level trigger,1: High level trigger,2: Falling edge trigger,3: Rising edge trigger"
|
|
newline
|
|
bitfld.long 0x00 10. "LALIGN,DAC Data Left-aligned Enabled Control" "0: Right alignment,1: Left alignment"
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bitfld.long 0x00 8. "BYPASS,Bypass Buffer Mode" "0: Output voltage buffer Enabled,1: Output voltage buffer Disabled"
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newline
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bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: External pin DAC1_ST trigger,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: EPWM0 trigger,7: EPWM1 trigger"
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bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled"
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newline
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bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA under-run interrupt Disabled,1: DMA under-run interrupt Enabled"
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bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled"
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|
newline
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bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: DAC interrupt Disabled,1: DAC interrupt Enabled"
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bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled"
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group.long 0x44++0x03
|
|
line.long 0x00 "DAC1_SWTRG,DAC1 Software Trigger Control Register"
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bitfld.long 0x00 0. "SWTRG,Software Trigger\nNote: User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled"
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group.long 0x48++0x03
|
|
line.long 0x00 "DAC1_DAT,DAC1 Data Holding Register"
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|
hexmask.long.word 0x00 0.--15. 1. "DACDAT,DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output"
|
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rgroup.long 0x4C++0x03
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line.long 0x00 "DAC1_DATOUT,DAC1 Data Output Register"
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hexmask.long.word 0x00 0.--11. 1. "DATOUT,DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly"
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group.long 0x50++0x03
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line.long 0x00 "DAC1_STATUS,DAC1 Status Register"
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rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)" "0: DAC is ready for next conversion,1: DAC is busy in conversion"
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bitfld.long 0x00 1. "DMAUDR,DMA Under-run Interrupt Flag\nNote: User writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred"
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|
newline
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bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nNote: This bit set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish"
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group.long 0x54++0x03
|
|
line.long 0x00 "DAC1_TCTL,DAC1 Timing Control Register"
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hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 80MHz and DAC conversion settling time is 1 us.."
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tree.end
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tree.end
|
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tree "EADC"
|
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tree "EADC"
|
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base ad:0x40043000
|
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rgroup.long 0x00++0x03
|
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line.long 0x00 "EADC_DAT0,ADC Data Register 0 for Sample Module 0"
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bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x04++0x03
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line.long 0x00 "EADC_DAT1,ADC Data Register 1 for Sample Module 1"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x08++0x03
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line.long 0x00 "EADC_DAT2,ADC Data Register 2 for Sample Module 2"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x0C++0x03
|
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line.long 0x00 "EADC_DAT3,ADC Data Register 3 for Sample Module 3"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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|
group.long 0x10++0x03
|
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line.long 0x00 "EADC_DAT4,ADC Data Register 4 for Sample Module 4"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x14++0x03
|
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line.long 0x00 "EADC_DAT5,ADC Data Register 5 for Sample Module 5"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "EADC_DAT6,ADC Data Register 6 for Sample Module 6"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x1C++0x03
|
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line.long 0x00 "EADC_DAT7,ADC Data Register 7 for Sample Module 7"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x20++0x03
|
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line.long 0x00 "EADC_DAT8,ADC Data Register 8 for Sample Module 8"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x24++0x03
|
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line.long 0x00 "EADC_DAT9,ADC Data Register 9 for Sample Module 9"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x28++0x03
|
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line.long 0x00 "EADC_DAT10,ADC Data Register 10 for Sample Module 10"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x2C++0x03
|
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line.long 0x00 "EADC_DAT11,ADC Data Register 11 for Sample Module 11"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "EADC_DAT12,ADC Data Register 12 for Sample Module 12"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "EADC_DAT13,ADC Data Register 13 for Sample Module 13"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "EADC_DAT14,ADC Data Register 14 for Sample Module 14"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x3C++0x03
|
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line.long 0x00 "EADC_DAT15,ADC Data Register 15 for Sample Module 15"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "EADC_DAT16,ADC Data Register 16 for Sample Module 16"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EADC_DAT17,ADC Data Register 17 for Sample Module 17"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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|
newline
|
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
group.long 0x48++0x03
|
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line.long 0x00 "EADC_DAT18,ADC Data Register 18 for Sample Module 18"
|
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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newline
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "EADC_CURDAT,ADC PDMA Current Transfer Data Register"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data (Read Only)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "EADC_CTL,ADC Control Register"
|
|
bitfld.long 0x00 11. "PDMAEN,PDMA Transfer Enable Bit\nWhen ADC conversion is completed the converted data is loaded into EADC_DATn (n: 0 ~ 18) register user can enable this bit to generate a PDMA data transfer request" "0: PDMA data transfer Disabled,1: PDMA data transfer Enabled"
|
|
bitfld.long 0x00 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in..,1: ADC conversion result will be filled in.."
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newline
|
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bitfld.long 0x00 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
|
|
bitfld.long 0x00 6.--7. "RESSEL,Resolution Selection" "0: 6-bit ADC result will be put at RESULT..,1: 8-bit ADC result will be put at RESULT..,2: 10-bit ADC result will be put at RESULT..,3: 12-bit ADC result will be put at RESULT.."
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newline
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bitfld.long 0x00 5. "ADCIEN3,Specific Sample Module ADC ADINT3 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT3 interrupt..,1: Specific sample module ADC ADINT3 interrupt.."
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bitfld.long 0x00 4. "ADCIEN2,Specific Sample Module ADC ADINT2 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT2 interrupt..,1: Specific sample module ADC ADINT2 interrupt.."
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newline
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bitfld.long 0x00 3. "ADCIEN1,Specific Sample Module ADC ADINT1 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT1 interrupt..,1: Specific sample module ADC ADINT1 interrupt.."
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bitfld.long 0x00 2. "ADCIEN0,Specific Sample Module ADC ADINT0 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT0 interrupt..,1: Specific sample module ADC ADINT0 interrupt.."
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newline
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bitfld.long 0x00 1. "ADCRST,ADC Converter Control Circuits Reset\nNote: ADCRST bit remains 1 during ADC reset when ADC reset end the ADCRST bit is automatically cleared to 0" "0: No effect,1: Cause ADC control circuits reset to initial.."
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bitfld.long 0x00 0. "ADCEN,ADC Converter Enable Bit\nNote: Before starting ADC conversion function this bit should be set to 1" "0: Disabled EADC,1: Enabled EADC"
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wgroup.long 0x54++0x03
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line.long 0x00 "EADC_SWTRG,ADC Sample Module Software Start Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "SWTRG,ADC Sample Module 0~18 Software Force to Start ADC Conversion\nNote: After writing this register to start ADC conversion the EADC_PENDSTS register will show which sample module will conversion"
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group.long 0x58++0x03
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line.long 0x00 "EADC_PENDSTS,ADC Start of Conversion Pending Flag Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "STPF,ADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation"
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group.long 0x5C++0x03
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line.long 0x00 "EADC_OVSTS,ADC Sample Module Start of Conversion Overrun Flag Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "SPOVF,ADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it"
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group.long 0x80++0x03
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line.long 0x00 "EADC_SCTL0,ADC Sample Module 0 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x84++0x03
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line.long 0x00 "EADC_SCTL1,ADC Sample Module 1 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x88++0x03
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line.long 0x00 "EADC_SCTL2,ADC Sample Module 2 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x8C++0x03
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line.long 0x00 "EADC_SCTL3,ADC Sample Module 3 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x90++0x03
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line.long 0x00 "EADC_SCTL4,ADC Sample Module 4 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x94++0x03
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line.long 0x00 "EADC_SCTL5,ADC Sample Module 5 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x98++0x03
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line.long 0x00 "EADC_SCTL6,ADC Sample Module 6 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x9C++0x03
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line.long 0x00 "EADC_SCTL7,ADC Sample Module 7 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xA0++0x03
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line.long 0x00 "EADC_SCTL8,ADC Sample Module 8 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.long 0xA4++0x03
|
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line.long 0x00 "EADC_SCTL9,ADC Sample Module 9 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
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group.long 0xA8++0x03
|
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line.long 0x00 "EADC_SCTL10,ADC Sample Module 10 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xAC++0x03
|
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line.long 0x00 "EADC_SCTL11,ADC Sample Module 11 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xB0++0x03
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line.long 0x00 "EADC_SCTL12,ADC Sample Module 12 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xB4++0x03
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line.long 0x00 "EADC_SCTL13,ADC Sample Module 13 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xB8++0x03
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line.long 0x00 "EADC_SCTL14,ADC Sample Module 14 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xBC++0x03
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line.long 0x00 "EADC_SCTL15,ADC Sample Module 15 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xC0++0x03
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line.long 0x00 "EADC_SCTL16,ADC Sample Module 16 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xC4++0x03
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line.long 0x00 "EADC_SCTL17,ADC Sample Module 17 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xC8++0x03
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line.long 0x00 "EADC_SCTL18,ADC Sample Module 18 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xD0++0x03
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line.long 0x00 "EADC_INTSRC0,ADC Interrupt 0 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EADC_INTSRC1,ADC Interrupt 1 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EADC_INTSRC2,ADC Interrupt 2 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xDC++0x03
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line.long 0x00 "EADC_INTSRC3,ADC Interrupt 3 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xE0++0x03
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line.long 0x00 "EADC_CMP0,ADC Result Compare Register 0"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EADC_CMP1,ADC Result Compare Register 1"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "EADC_CMP2,ADC Result Compare Register 2"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xEC++0x03
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line.long 0x00 "EADC_CMP3,ADC Result Compare Register 3"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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rgroup.long 0xF0++0x03
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line.long 0x00 "EADC_STATUS0,ADC Status Register 0"
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hexmask.long.word 0x00 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
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hexmask.long.word 0x00 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
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rgroup.long 0xF4++0x03
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line.long 0x00 "EADC_STATUS1,ADC Status Register 1"
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bitfld.long 0x00 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
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group.long 0xF8++0x03
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line.long 0x00 "EADC_STATUS2,ADC Status Register 2"
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rbitfld.long 0x00 27. "AOV,for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1" "0: None of sample module data register overrun..,1: Any one of sample module data register.."
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rbitfld.long 0x00 26. "AVALID,for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1" "0: None of sample module data register valid..,1: Any one of sample module data register valid.."
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rbitfld.long 0x00 25. "STOVF,for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1" "0: None of sample module event overrun flag..,1: Any one of sample module event overrun flag.."
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rbitfld.long 0x00 24. "ADOVIF,All ADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1" "0: None of ADINT interrupt flag ADOVIFn..,1: Any one of ADINT interrupt flag ADOVIFn.."
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rbitfld.long 0x00 23. "BUSY,Busy/Idle (Read Only)" "0: EADC is in idle state,1: EADC is busy at conversion"
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rbitfld.long 0x00 16.--20. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 15. "ADCMPO3,ADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 14. "ADCMPO2,ADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 13. "ADCMPO1,ADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 12. "ADCMPO0,ADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x00 11. "ADOVIF3,ADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x00 10. "ADOVIF2,ADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x00 9. "ADOVIF1,ADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x00 8. "ADOVIF0,ADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x00 7. "ADCMPF3,ADC Compare 3 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x00 6. "ADCMPF2,ADC Compare 2 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x00 5. "ADCMPF1,ADC Compare 1 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x00 4. "ADCMPF0,ADC Compare 0 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x00 3. "ADIF3,ADC ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse has been received"
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bitfld.long 0x00 2. "ADIF2,ADC ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it" "0: No ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse has been received"
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bitfld.long 0x00 1. "ADIF1,ADC ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
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bitfld.long 0x00 0. "ADIF0,ADC ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse has been received"
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rgroup.long 0xFC++0x03
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line.long 0x00 "EADC_STATUS3,ADC Status Register 3"
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bitfld.long 0x00 0.--4. "CURSPL,ADC Current Sample Module (Read Only)\nThis register shows the current ADC is controlled by which sample module control logic modules.\nIf the ADC is Idle the bit filed will set to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rgroup.long 0x100++0x03
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line.long 0x00 "EADC_DDAT0,ADC Double Data Register 0 for Sample Module 0"
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bitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x104++0x03
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line.long 0x00 "EADC_DDAT1,ADC Double Data Register 1 for Sample Module 1"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x108++0x03
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line.long 0x00 "EADC_DDAT2,ADC Double Data Register 2 for Sample Module 2"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x10C++0x03
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line.long 0x00 "EADC_DDAT3,ADC Double Data Register 3 for Sample Module 3"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x110++0x03
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line.long 0x00 "EADC_PWRM,ADC Power Management Register"
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hexmask.long.word 0x00 8.--19. 1. "LDOSUT,ADC Internal LDO Start-up Time"
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bitfld.long 0x00 2.--3. "PWDMOD,ADC Power-down Mode\nSet this bit field to select ADC Power-down mode when system power-down.\nNote: Different PWDMOD has different power down/up sequence in order to avoid ADC powering up with wrong sequence user must keep PWMOD consistent each.." "0: ADC Deep Power-down mode,1: ADC Power down,2: ADC Standby mode,3: ADC Deep Power-down mode"
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bitfld.long 0x00 1. "PWUCALEN,Power Up Calibration Function Enable Bit\nNote: This bit work together with CALSEL (EADC_CALCTL [3]) see the following\n{PWUCALEN CALSEL } Description:\nPWUCALEN is 0 and CALSEL is" "0: Calibration function Disabled at power up,1: Calibration function Enabled at power up"
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rbitfld.long 0x00 0. "PWUPRDY,ADC Power-up Sequence Completed and Ready for Conversion (Read Only)" "0: ADC is not ready for conversion may be in..,1: ADC is ready for conversion"
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group.long 0x114++0x03
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line.long 0x00 "EADC_CALCTL,ADC Calibration Control Register"
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bitfld.long 0x00 3. "CALSEL,Select Calibration Functional Block" "0: Load calibration word when calibration..,1: Execute calibration when calibration.."
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rbitfld.long 0x00 2. "CALDONE,Calibration Functional Block Complete (Read Only)" "0: During a calibration,1: Calibration is completed"
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bitfld.long 0x00 1. "CALSTART,Calibration Functional Block Start\nNote: This bit is set by SW and clear by HW after re-calibration finish" "0: Stop calibration functional block,1: Start calibration functional block"
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group.long 0x118++0x03
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line.long 0x00 "EADC_CALDWRD,ADC Calibration Load Word Register"
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hexmask.long.byte 0x00 0.--6. 1. "CALWORD,Calibration Word Bits\nWrite to this register with the previous calibration word before load calibration action.\nRead this register after calibration done.\nNote: The calibration block contains two parts 'CALIBRATION' and 'LOAD CALIBRATION' if.."
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tree.end
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tree "EADC_NS"
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base ad:0x50043000
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rgroup.long 0x00++0x03
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line.long 0x00 "EADC_DAT0,ADC Data Register 0 for Sample Module 0"
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bitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x04++0x03
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line.long 0x00 "EADC_DAT1,ADC Data Register 1 for Sample Module 1"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x08++0x03
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line.long 0x00 "EADC_DAT2,ADC Data Register 2 for Sample Module 2"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x0C++0x03
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line.long 0x00 "EADC_DAT3,ADC Data Register 3 for Sample Module 3"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x10++0x03
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line.long 0x00 "EADC_DAT4,ADC Data Register 4 for Sample Module 4"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x14++0x03
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line.long 0x00 "EADC_DAT5,ADC Data Register 5 for Sample Module 5"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x18++0x03
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line.long 0x00 "EADC_DAT6,ADC Data Register 6 for Sample Module 6"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x1C++0x03
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line.long 0x00 "EADC_DAT7,ADC Data Register 7 for Sample Module 7"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x20++0x03
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line.long 0x00 "EADC_DAT8,ADC Data Register 8 for Sample Module 8"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x24++0x03
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line.long 0x00 "EADC_DAT9,ADC Data Register 9 for Sample Module 9"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x28++0x03
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line.long 0x00 "EADC_DAT10,ADC Data Register 10 for Sample Module 10"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x2C++0x03
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line.long 0x00 "EADC_DAT11,ADC Data Register 11 for Sample Module 11"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x30++0x03
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line.long 0x00 "EADC_DAT12,ADC Data Register 12 for Sample Module 12"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x34++0x03
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line.long 0x00 "EADC_DAT13,ADC Data Register 13 for Sample Module 13"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x38++0x03
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line.long 0x00 "EADC_DAT14,ADC Data Register 14 for Sample Module 14"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x3C++0x03
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line.long 0x00 "EADC_DAT15,ADC Data Register 15 for Sample Module 15"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x40++0x03
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line.long 0x00 "EADC_DAT16,ADC Data Register 16 for Sample Module 16"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x44++0x03
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line.long 0x00 "EADC_DAT17,ADC Data Register 17 for Sample Module 17"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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group.long 0x48++0x03
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line.long 0x00 "EADC_DAT18,ADC Data Register 18 for Sample Module 18"
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rbitfld.long 0x00 17. "VALID,Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] bits is not valid,1: Data in RESULT[11:0] bits is valid"
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is" "0: Data in RESULT[11:0] is recent conversion..,1: Data in RESULT[11:0] is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF.."
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rgroup.long 0x4C++0x03
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line.long 0x00 "EADC_CURDAT,ADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data (Read Only)"
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group.long 0x50++0x03
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line.long 0x00 "EADC_CTL,ADC Control Register"
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bitfld.long 0x00 11. "PDMAEN,PDMA Transfer Enable Bit\nWhen ADC conversion is completed the converted data is loaded into EADC_DATn (n: 0 ~ 18) register user can enable this bit to generate a PDMA data transfer request" "0: PDMA data transfer Disabled,1: PDMA data transfer Enabled"
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bitfld.long 0x00 9. "DMOF,ADC Differential Input Mode Output Format" "0: ADC conversion result will be filled in..,1: ADC conversion result will be filled in.."
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bitfld.long 0x00 8. "DIFFEN,Differential Analog Input Mode Enable Bit" "0: Single-end analog input mode,1: Differential analog input mode"
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bitfld.long 0x00 6.--7. "RESSEL,Resolution Selection" "0: 6-bit ADC result will be put at RESULT..,1: 8-bit ADC result will be put at RESULT..,2: 10-bit ADC result will be put at RESULT..,3: 12-bit ADC result will be put at RESULT.."
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bitfld.long 0x00 5. "ADCIEN3,Specific Sample Module ADC ADINT3 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT3 interrupt..,1: Specific sample module ADC ADINT3 interrupt.."
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bitfld.long 0x00 4. "ADCIEN2,Specific Sample Module ADC ADINT2 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT2 interrupt..,1: Specific sample module ADC ADINT2 interrupt.."
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bitfld.long 0x00 3. "ADCIEN1,Specific Sample Module ADC ADINT1 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT1 interrupt..,1: Specific sample module ADC ADINT1 interrupt.."
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bitfld.long 0x00 2. "ADCIEN0,Specific Sample Module ADC ADINT0 Interrupt Enable Bit\nThe ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion" "0: Specific sample module ADC ADINT0 interrupt..,1: Specific sample module ADC ADINT0 interrupt.."
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bitfld.long 0x00 1. "ADCRST,ADC Converter Control Circuits Reset\nNote: ADCRST bit remains 1 during ADC reset when ADC reset end the ADCRST bit is automatically cleared to 0" "0: No effect,1: Cause ADC control circuits reset to initial.."
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bitfld.long 0x00 0. "ADCEN,ADC Converter Enable Bit\nNote: Before starting ADC conversion function this bit should be set to 1" "0: Disabled EADC,1: Enabled EADC"
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wgroup.long 0x54++0x03
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line.long 0x00 "EADC_SWTRG,ADC Sample Module Software Start Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "SWTRG,ADC Sample Module 0~18 Software Force to Start ADC Conversion\nNote: After writing this register to start ADC conversion the EADC_PENDSTS register will show which sample module will conversion"
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group.long 0x58++0x03
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line.long 0x00 "EADC_PENDSTS,ADC Start of Conversion Pending Flag Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "STPF,ADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation"
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group.long 0x5C++0x03
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line.long 0x00 "EADC_OVSTS,ADC Sample Module Start of Conversion Overrun Flag Register"
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hexmask.long.tbyte 0x00 0.--18. 1. "SPOVF,ADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it"
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group.long 0x80++0x03
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line.long 0x00 "EADC_SCTL0,ADC Sample Module 0 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x84++0x03
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line.long 0x00 "EADC_SCTL1,ADC Sample Module 1 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x88++0x03
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line.long 0x00 "EADC_SCTL2,ADC Sample Module 2 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
|
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
|
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
|
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x8C++0x03
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line.long 0x00 "EADC_SCTL3,ADC Sample Module 3 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy user can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 23. "DBMEN,Double Buffer Mode Enable Bit" "0: Sample has one sample result register (default),1: Sample has two sample result registers"
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newline
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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newline
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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newline
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x90++0x03
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line.long 0x00 "EADC_SCTL4,ADC Sample Module 4 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x94++0x03
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line.long 0x00 "EADC_SCTL5,ADC Sample Module 5 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x98++0x03
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line.long 0x00 "EADC_SCTL6,ADC Sample Module 6 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x9C++0x03
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line.long 0x00 "EADC_SCTL7,ADC Sample Module 7 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xA0++0x03
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line.long 0x00 "EADC_SCTL8,ADC Sample Module 8 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
|
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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|
newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xA4++0x03
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line.long 0x00 "EADC_SCTL9,ADC Sample Module 9 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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newline
|
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xA8++0x03
|
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line.long 0x00 "EADC_SCTL10,ADC Sample Module 10 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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|
newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
|
|
newline
|
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xAC++0x03
|
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line.long 0x00 "EADC_SCTL11,ADC Sample Module 11 Control Register"
|
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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|
newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
|
|
newline
|
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB0++0x03
|
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line.long 0x00 "EADC_SCTL12,ADC Sample Module 12 Control Register"
|
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "EADC_SCTL13,ADC Sample Module 13 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
|
|
bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
|
|
newline
|
|
bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
|
|
bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "EADC_SCTL14,ADC Sample Module 14 Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
|
|
bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
|
|
newline
|
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xBC++0x03
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line.long 0x00 "EADC_SCTL15,ADC Sample Module 15 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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bitfld.long 0x00 22. "INTPOS,Interrupt Flag Position Select" "0: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC end..,1: Set ADIFn (EADC_STATUS2[n] n=0~3) at ADC.."
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bitfld.long 0x00 16.--20. "TRGSEL,ADC Sample Module Start of Conversion Trigger Source Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x00 8.--15. 1. "TRGDLYCNT,ADC Sample Module Start of Conversion Trigger Delay Time"
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bitfld.long 0x00 6.--7. "TRGDLYDIV,ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency" "0: ADC_CLK/1,1: ADC_CLK/2,2: ADC_CLK/4,3: ADC_CLK/16"
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bitfld.long 0x00 5. "EXTFEN,ADC External Trigger Falling Edge Enable Bit" "0: Falling edge Disabled when ADC selects..,1: Falling edge Enabled when ADC selects.."
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bitfld.long 0x00 4. "EXTREN,ADC External Trigger Rising Edge Enable Bit" "0: Rising edge Disabled when ADC selects..,1: Rising edge Enabled when ADC selects EADC0_ST.."
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bitfld.long 0x00 0.--3. "CHSEL,ADC Sample Module Channel Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xC0++0x03
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line.long 0x00 "EADC_SCTL16,ADC Sample Module 16 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xC4++0x03
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line.long 0x00 "EADC_SCTL17,ADC Sample Module 17 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xC8++0x03
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line.long 0x00 "EADC_SCTL18,ADC Sample Module 18 Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Sampling Time Extend\nWhen ADC converting at high conversion rate the sampling time of analog input voltage may not enough if input channel loading is heavy SW can extend ADC sampling time after trigger source is coming to get enough.."
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group.long 0xD0++0x03
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line.long 0x00 "EADC_INTSRC0,ADC Interrupt 0 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EADC_INTSRC1,ADC Interrupt 1 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EADC_INTSRC2,ADC Interrupt 2 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xDC++0x03
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line.long 0x00 "EADC_INTSRC3,ADC Interrupt 3 Source Enable Control Register"
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bitfld.long 0x00 18. "SPLIE18,Sample Module 18 Interrupt Enable Bit" "0: Sample Module 18 interrupt Disabled,1: Sample Module 18 interrupt Enabled"
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bitfld.long 0x00 17. "SPLIE17,Sample Module 17 Interrupt Enable Bit" "0: Sample Module 17 interrupt Disabled,1: Sample Module 17 interrupt Enabled"
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bitfld.long 0x00 16. "SPLIE16,Sample Module 16 Interrupt Enable Bit" "0: Sample Module 16 interrupt Disabled,1: Sample Module 16 interrupt Enabled"
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bitfld.long 0x00 15. "SPLIE15,Sample Module 15 Interrupt Enable Bit" "0: Sample Module 15 interrupt Disabled,1: Sample Module 15 interrupt Enabled"
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bitfld.long 0x00 14. "SPLIE14,Sample Module 14 Interrupt Enable Bit" "0: Sample Module 14 interrupt Disabled,1: Sample Module 14 interrupt Enabled"
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bitfld.long 0x00 13. "SPLIE13,Sample Module 13 Interrupt Enable Bit" "0: Sample Module 13 interrupt Disabled,1: Sample Module 13 interrupt Enabled"
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bitfld.long 0x00 12. "SPLIE12,Sample Module 12 Interrupt Enable Bit" "0: Sample Module 12 interrupt Disabled,1: Sample Module 12 interrupt Enabled"
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bitfld.long 0x00 11. "SPLIE11,Sample Module 11 Interrupt Enable Bit" "0: Sample Module 11 interrupt Disabled,1: Sample Module 11 interrupt Enabled"
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bitfld.long 0x00 10. "SPLIE10,Sample Module 10 Interrupt Enable Bit" "0: Sample Module 10 interrupt Disabled,1: Sample Module 10 interrupt Enabled"
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bitfld.long 0x00 9. "SPLIE9,Sample Module 9 Interrupt Enable Bit" "0: Sample Module 9 interrupt Disabled,1: Sample Module 9 interrupt Enabled"
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bitfld.long 0x00 8. "SPLIE8,Sample Module 8 Interrupt Enable Bit" "0: Sample Module 8 interrupt Disabled,1: Sample Module 8 interrupt Enabled"
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bitfld.long 0x00 7. "SPLIE7,Sample Module 7 Interrupt Enable Bit" "0: Sample Module 7 interrupt Disabled,1: Sample Module 7 interrupt Enabled"
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bitfld.long 0x00 6. "SPLIE6,Sample Module 6 Interrupt Enable Bit" "0: Sample Module 6 interrupt Disabled,1: Sample Module 6 interrupt Enabled"
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bitfld.long 0x00 5. "SPLIE5,Sample Module 5 Interrupt Enable Bit" "0: Sample Module 5 interrupt Disabled,1: Sample Module 5 interrupt Enabled"
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bitfld.long 0x00 4. "SPLIE4,Sample Module 4 Interrupt Enable Bit" "0: Sample Module 4 interrupt Disabled,1: Sample Module 4 interrupt Enabled"
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bitfld.long 0x00 3. "SPLIE3,Sample Module 3 Interrupt Enable Bit" "0: Sample Module 3 interrupt Disabled,1: Sample Module 3 interrupt Enabled"
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bitfld.long 0x00 2. "SPLIE2,Sample Module 2 Interrupt Enable Bit" "0: Sample Module 2 interrupt Disabled,1: Sample Module 2 interrupt Enabled"
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bitfld.long 0x00 1. "SPLIE1,Sample Module 1 Interrupt Enable Bit" "0: Sample Module 1 interrupt Disabled,1: Sample Module 1 interrupt Enabled"
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newline
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bitfld.long 0x00 0. "SPLIE0,Sample Module 0 Interrupt Enable Bit" "0: Sample Module 0 interrupt Disabled,1: Sample Module 0 interrupt Enabled"
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group.long 0xE0++0x03
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line.long 0x00 "EADC_CMP0,ADC Result Compare Register 0"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xE4++0x03
|
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line.long 0x00 "EADC_CMP1,ADC Result Compare Register 1"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xE8++0x03
|
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line.long 0x00 "EADC_CMP2,ADC Result Compare Register 2"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
|
|
bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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group.long 0xEC++0x03
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line.long 0x00 "EADC_CMP3,ADC Result Compare Register 3"
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hexmask.long.word 0x00 16.--27. 1. "CMPDAT,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register" "0: ADCMPF0 (EADC_STATUS2[4]) will be set when..,1: ADCMPF0 (EADC_STATUS2[4]) will be set when.."
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bitfld.long 0x00 8.--11. "CMPMCNT,Compare Match Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPSPL,Compare Sample Module Selection" "0: Sample Module 0 conversion result EADC_DAT0..,1: Sample Module 1 conversion result EADC_DAT1..,2: Sample Module 2 conversion result EADC_DAT2..,3: Sample Module 3 conversion result EADC_DAT3..,4: Sample Module 4 conversion result EADC_DAT4..,5: Sample Module 5 conversion result EADC_DAT5..,6: Sample Module 6 conversion result EADC_DAT6..,7: Sample Module 7 conversion result EADC_DAT7..,8: Sample Module 8 conversion result EADC_DAT8..,9: Sample Module 9 conversion result EADC_DAT9..,10: Sample Module 10 conversion result..,11: Sample Module 11 conversion result..,12: Sample Module 12 conversion result..,13: Sample Module 13 conversion result..,14: Sample Module 14 conversion result..,15: Sample Module 15 conversion result..,16: Sample Module 16 conversion result..,17: Sample Module 17 conversion result..,18: Sample Module 18 conversion result..,?..."
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newline
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bitfld.long 0x00 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "ADCMPIE,ADC Result Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "ADCMPEN,ADC Result Compare Enable Bit" "0: Compare Disabled,1: Compare Enabled"
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rgroup.long 0xF0++0x03
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line.long 0x00 "EADC_STATUS0,ADC Status Register 0"
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hexmask.long.word 0x00 16.--31. 1. "OV,EADC_DAT0~15 Overrun Flag"
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hexmask.long.word 0x00 0.--15. 1. "VALID,EADC_DAT0~15 Data Valid Flag"
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rgroup.long 0xF4++0x03
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line.long 0x00 "EADC_STATUS1,ADC Status Register 1"
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bitfld.long 0x00 16.--18. "OV,EADC_DAT16~18 Overrun Flag" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "VALID,EADC_DAT16~18 Data Valid Flag" "0,1,2,3,4,5,6,7"
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group.long 0xF8++0x03
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line.long 0x00 "EADC_STATUS2,ADC Status Register 2"
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rbitfld.long 0x00 27. "AOV,for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1" "0: None of sample module data register overrun..,1: Any one of sample module data register.."
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rbitfld.long 0x00 26. "AVALID,for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1" "0: None of sample module data register valid..,1: Any one of sample module data register valid.."
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rbitfld.long 0x00 25. "STOVF,for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1" "0: None of sample module event overrun flag..,1: Any one of sample module event overrun flag.."
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rbitfld.long 0x00 24. "ADOVIF,All ADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1" "0: None of ADINT interrupt flag ADOVIFn..,1: Any one of ADINT interrupt flag ADOVIFn.."
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rbitfld.long 0x00 23. "BUSY,Busy/Idle (Read Only)" "0: EADC is in idle state,1: EADC is busy at conversion"
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rbitfld.long 0x00 16.--20. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 15. "ADCMPO3,ADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 14. "ADCMPO2,ADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 13. "ADCMPO1,ADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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rbitfld.long 0x00 12. "ADCMPO0,ADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module" "0: Conversion result in EADC_DAT less than..,1: Conversion result in EADC_DAT great than or.."
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bitfld.long 0x00 11. "ADOVIF3,ADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT3 interrupt flag is not overwritten to 1,1: ADINT3 interrupt flag is overwritten to 1"
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bitfld.long 0x00 10. "ADOVIF2,ADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT2 interrupt flag is not overwritten to 1,1: ADINT2 interrupt flag is s overwritten to 1"
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bitfld.long 0x00 9. "ADOVIF1,ADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT1 interrupt flag is not overwritten to 1,1: ADINT1 interrupt flag is overwritten to 1"
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bitfld.long 0x00 8. "ADOVIF0,ADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it" "0: ADINT0 interrupt flag is not overwritten to 1,1: ADINT0 interrupt flag is overwritten to 1"
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bitfld.long 0x00 7. "ADCMPF3,ADC Compare 3 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP3.."
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bitfld.long 0x00 6. "ADCMPF2,ADC Compare 2 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP2.."
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bitfld.long 0x00 5. "ADCMPF1,ADC Compare 1 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP1.."
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bitfld.long 0x00 4. "ADCMPF0,ADC Compare 0 Flag\nWhen the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it" "0: Conversion result in EADC_DAT does not meet..,1: Conversion result in EADC_DAT meets EADC_CMP0.."
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bitfld.long 0x00 3. "ADIF3,ADC ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT3 interrupt pulse received,1: ADINT3 interrupt pulse has been received"
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bitfld.long 0x00 2. "ADIF2,ADC ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it" "0: No ADINT2 interrupt pulse received,1: ADINT2 interrupt pulse has been received"
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bitfld.long 0x00 1. "ADIF1,ADC ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT1 interrupt pulse received,1: ADINT1 interrupt pulse has been received"
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bitfld.long 0x00 0. "ADIF0,ADC ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an ADC conversion of specific sample module has been completed" "0: No ADINT0 interrupt pulse received,1: ADINT0 interrupt pulse has been received"
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rgroup.long 0xFC++0x03
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line.long 0x00 "EADC_STATUS3,ADC Status Register 3"
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bitfld.long 0x00 0.--4. "CURSPL,ADC Current Sample Module (Read Only)\nThis register shows the current ADC is controlled by which sample module control logic modules.\nIf the ADC is Idle the bit filed will set to 0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rgroup.long 0x100++0x03
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line.long 0x00 "EADC_DDAT0,ADC Double Data Register 0 for Sample Module 0"
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bitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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bitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x104++0x03
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line.long 0x00 "EADC_DDAT1,ADC Double Data Register 1 for Sample Module 1"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x108++0x03
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line.long 0x00 "EADC_DDAT2,ADC Double Data Register 2 for Sample Module 2"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x10C++0x03
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line.long 0x00 "EADC_DDAT3,ADC Double Data Register 3 for Sample Module 3"
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rbitfld.long 0x00 17. "VALID,Valid Flag" "0: Double data in RESULT (EADC_DDATn[15:0]) is..,1: Double data in RESULT (EADC_DDATn[15:0]) is.."
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rbitfld.long 0x00 16. "OV,Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register OV is set to 1" "0: Data in RESULT (EADC_DATn[15:0] n=0~3) is..,1: Data in RESULT (EADC_DATn[15:0] n=0~3) is over"
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hexmask.long.word 0x00 0.--15. 1. "RESULT,ADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen.."
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group.long 0x110++0x03
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line.long 0x00 "EADC_PWRM,ADC Power Management Register"
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hexmask.long.word 0x00 8.--19. 1. "LDOSUT,ADC Internal LDO Start-up Time"
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bitfld.long 0x00 2.--3. "PWDMOD,ADC Power-down Mode\nSet this bit field to select ADC Power-down mode when system power-down.\nNote: Different PWDMOD has different power down/up sequence in order to avoid ADC powering up with wrong sequence user must keep PWMOD consistent each.." "0: ADC Deep Power-down mode,1: ADC Power down,2: ADC Standby mode,3: ADC Deep Power-down mode"
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bitfld.long 0x00 1. "PWUCALEN,Power Up Calibration Function Enable Bit\nNote: This bit work together with CALSEL (EADC_CALCTL [3]) see the following\n{PWUCALEN CALSEL } Description:\nPWUCALEN is 0 and CALSEL is" "0: Calibration function Disabled at power up,1: Calibration function Enabled at power up"
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rbitfld.long 0x00 0. "PWUPRDY,ADC Power-up Sequence Completed and Ready for Conversion (Read Only)" "0: ADC is not ready for conversion may be in..,1: ADC is ready for conversion"
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group.long 0x114++0x03
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line.long 0x00 "EADC_CALCTL,ADC Calibration Control Register"
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bitfld.long 0x00 3. "CALSEL,Select Calibration Functional Block" "0: Load calibration word when calibration..,1: Execute calibration when calibration.."
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rbitfld.long 0x00 2. "CALDONE,Calibration Functional Block Complete (Read Only)" "0: During a calibration,1: Calibration is completed"
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bitfld.long 0x00 1. "CALSTART,Calibration Functional Block Start\nNote: This bit is set by SW and clear by HW after re-calibration finish" "0: Stop calibration functional block,1: Start calibration functional block"
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group.long 0x118++0x03
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line.long 0x00 "EADC_CALDWRD,ADC Calibration Load Word Register"
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hexmask.long.byte 0x00 0.--6. 1. "CALWORD,Calibration Word Bits\nWrite to this register with the previous calibration word before load calibration action.\nRead this register after calibration done.\nNote: The calibration block contains two parts 'CALIBRATION' and 'LOAD CALIBRATION' if.."
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tree.end
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tree.end
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tree "EBI"
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tree "EBI"
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base ad:0x40010000
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group.long 0x00++0x03
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line.long 0x00 "EBI_CTL0,External Bus Interface Bank0 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x10++0x03
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line.long 0x00 "EBI_CTL1,External Bus Interface Bank1 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x14++0x03
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line.long 0x00 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x20++0x03
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line.long 0x00 "EBI_CTL2,External Bus Interface Bank2 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x24++0x03
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line.long 0x00 "EBI_TCTL2,External Bus Interface Bank2 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "EBI_NS"
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base ad:0x50010000
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group.long 0x00++0x03
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line.long 0x00 "EBI_CTL0,External Bus Interface Bank0 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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newline
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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newline
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x10++0x03
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line.long 0x00 "EBI_CTL1,External Bus Interface Bank1 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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newline
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x14++0x03
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line.long 0x00 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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newline
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x20++0x03
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line.long 0x00 "EBI_CTL2,External Bus Interface Bank2 Control Register"
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bitfld.long 0x00 24. "WBUFEN,EBI Write Buffer Enable Bit\nNote: This bit only available in EBI_CTL0 register" "0: EBI write buffer Disabled,1: EBI write buffer Enabled"
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bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen con tenuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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newline
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bitfld.long 0x00 3. "ADSEPEN,EBI Address/Data Bus Separating Mode Enable Bit" "0: Address/Data Bus Separating Mode Disabled,1: Address/Data Bus Separating Mode Enabled"
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bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse\nThis bit defines the active level of EBI chip select pin (EBI_nCS)" "0: Chip select pin (EBI_nCS) is active low,1: Chip select pin (EBI_nCS) is active high"
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newline
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
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group.long 0x24++0x03
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line.long 0x00 "EBI_TCTL2,External Bus Interface Bank2 Timing Control Register"
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bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.\nWhen read action is finished and the next action is going to read R2R idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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newline
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bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle.\nWhen write action is finished W2X idle cycle is inserted and EBI_nCS return to idle state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD defines data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC defines data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree.end
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tree "ECAP"
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tree "ECAP0"
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base ad:0x400B4000
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group.long 0x00++0x03
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line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
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group.long 0x04++0x03
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line.long 0x00 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x08++0x03
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line.long 0x00 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x0C++0x03
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line.long 0x00 "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x10++0x03
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line.long 0x00 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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group.long 0x14++0x03
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line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Control" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x00 28. "CMPEN,Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
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newline
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bitfld.long 0x00 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear..,1: Compare-match event (CAPCMPF) can clear.."
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bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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newline
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bitfld.long 0x00 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x00 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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newline
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bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Control" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Control" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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newline
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bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Control" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: Reserved,2: CAP2 input is from signal CHX of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: Reserved,2: CAP1 input is from signal CHB of QEI..,3: Reserved"
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bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: Reserved,2: CAP0 input is from signal CHA of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Control" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x00 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Control" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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newline
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bitfld.long 0x00 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Control" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x00 3. "CAPNFDIS,Input Capture Noise Filter Disable Control" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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newline
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16,4: CAP_CLK/32,5: CAP_CLK/64,?..."
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group.long 0x18++0x03
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line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x00 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x00 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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newline
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bitfld.long 0x00 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x00 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
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newline
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bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
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bitfld.long 0x00 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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newline
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bitfld.long 0x00 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x00 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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newline
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bitfld.long 0x00 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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newline
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bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x00 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored" "0,1"
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rbitfld.long 0x00 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored" "0,1"
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newline
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rbitfld.long 0x00 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored" "0,1"
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bitfld.long 0x00 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since.."
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newline
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bitfld.long 0x00 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT has not matched ECAP_CNTCMP value..,1: ECAP_CNT has matched ECAP_CNTCMP value at.."
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bitfld.long 0x00 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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newline
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bitfld.long 0x00 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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bitfld.long 0x00 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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tree.end
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tree "ECAP0_NS"
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base ad:0x500B4000
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group.long 0x00++0x03
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line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
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group.long 0x04++0x03
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line.long 0x00 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x08++0x03
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line.long 0x00 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x0C++0x03
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line.long 0x00 "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x10++0x03
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line.long 0x00 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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group.long 0x14++0x03
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line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Control" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x00 28. "CMPEN,Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
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newline
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bitfld.long 0x00 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear..,1: Compare-match event (CAPCMPF) can clear.."
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bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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newline
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bitfld.long 0x00 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x00 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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newline
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bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Control" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Control" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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newline
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bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Control" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: Reserved,2: CAP2 input is from signal CHX of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: Reserved,2: CAP1 input is from signal CHB of QEI..,3: Reserved"
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bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: Reserved,2: CAP0 input is from signal CHA of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Control" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x00 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Control" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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newline
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bitfld.long 0x00 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Control" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x00 3. "CAPNFDIS,Input Capture Noise Filter Disable Control" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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newline
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16,4: CAP_CLK/32,5: CAP_CLK/64,?..."
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group.long 0x18++0x03
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line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x00 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x00 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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newline
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bitfld.long 0x00 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x00 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
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newline
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bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
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bitfld.long 0x00 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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newline
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bitfld.long 0x00 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x00 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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newline
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bitfld.long 0x00 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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newline
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bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x00 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored" "0,1"
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rbitfld.long 0x00 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored" "0,1"
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newline
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rbitfld.long 0x00 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored" "0,1"
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bitfld.long 0x00 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since.."
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newline
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bitfld.long 0x00 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT has not matched ECAP_CNTCMP value..,1: ECAP_CNT has matched ECAP_CNTCMP value at.."
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bitfld.long 0x00 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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newline
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bitfld.long 0x00 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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bitfld.long 0x00 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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tree.end
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tree "ECAP1"
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base ad:0x400B5000
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group.long 0x00++0x03
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line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
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group.long 0x04++0x03
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line.long 0x00 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x08++0x03
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line.long 0x00 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x0C++0x03
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line.long 0x00 "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x10++0x03
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line.long 0x00 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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group.long 0x14++0x03
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line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Control" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x00 28. "CMPEN,Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
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newline
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bitfld.long 0x00 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear..,1: Compare-match event (CAPCMPF) can clear.."
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bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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newline
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bitfld.long 0x00 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x00 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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newline
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bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Control" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Control" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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newline
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bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Control" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: Reserved,2: CAP2 input is from signal CHX of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: Reserved,2: CAP1 input is from signal CHB of QEI..,3: Reserved"
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bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: Reserved,2: CAP0 input is from signal CHA of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Control" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x00 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Control" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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newline
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bitfld.long 0x00 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Control" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x00 3. "CAPNFDIS,Input Capture Noise Filter Disable Control" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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newline
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16,4: CAP_CLK/32,5: CAP_CLK/64,?..."
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group.long 0x18++0x03
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line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x00 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x00 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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newline
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bitfld.long 0x00 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x00 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
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newline
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bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
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bitfld.long 0x00 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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newline
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bitfld.long 0x00 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x00 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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newline
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bitfld.long 0x00 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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newline
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bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x00 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored" "0,1"
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rbitfld.long 0x00 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored" "0,1"
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newline
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rbitfld.long 0x00 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored" "0,1"
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bitfld.long 0x00 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since.."
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newline
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bitfld.long 0x00 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT has not matched ECAP_CNTCMP value..,1: ECAP_CNT has matched ECAP_CNTCMP value at.."
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bitfld.long 0x00 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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newline
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bitfld.long 0x00 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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bitfld.long 0x00 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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tree.end
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tree "ECAP1_NS"
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base ad:0x500B5000
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group.long 0x00++0x03
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line.long 0x00 "ECAP_CNT,Input Capture Counter (24-bit Up Counter)"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter"
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group.long 0x04++0x03
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line.long 0x00 "ECAP_HLD0,Input Capture Hold Register 0"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x08++0x03
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line.long 0x00 "ECAP_HLD1,Input Capture Hold Register 1"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x0C++0x03
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line.long 0x00 "ECAP_HLD2,Input Capture Hold Register 2"
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hexmask.long.tbyte 0x00 0.--23. 1. "HOLD,Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change the ECAPCNT value is latched into the corresponding holding register"
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group.long 0x10++0x03
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line.long 0x00 "ECAP_CNTCMP,Input Capture Compare Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNTCMP,Input Capture Counter Compare Register"
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group.long 0x14++0x03
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line.long 0x00 "ECAP_CTL0,Input Capture Control Register 0"
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bitfld.long 0x00 29. "CAPEN,Input Capture Timer/Counter Enable Control" "0: Input Capture function Disabled,1: Input Capture function Enabled"
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bitfld.long 0x00 28. "CMPEN,Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP if ECAP_CNT value reaches ECAP_CNTCMP the flag CAPCMPF will be set" "0: The compare function Disabled,1: The compare function Enabled"
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newline
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bitfld.long 0x00 25. "CMPCLREN,Input Capture Counter Cleared by Compare-match Control" "0: Compare-match event (CAPCMPF) can clear..,1: Compare-match event (CAPCMPF) can clear.."
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bitfld.long 0x00 24. "CNTEN,Input Capture Counter Start Counting Control\nSetting this bit to 1 the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from" "0: ECAP_CNT stop counting,1: ECAP_CNT starts up-counting"
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newline
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bitfld.long 0x00 21. "CMPIEN,CAPCMPF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPCMPF can trigger Input Capture..,1: The flag CAPCMPF can trigger Input Capture.."
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bitfld.long 0x00 20. "OVIEN,CAPOVF Trigger Input Capture Interrupt Enable Control" "0: The flag CAPOVF can trigger Input Capture..,1: The flag CAPOVF can trigger Input Capture.."
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newline
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bitfld.long 0x00 18. "CAPIEN2,Input Capture Channel 2 Interrupt Enable Control" "0: The flag CAPTF2 can trigger Input Capture..,1: The flag CAPTF2 can trigger Input Capture.."
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bitfld.long 0x00 17. "CAPIEN1,Input Capture Channel 1 Interrupt Enable Control" "0: The flag CAPTF1 can trigger Input Capture..,1: The flag CAPTF1 can trigger Input Capture.."
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newline
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bitfld.long 0x00 16. "CAPIEN0,Input Capture Channel 0 Interrupt Enable Control" "0: The flag CAPTF0 can trigger Input Capture..,1: The flag CAPTF0 can trigger Input Capture.."
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bitfld.long 0x00 12.--13. "CAPSEL2,CAP2 Input Source Selection" "0: CAP2 input is from port pin ICAP2,1: Reserved,2: CAP2 input is from signal CHX of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "CAPSEL1,CAP1 Input Source Selection" "0: CAP1 input is from port pin ICAP1,1: Reserved,2: CAP1 input is from signal CHB of QEI..,3: Reserved"
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bitfld.long 0x00 8.--9. "CAPSEL0,CAP0 Input Source Selection" "0: CAP0 input is from port pin ICAP0,1: Reserved,2: CAP0 input is from signal CHA of QEI..,3: Reserved"
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newline
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bitfld.long 0x00 6. "IC2EN,Port Pin IC2 Input to Input Capture Unit Enable Control" "0: IC2 input to Input Capture Unit Disabled,1: IC2 input to Input Capture Unit Enabled"
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bitfld.long 0x00 5. "IC1EN,Port Pin IC1 Input to Input Capture Unit Enable Control" "0: IC1 input to Input Capture Unit Disabled,1: IC1 input to Input Capture Unit Enabled"
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bitfld.long 0x00 4. "IC0EN,Port Pin IC0 Input to Input Capture Unit Enable Control" "0: IC0 input to Input Capture Unit Disabled,1: IC0 input to Input Capture Unit Enabled"
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bitfld.long 0x00 3. "CAPNFDIS,Input Capture Noise Filter Disable Control" "0: Noise filter of Input Capture Enabled,1: Noise filter of Input Capture Disabled (Bypass)"
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: CAP_CLK,1: CAP_CLK/2,2: CAP_CLK/4,3: CAP_CLK/16,4: CAP_CLK/32,5: CAP_CLK/64,?..."
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group.long 0x18++0x03
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line.long 0x00 "ECAP_CTL1,Input Capture Control Register 1"
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bitfld.long 0x00 22. "CAP2CLREN,Capture Counter Cleared by Capture Event2 Control" "0: Event CAPTE2 can clear capture counter..,1: Event CAPTE2 can clear capture counter.."
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bitfld.long 0x00 21. "CAP1CLREN,Capture Counter Cleared by Capture Event1 Control" "0: Event CAPTE1 can clear capture counter..,1: Event CAPTE1 can clear capture counter.."
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bitfld.long 0x00 20. "CAP0CLREN,Capture Counter Cleared by Capture Event0 Control" "0: Event CAPTE0 can clear capture counter..,1: Event CAPTE0 can clear capture counter.."
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bitfld.long 0x00 16.--17. "CNTSRCSEL,Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source" "0: CAP_CLK (default),1: CAP0,2: CAP1,3: CAP2"
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bitfld.long 0x00 12.--14. "CLKSEL,Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]" "0: CAP_CLK/1,1: CAP_CLK/4,2: CAP_CLK/16,3: CAP_CLK/32,4: CAP_CLK/64,5: CAP_CLK/96,6: CAP_CLK/112,7: CAP_CLK/128"
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bitfld.long 0x00 11. "OVRLDEN,Capture Counter's Reload Function Triggered by Overflow Enable Bit" "0: The reload triggered by CAPOV Disabled,1: The reload triggered by CAPOV Enabled"
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bitfld.long 0x00 10. "CAP2RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit" "0: The reload triggered by Event CAPTE2 Disabled,1: The reload triggered by Event CAPTE2 Enabled"
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bitfld.long 0x00 9. "CAP1RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit" "0: The reload triggered by Event CAPTE1 Disabled,1: The reload triggered by Event CAPTE1 Enabled"
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bitfld.long 0x00 8. "CAP0RLDEN,Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit" "0: The reload triggered by Event CAPTE0 Disabled,1: The reload triggered by Event CAPTE0 Enabled"
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bitfld.long 0x00 4.--5. "EDGESEL2,Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only rising edge change only or both edge changes" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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bitfld.long 0x00 2.--3. "EDGESEL1,Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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bitfld.long 0x00 0.--1. "EDGESEL0,Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only rising edge change only or both edge change" "0: Detect rising edge only,1: Detect falling edge only.\nDetect both rising..,?..."
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group.long 0x1C++0x03
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line.long 0x00 "ECAP_STATUS,Input Capture Status Register"
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rbitfld.long 0x00 10. "CAP2,Value of Input Channel 2 CAP2 (Read Only)\nReflecting the value of input channel 2 CAP2.\nNote: The bit is read only and write is ignored" "0,1"
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rbitfld.long 0x00 9. "CAP1,Value of Input Channel 1 CAP1 (Read Only)\nReflecting the value of input channel 1 CAP1\nNote: The bit is read only and write is ignored" "0,1"
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rbitfld.long 0x00 8. "CAP0,Value of Input Channel 0 CAP0 (Read Only)\nReflecting the value of input channel 0 CAP0\nNote: The bit is read only and write is ignored" "0,1"
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bitfld.long 0x00 5. "CAPOVF,Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it" "0: No overflow event has occurred since last clear,1: Overflow event(s) has/have occurred since.."
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bitfld.long 0x00 4. "CAPCMPF,Input Capture Compare-match Flag\nIf the input capture compare function is enabled the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it" "0: ECAP_CNT has not matched ECAP_CNTCMP value..,1: ECAP_CNT has matched ECAP_CNTCMP value at.."
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bitfld.long 0x00 2. "CAPTF2,Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input it will set flag CAPTF2 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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bitfld.long 0x00 1. "CAPTF1,Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input it will set flag CAPTF1 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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bitfld.long 0x00 0. "CAPTF0,Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input it will set flag CAPTF0 to high" "0: No valid edge change has been detected at..,1: At least a valid edge change has been.."
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tree.end
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tree.end
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tree "EPWM"
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tree "EPWM0"
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base ad:0x40058000
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group.long 0x00++0x03
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line.long 0x00 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects EPWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "EPWM_CTL1,EPWM Control Register 1"
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bitfld.long 0x00 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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newline
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bitfld.long 0x00 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the..,1: The inversed state of pin SYNC is passed to.."
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newline
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN..,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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newline
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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newline
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bitfld.long 0x00 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CLKPSC0_1,EPWM Clock Prescale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_CLKPSC2_3,EPWM Clock Prescale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_CLKPSC4_5,EPWM Clock Prescale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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newline
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bitfld.long 0x00 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x00 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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newline
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bitfld.long 0x00 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x00 3. "LOAD3,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x00 1. "LOAD1,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x03
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line.long 0x00 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x34++0x03
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line.long 0x00 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x38++0x03
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line.long 0x00 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x54++0x03
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line.long 0x00 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x58++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x5C++0x03
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line.long 0x00 "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x60++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x64++0x03
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line.long 0x00 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x70++0x03
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line.long 0x00 "EPWM_DTCTL0_1,EPWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x74++0x03
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line.long 0x00 "EPWM_DTCTL2_3,EPWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x78++0x03
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line.long 0x00 "EPWM_DTCTL4_5,EPWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x80++0x03
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line.long 0x00 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x94++0x03
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line.long 0x00 "EPWM_CNT1,EPWM Counter Register 1"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x98++0x03
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line.long 0x00 "EPWM_CNT2,EPWM Counter Register 2"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x9C++0x03
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line.long 0x00 "EPWM_CNT3,EPWM Counter Register 3"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA0++0x03
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line.long 0x00 "EPWM_CNT4,EPWM Counter Register 4"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA4++0x03
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line.long 0x00 "EPWM_CNT5,EPWM Counter Register 5"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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group.long 0xC0++0x03
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line.long 0x00 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
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group.long 0xC8++0x03
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line.long 0x00 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x03
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line.long 0x00 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x00 29. "CDTRGE5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 28. "CDTRGE4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 27. "CDTRGE3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 26. "CDTRGE2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 25. "CDTRGE1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 24. "CDTRGE0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 21. "CUTRGE5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 20. "CUTRGE4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 19. "CUTRGE3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 18. "CUTRGE2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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newline
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bitfld.long 0x00 17. "CUTRGE1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 16. "CUTRGE0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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newline
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bitfld.long 0x00 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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group.long 0xF8++0x03
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line.long 0x00 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0xFC++0x03
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line.long 0x00 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0x100++0x03
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line.long 0x00 "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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group.long 0x120++0x03
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line.long 0x00 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x00 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x00 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x03
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line.long 0x00 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x134++0x03
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line.long 0x00 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x138++0x03
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line.long 0x00 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x13C++0x03
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line.long 0x00 "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x140++0x03
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line.long 0x00 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x144++0x03
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line.long 0x00 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x150++0x03
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line.long 0x00 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x00 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x00 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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group.long 0x158++0x03
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line.long 0x00 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x00 5. "APDMAEN5,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 4. "APDMAEN4,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 3. "APDMAEN3,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 2. "APDMAEN2,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 1. "APDMAEN1,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 0. "APDMAEN0,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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group.long 0x200++0x03
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line.long 0x00 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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|
newline
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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|
bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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|
rgroup.long 0x208++0x03
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|
line.long 0x00 "EPWM_CAPSTS,EPWM Capture Status Register"
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|
bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
newline
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|
bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
newline
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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|
newline
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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rgroup.long 0x20C++0x03
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|
line.long 0x00 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
rgroup.long 0x210++0x03
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|
line.long 0x00 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x214++0x03
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line.long 0x00 "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x218++0x03
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|
line.long 0x00 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x21C++0x03
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line.long 0x00 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x220++0x03
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|
line.long 0x00 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x224++0x03
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line.long 0x00 "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x22C++0x03
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line.long 0x00 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x230++0x03
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line.long 0x00 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x234++0x03
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line.long 0x00 "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x238++0x03
|
|
line.long 0x00 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x23C++0x03
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line.long 0x00 "EPWM_PDMACTL,EPWM PDMA Control Register"
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bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT4/5,2: EPWM_FCAPDAT4/5,3: Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5"
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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|
newline
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT2/3,2: EPWM_FCAPDAT2/3,3: Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3"
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bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT0/1,2: EPWM_FCAPDAT0/1,3: Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1"
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bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
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|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x244++0x03
|
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line.long 0x00 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x248++0x03
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line.long 0x00 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x250++0x03
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line.long 0x00 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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group.long 0x254++0x03
|
|
line.long 0x00 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
|
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bitfld.long 0x00 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
|
|
line.long 0x00 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
|
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
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group.long 0x308++0x03
|
|
line.long 0x00 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
|
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
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group.long 0x30C++0x03
|
|
line.long 0x00 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EPWM_PBUF3,EPWM PERIOD3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF0_1,EPWM CLKPSC0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF2_3,EPWM CLKPSC2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF4_5,EPWM CLKPSC4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
|
|
bitfld.long 0x00 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
newline
|
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bitfld.long 0x00 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
tree.end
|
|
tree "EPWM0_NS"
|
|
base ad:0x50058000
|
|
group.long 0x00++0x03
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line.long 0x00 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects EPWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "EPWM_CTL1,EPWM Control Register 1"
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bitfld.long 0x00 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the..,1: The inversed state of pin SYNC is passed to.."
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN..,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CLKPSC0_1,EPWM Clock Prescale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_CLKPSC2_3,EPWM Clock Prescale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_CLKPSC4_5,EPWM Clock Prescale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 3. "LOAD3,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 1. "LOAD1,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x03
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line.long 0x00 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x34++0x03
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line.long 0x00 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x38++0x03
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line.long 0x00 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x54++0x03
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line.long 0x00 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x58++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x5C++0x03
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line.long 0x00 "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x60++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x64++0x03
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line.long 0x00 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x70++0x03
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line.long 0x00 "EPWM_DTCTL0_1,EPWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x74++0x03
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line.long 0x00 "EPWM_DTCTL2_3,EPWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x78++0x03
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line.long 0x00 "EPWM_DTCTL4_5,EPWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x80++0x03
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line.long 0x00 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x94++0x03
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line.long 0x00 "EPWM_CNT1,EPWM Counter Register 1"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x98++0x03
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line.long 0x00 "EPWM_CNT2,EPWM Counter Register 2"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x9C++0x03
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line.long 0x00 "EPWM_CNT3,EPWM Counter Register 3"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA0++0x03
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line.long 0x00 "EPWM_CNT4,EPWM Counter Register 4"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA4++0x03
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line.long 0x00 "EPWM_CNT5,EPWM Counter Register 5"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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group.long 0xC0++0x03
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line.long 0x00 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
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group.long 0xC8++0x03
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line.long 0x00 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x03
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line.long 0x00 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x00 29. "CDTRGE5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 28. "CDTRGE4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 27. "CDTRGE3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 26. "CDTRGE2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 25. "CDTRGE1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 24. "CDTRGE0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 21. "CUTRGE5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 20. "CUTRGE4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 19. "CUTRGE3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 18. "CUTRGE2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 17. "CUTRGE1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 16. "CUTRGE0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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group.long 0xF8++0x03
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line.long 0x00 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0xFC++0x03
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line.long 0x00 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0x100++0x03
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line.long 0x00 "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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group.long 0x120++0x03
|
|
line.long 0x00 "EPWM_STATUS,EPWM Status Register"
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|
bitfld.long 0x00 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x00 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x03
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line.long 0x00 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x134++0x03
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line.long 0x00 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x138++0x03
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line.long 0x00 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x13C++0x03
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line.long 0x00 "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x140++0x03
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line.long 0x00 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x144++0x03
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line.long 0x00 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x150++0x03
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line.long 0x00 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x00 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x00 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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group.long 0x158++0x03
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line.long 0x00 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x00 5. "APDMAEN5,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 4. "APDMAEN4,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 3. "APDMAEN3,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 2. "APDMAEN2,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 1. "APDMAEN1,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 0. "APDMAEN0,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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group.long 0x200++0x03
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line.long 0x00 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
|
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
|
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line.long 0x00 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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|
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
|
|
group.long 0x230++0x03
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line.long 0x00 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x234++0x03
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line.long 0x00 "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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|
group.long 0x238++0x03
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|
line.long 0x00 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x23C++0x03
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line.long 0x00 "EPWM_PDMACTL,EPWM PDMA Control Register"
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bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT4/5,2: EPWM_FCAPDAT4/5,3: Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5"
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT2/3,2: EPWM_FCAPDAT2/3,3: Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3"
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bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT0/1,2: EPWM_FCAPDAT0/1,3: Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1"
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bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0x03
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line.long 0x00 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x244++0x03
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line.long 0x00 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x248++0x03
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line.long 0x00 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x250++0x03
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line.long 0x00 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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group.long 0x254++0x03
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line.long 0x00 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
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line.long 0x00 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x308++0x03
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line.long 0x00 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x30C++0x03
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line.long 0x00 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x310++0x03
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line.long 0x00 "EPWM_PBUF3,EPWM PERIOD3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x314++0x03
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line.long 0x00 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x318++0x03
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line.long 0x00 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
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line.long 0x00 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x320++0x03
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line.long 0x00 "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x324++0x03
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line.long 0x00 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x328++0x03
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line.long 0x00 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
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line.long 0x00 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x330++0x03
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line.long 0x00 "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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rgroup.long 0x334++0x03
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line.long 0x00 "EPWM_CPSCBUF0_1,EPWM CLKPSC0_1 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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group.long 0x338++0x03
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line.long 0x00 "EPWM_CPSCBUF2_3,EPWM CLKPSC2_3 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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group.long 0x33C++0x03
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line.long 0x00 "EPWM_CPSCBUF4_5,EPWM CLKPSC4_5 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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rgroup.long 0x340++0x03
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line.long 0x00 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x344++0x03
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line.long 0x00 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x348++0x03
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line.long 0x00 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x34C++0x03
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line.long 0x00 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
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bitfld.long 0x00 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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newline
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bitfld.long 0x00 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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newline
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bitfld.long 0x00 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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tree.end
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tree "EPWM1"
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base ad:0x40059000
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group.long 0x00++0x03
|
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line.long 0x00 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects EPWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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newline
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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newline
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bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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|
bitfld.long 0x00 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
|
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
|
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line.long 0x00 "EPWM_CTL1,EPWM Control Register 1"
|
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bitfld.long 0x00 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
|
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bitfld.long 0x00 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the..,1: The inversed state of pin SYNC is passed to.."
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN..,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CLKPSC0_1,EPWM Clock Prescale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_CLKPSC2_3,EPWM Clock Prescale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_CLKPSC4_5,EPWM Clock Prescale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 3. "LOAD3,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 1. "LOAD1,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x03
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line.long 0x00 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x34++0x03
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line.long 0x00 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x38++0x03
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line.long 0x00 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x54++0x03
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line.long 0x00 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x58++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x5C++0x03
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line.long 0x00 "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x60++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x64++0x03
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line.long 0x00 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x70++0x03
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line.long 0x00 "EPWM_DTCTL0_1,EPWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x74++0x03
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line.long 0x00 "EPWM_DTCTL2_3,EPWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x78++0x03
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line.long 0x00 "EPWM_DTCTL4_5,EPWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x80++0x03
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line.long 0x00 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x94++0x03
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line.long 0x00 "EPWM_CNT1,EPWM Counter Register 1"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x98++0x03
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line.long 0x00 "EPWM_CNT2,EPWM Counter Register 2"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x9C++0x03
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line.long 0x00 "EPWM_CNT3,EPWM Counter Register 3"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA0++0x03
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line.long 0x00 "EPWM_CNT4,EPWM Counter Register 4"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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|
hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA4++0x03
|
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line.long 0x00 "EPWM_CNT5,EPWM Counter Register 5"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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|
hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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|
group.long 0xB0++0x03
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line.long 0x00 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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group.long 0xC0++0x03
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line.long 0x00 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
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group.long 0xC8++0x03
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line.long 0x00 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x03
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line.long 0x00 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x00 29. "CDTRGE5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 28. "CDTRGE4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 27. "CDTRGE3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 26. "CDTRGE2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 25. "CDTRGE1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 24. "CDTRGE0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 21. "CUTRGE5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 20. "CUTRGE4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 19. "CUTRGE3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 18. "CUTRGE2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 17. "CUTRGE1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 16. "CUTRGE0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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group.long 0xF8++0x03
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line.long 0x00 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0xFC++0x03
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line.long 0x00 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0x100++0x03
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line.long 0x00 "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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group.long 0x120++0x03
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line.long 0x00 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x00 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x00 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x03
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line.long 0x00 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x134++0x03
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line.long 0x00 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x138++0x03
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line.long 0x00 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x13C++0x03
|
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line.long 0x00 "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x140++0x03
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line.long 0x00 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x144++0x03
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line.long 0x00 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x150++0x03
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line.long 0x00 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x00 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x00 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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group.long 0x158++0x03
|
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line.long 0x00 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x00 5. "APDMAEN5,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 4. "APDMAEN4,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 3. "APDMAEN3,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 2. "APDMAEN2,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 1. "APDMAEN1,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 0. "APDMAEN0,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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group.long 0x200++0x03
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line.long 0x00 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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group.long 0x204++0x03
|
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line.long 0x00 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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newline
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x214++0x03
|
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line.long 0x00 "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x218++0x03
|
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line.long 0x00 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x21C++0x03
|
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line.long 0x00 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x230++0x03
|
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line.long 0x00 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x234++0x03
|
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line.long 0x00 "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x238++0x03
|
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line.long 0x00 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x23C++0x03
|
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line.long 0x00 "EPWM_PDMACTL,EPWM PDMA Control Register"
|
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bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT4/5,2: EPWM_FCAPDAT4/5,3: Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5"
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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|
bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT2/3,2: EPWM_FCAPDAT2/3,3: Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3"
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bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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|
bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT0/1,2: EPWM_FCAPDAT0/1,3: Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1"
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bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
|
|
group.long 0x250++0x03
|
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line.long 0x00 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
|
|
bitfld.long 0x00 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
|
|
bitfld.long 0x00 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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group.long 0x254++0x03
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line.long 0x00 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
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line.long 0x00 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x308++0x03
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line.long 0x00 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x30C++0x03
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line.long 0x00 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x310++0x03
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line.long 0x00 "EPWM_PBUF3,EPWM PERIOD3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x314++0x03
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line.long 0x00 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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group.long 0x318++0x03
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line.long 0x00 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0x31C++0x03
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line.long 0x00 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x320++0x03
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line.long 0x00 "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x324++0x03
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line.long 0x00 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x328++0x03
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line.long 0x00 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x32C++0x03
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line.long 0x00 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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group.long 0x330++0x03
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line.long 0x00 "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
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rgroup.long 0x334++0x03
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line.long 0x00 "EPWM_CPSCBUF0_1,EPWM CLKPSC0_1 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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group.long 0x338++0x03
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line.long 0x00 "EPWM_CPSCBUF2_3,EPWM CLKPSC2_3 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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group.long 0x33C++0x03
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line.long 0x00 "EPWM_CPSCBUF4_5,EPWM CLKPSC4_5 Buffer"
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
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rgroup.long 0x340++0x03
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line.long 0x00 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x344++0x03
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line.long 0x00 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x348++0x03
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line.long 0x00 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x34C++0x03
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line.long 0x00 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
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bitfld.long 0x00 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
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tree.end
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tree "EPWM1_NS"
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base ad:0x50059000
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group.long 0x00++0x03
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line.long 0x00 "EPWM_CTL0,EPWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nEPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects EPWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled EPWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each EPWM channel are..,1: Unify the EPWM_CH2 and EPWM_CH4 to output the.."
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.."
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bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD will load to PBUF at the end point of.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "EPWM_CTL1,EPWM Control Register 1"
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bitfld.long 0x00 26. "OUTMODE4,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 25. "OUTMODE2,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 24. "OUTMODE0,EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: EPWM independent mode,1: EPWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 20. "CNTMODE4,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 18. "CNTMODE2,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 17. "CNTMODE1,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 16. "CNTMODE0,EPWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 8.--9. "CNTTYPE4,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 4.--5. "CNTTYPE2,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 0.--1. "CNTTYPE0,EPWM Counter Behavior Type" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "EPWM_SYNC,EPWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 24. "PHSDIR0,EPWM Phase Direction Control" "0: Control EPWM counter count decrement after..,1: Control EPWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of pin SYNC is passed to the..,1: The inversed state of pin SYNC is passed to.."
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newline
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 16. "SNFLTEN,EPWM0_SYNC_IN Noise Filter Enable Bits" "0: Noise filter of input pin EPWM0_SYNC_IN..,1: Noise filter of input pin EPWM0_SYNC_IN Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 10.--11. "SINSRC2,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,EPWM0_SYNC_IN Source Selection" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to EPWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT will not be generated"
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newline
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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newline
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits" "0: EPWM counter disable to load PHS value,1: EPWM counter enable to load PHS value"
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group.long 0x0C++0x03
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line.long 0x00 "EPWM_SWSYNC,EPWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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newline
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0 SYNC_OUT source comes from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "EPWM_CLKSRC,EPWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,EPWM_CH45 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,EPWM_CH23 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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newline
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bitfld.long 0x00 0.--2. "ECLKSRC0,EPWM_CH01 External Clock Source Select" "0: EPWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..."
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group.long 0x14++0x03
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line.long 0x00 "EPWM_CLKPSC0_1,EPWM Clock Prescale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "EPWM_CLKPSC2_3,EPWM Clock Prescale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "EPWM_CLKPSC4_5,EPWM Clock Prescale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "EPWM_CNTEN,EPWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 4. "CNTEN4,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 3. "CNTEN3,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 2. "CNTEN2,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 1. "CNTEN1,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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bitfld.long 0x00 0. "CNTEN0,EPWM Counter Enable Bits" "0: EPWM Counter and clock prescaler stop running,1: EPWM Counter and clock prescaler start running"
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group.long 0x24++0x03
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line.long 0x00 "EPWM_CNTCLR,EPWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 4. "CNTCLR4,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 3. "CNTCLR3,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 2. "CNTCLR2,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 1. "CNTCLR1,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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bitfld.long 0x00 0. "CNTCLR0,Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit EPWM counter to 0000H"
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group.long 0x28++0x03
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line.long 0x00 "EPWM_LOAD,EPWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 3. "LOAD3,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 1. "LOAD1,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load EPWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write hardware clear when current EPWM period end.\nWrite Operation" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x03
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line.long 0x00 "EPWM_PERIOD0,EPWM Period Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x34++0x03
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line.long 0x00 "EPWM_PERIOD1,EPWM Period Register 1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x38++0x03
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line.long 0x00 "EPWM_PERIOD2,EPWM Period Register 2"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x3C++0x03
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line.long 0x00 "EPWM_PERIOD3,EPWM Period Register 3"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x40++0x03
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line.long 0x00 "EPWM_PERIOD4,EPWM Period Register 4"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x44++0x03
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line.long 0x00 "EPWM_PERIOD5,EPWM Period Register 5"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,EPWM Period Register\nUp-Count mode: \nIn this mode EPWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
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line.long 0x00 "EPWM_CMPDAT0,EPWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x54++0x03
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line.long 0x00 "EPWM_CMPDAT1,EPWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x58++0x03
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line.long 0x00 "EPWM_CMPDAT2,EPWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x5C++0x03
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line.long 0x00 "EPWM_CMPDAT3,EPWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x60++0x03
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line.long 0x00 "EPWM_CMPDAT4,EPWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x64++0x03
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line.long 0x00 "EPWM_CMPDAT5,EPWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMP,EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform interrupt and trigger EADC/DAC.\nIn independent mode CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x70++0x03
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line.long 0x00 "EPWM_DTCTL0_1,EPWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x74++0x03
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line.long 0x00 "EPWM_DTCTL2_3,EPWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x78++0x03
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line.long 0x00 "EPWM_DTCTL4_5,EPWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from EPWM_CLK,1: Dead-time clock source from prescaler output"
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for EPWM Pair (EPWM_CH0 EPWM_CH1) (EPWM_CH2 EPWM_CH3) (EPWM_CH4 EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected"
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group.long 0x80++0x03
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line.long 0x00 "EPWM_PHS0_1,EPWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "EPWM_PHS2_3,EPWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "EPWM_PHS4_5,EPWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "EPWM_CNT0,EPWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x94++0x03
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line.long 0x00 "EPWM_CNT1,EPWM Counter Register 1"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x98++0x03
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line.long 0x00 "EPWM_CNT2,EPWM Counter Register 2"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x9C++0x03
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line.long 0x00 "EPWM_CNT3,EPWM Counter Register 3"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA0++0x03
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line.long 0x00 "EPWM_CNT4,EPWM Counter Register 4"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA4++0x03
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line.long 0x00 "EPWM_CNT5,EPWM Counter Register 5"
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rbitfld.long 0x00 16. "DIRF,EPWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up"
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hexmask.long.word 0x00 0.--15. 1. "CNT,EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "EPWM_WGCTL0,EPWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type" "0: Do nothing,1: EPWM period (center) point output Low,2: EPWM period (center) point output High,3: EPWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0" "0: Do nothing,1: EPWM zero point output Low,2: EPWM zero point output High,3: EPWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "EPWM_WGCTL1,EPWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMPDAT.\nNote: In complementary mode CMPDCTL1 3 5 is used as another CMPDCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare down point output Low,2: EPWM compare down point output High,3: EPWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMPDAT.\nNote: In complementary mode CMPUCTL1 3 5 is used as another CMPUCTL for channel 0 2 4" "0: Do nothing,1: EPWM compare up point output Low,2: EPWM compare up point output High,3: EPWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "EPWM_MSKEN,EPWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled" "0: EPWM output signal is non-masked,1: EPWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "EPWM_MSK,EPWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 4. "MSKDAT4,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 3. "MSKDAT3,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 2. "MSKDAT2,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 1. "MSKDAT1,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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bitfld.long 0x00 0. "MSKDAT0,EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin if corresponding mask function is enabled" "0: Output logic low to EPWM channel n,1: Output logic high to EPWM channel n"
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group.long 0xC0++0x03
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line.long 0x00 "EPWM_BNF,EPWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor EPWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor EPWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,EPWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 1 Disabled,1: Noise filter of EPWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: brake pin event will be detected if EPWMx..,1: brake pin event will be detected if EPWMx.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,EPWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of EPWM Brake 0 Disabled,1: Noise filter of EPWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "EPWM_FAILBRK,EPWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.."
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group.long 0xC8++0x03
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line.long 0x00 "EPWM_BRKCTL0_1,EPWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "EPWM_BRKCTL2_3,EPWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "EPWM_BRKCTL4_5,EPWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "EADCLBEN,Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as level-detect brake source Disabled,1: EADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "EADCEBEN,Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EADCRM as edge-detect brake source Disabled,1: EADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect odd..,1: EPWM odd channel output tri-state when EPWMx..,2: EPWM odd channel output low level when EPWMx..,3: EPWM odd channel output high level when EPWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,EPWM Brake Action Select for Even Channel (Write Protect)\nNote: This bit is write protected" "0: EPWMx brake event will not affect even..,1: EPWM even channel output tri-state when EPWMx..,2: EPWM even channel output low level when EPWMx..,3: EPWM even channel output high level when.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as level-detect brake source..,1: EPWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as level-detect brake source..,1: EPWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE1 pin as edge-detect brake source..,1: EPWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: EPWMx_BRAKE0 pin as edge-detect brake source..,1: EPWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "EPWM_POLCTL,EPWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWM output" "0: EPWMx_CHn output polar inverse Disabled,1: EPWMx_CHn output polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "EPWM_POEN,EPWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,EPWM Pin Output Enable Bits" "0: EPWMx_CHn pin at tri-state,1: EPWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "EPWM_SWBRK,EPWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake and set BRKEIFn to 1 in EPWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "EPWM_INTEN0,EPWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "EPWM_INTEN1,EPWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "EPWM_INTSTS0,EPWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 28. "CMPDIF4,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 27. "CMPDIF3,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 26. "CMPDIF2,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 25. "CMPDIF1,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 24. "CMPDIF0,EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel.." "0,1"
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bitfld.long 0x00 21. "CMPUIF5,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1"
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bitfld.long 0x00 13. "PIF5,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 12. "PIF4,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 11. "PIF3,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 10. "PIF2,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 9. "PIF1,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 8. "PIF0,EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn" "0,1"
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bitfld.long 0x00 5. "ZIF5,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 4. "ZIF4,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 3. "ZIF3,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 2. "ZIF2,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 1. "ZIF1,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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bitfld.long 0x00 0. "ZIF0,EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "EPWM_INTSTS1,EPWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 28. "BRKLSTS4,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 27. "BRKLSTS3,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 26. "BRKLSTS2,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 25. "BRKLSTS1,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 24. "BRKLSTS0,EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n level-detect brake state is..,1: When EPWM channel n level-detect brake.."
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rbitfld.long 0x00 21. "BRKESTS5,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 20. "BRKESTS4,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 19. "BRKESTS3,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 18. "BRKESTS2,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 17. "BRKESTS1,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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rbitfld.long 0x00 16. "BRKESTS0,EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: EPWM channel n edge-detect brake state is..,1: When EPWM channel n edge-detect brake detects.."
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bitfld.long 0x00 13. "BRKLIF5,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 12. "BRKLIF4,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 11. "BRKLIF3,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 10. "BRKLIF2,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 9. "BRKLIF1,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 8. "BRKLIF0,EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n level-detect brake event do..,1: When EPWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: EPWM channel n edge-detect brake event do not..,1: When EPWM channel n edge-detect brake event.."
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group.long 0xF4++0x03
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line.long 0x00 "EPWM_DACTRGEN,EPWM Trigger DAC Enable Register"
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bitfld.long 0x00 29. "CDTRGE5,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 28. "CDTRGE4,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 27. "CDTRGE3,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 26. "CDTRGE2,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 25. "CDTRGE1,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 24. "CDTRGE0,EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2:.." "0: EPWM Compare Down count point trigger DAC..,1: EPWM Compare Down count point trigger DAC.."
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bitfld.long 0x00 21. "CUTRGE5,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 20. "CUTRGE4,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 19. "CUTRGE3,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 18. "CUTRGE2,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 17. "CUTRGE1,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 16. "CUTRGE0,EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMPDAT if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2:.." "0: EPWM Compare Up point trigger DAC function..,1: EPWM Compare Up point trigger DAC function.."
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bitfld.long 0x00 13. "PTE5,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 12. "PTE4,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 11. "PTE3,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 10. "PTE2,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 9. "PTE1,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 8. "PTE0,EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 5. "ZTE5,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 4. "ZTE4,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 3. "ZTE3,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 2. "ZTE2,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 1. "ZTE1,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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bitfld.long 0x00 0. "ZTE0,EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1" "0: EPWM period point trigger DAC function Disabled,1: EPWM period point trigger DAC function Enabled"
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group.long 0xF8++0x03
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line.long 0x00 "EPWM_EADCTS0,EPWM Trigger EADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,EPWM_CH3 Trigger EADC Enable Bit" "0: EPWM_CH3 Trigger EADC function Disabled,1: EPWM_CH3 Trigger EADC function Enabled"
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bitfld.long 0x00 24.--27. "TRGSEL3,EPWM_CH3 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 23. "TRGEN2,EPWM_CH2 Trigger EADC Enable Bit" "0: EPWM_CH2 Trigger EADC function Disabled,1: EPWM_CH2 Trigger EADC function Enabled"
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bitfld.long 0x00 16.--19. "TRGSEL2,EPWM_CH2 Trigger EADC Source Select" "0: EPWM_CH2 zero point,1: EPWM_CH2 period point,2: EPWM_CH2 zero or period point,3: EPWM_CH2 up-count compared point,4: EPWM_CH2 down-count compared point,5: EPWM_CH3 zero point,6: EPWM_CH3 period point,7: EPWM_CH3 zero or period point,8: EPWM_CH3 up-count compared point,9: EPWM_CH3 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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newline
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bitfld.long 0x00 15. "TRGEN1,EPWM_CH1 Trigger EADC Enable Bit" "0: EPWM_CH1 Trigger EADC function Disabled,1: EPWM_CH1 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL1,EPWM_CH1 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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newline
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bitfld.long 0x00 7. "TRGEN0,EPWM_CH0 Trigger EADC Enable Bit" "0: EPWM_CH0 Trigger EADC function Disabled,1: EPWM_CH0 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL0,EPWM_CH0 Trigger EADC Source Select" "0: EPWM_CH0 zero point,1: EPWM_CH0 period point,2: EPWM_CH0 zero or period point,3: EPWM_CH0 up-count compared point,4: EPWM_CH0 down-count compared point,5: EPWM_CH1 zero point,6: EPWM_CH1 period point,7: EPWM_CH1 zero or period point,8: EPWM_CH1 up-count compared point,9: EPWM_CH1 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0xFC++0x03
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line.long 0x00 "EPWM_EADCTS1,EPWM Trigger EADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,EPWM_CH5 Trigger EADC Enable Bit" "0: EPWM_CH5 Trigger EADC function Disabled,1: EPWM_CH5 Trigger EADC function Enabled"
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bitfld.long 0x00 8.--11. "TRGSEL5,EPWM_CH5 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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bitfld.long 0x00 7. "TRGEN4,EPWM_CH4 Trigger EADC Enable Bit" "0: EPWM_CH4 Trigger EADC function Disabled,1: EPWM_CH4 Trigger EADC function Enabled"
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bitfld.long 0x00 0.--3. "TRGSEL4,EPWM_CH4 Trigger EADC Source Select" "0: EPWM_CH4 zero point,1: EPWM_CH4 period point,2: EPWM_CH4 zero or period point,3: EPWM_CH4 up-count compared point,4: EPWM_CH4 down-count compared point,5: EPWM_CH5 zero point,6: EPWM_CH5 period point,7: EPWM_CH5 zero or period point,8: EPWM_CH5 up-count compared point,9: EPWM_CH5 down-count compared point,10: EPWM_CH0 up-count free trigger compared point,11: EPWM_CH0 down-count free trigger compared..,12: EPWM_CH2 up-count free trigger compared point,13: EPWM_CH2 down-count free trigger compared..,14: EPWM_CH4 up-count free trigger compared point,15: EPWM_CH4 down-count free trigger compared.."
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group.long 0x100++0x03
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line.long 0x00 "EPWM_FTCMPDAT0_1,EPWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "EPWM_FTCMPDAT2_3,EPWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "EPWM_FTCMPDAT4_5,EPWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,EPWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "EPWM_SSCTL,EPWM Synchronous Start Control Register"
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bitfld.long 0x00 8.--9. "SSRC,EPWM Synchronous Start Source Select Bits" "0: Synchronous start source come from EPWM0,1: Synchronous start source come from EPWM1,2: Synchronous start source come from BPWM0,3: Synchronous start source come from BPWM1"
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bitfld.long 0x00 5. "SSEN5,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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bitfld.long 0x00 0. "SSEN0,EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN)" "0: EPWM synchronous start function Disabled,1: EPWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "EPWM_SSTRG,EPWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "EPWM_LEBCTL,EPWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,EPWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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newline
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bitfld.long 0x00 9. "SRCEN2,EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit" "0: EPWM Leading Edge Blanking Source from..,1: EPWM Leading Edge Blanking Source from.."
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newline
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bitfld.long 0x00 0. "LEBEN,EPWM Leading Edge Blanking Enable Bit" "0: EPWM Leading Edge Blanking Disabled,1: EPWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "EPWM_LEBCNT,EPWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,EPWM Leading Edge Blanking Counter"
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group.long 0x120++0x03
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line.long 0x00 "EPWM_STATUS,EPWM Status Register"
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bitfld.long 0x00 24. "DACTRGF,DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No DAC start of conversion trigger event has..,1: A DAC start of conversion trigger event has.."
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bitfld.long 0x00 21. "EADCTRGF5,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 20. "EADCTRGF4,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 19. "EADCTRGF3,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 18. "EADCTRGF2,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 17. "EADCTRGF1,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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newline
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bitfld.long 0x00 16. "EADCTRGF0,EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1" "0: No EADC start of conversion trigger event has..,1: An EADC start of conversion trigger event has.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1" "0: No SYNC_IN event has occurred,1: A SYNC_IN event has occurred"
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value"
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group.long 0x130++0x03
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line.long 0x00 "EPWM_IFA0,EPWM Interrupt Flag Accumulator Register 0"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x134++0x03
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line.long 0x00 "EPWM_IFA1,EPWM Interrupt Flag Accumulator Register 1"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x138++0x03
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line.long 0x00 "EPWM_IFA2,EPWM Interrupt Flag Accumulator Register 2"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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newline
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x13C++0x03
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line.long 0x00 "EPWM_IFA3,EPWM Interrupt Flag Accumulator Register 3"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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newline
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x140++0x03
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line.long 0x00 "EPWM_IFA4,EPWM Interrupt Flag Accumulator Register 4"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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newline
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x144++0x03
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line.long 0x00 "EPWM_IFA5,EPWM Interrupt Flag Accumulator Register 5"
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bitfld.long 0x00 31. "IFAEN,EPWM_CHn Interrupt Flag Accumulator Enable Bits" "0: EPWM_CHn interrupt flag accumulator Disabled,1: EPWM_CHn interrupt flag accumulator Enabled"
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bitfld.long 0x00 28.--29. "IFASEL," "?,1: EPWM_CHn period in channel n,2: EPWM_CHn up-count compared point,3: EPWM_CHn down-count compared point"
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hexmask.long.word 0x00 0.--15. 1. "IFACNT,EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period"
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group.long 0x150++0x03
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line.long 0x00 "EPWM_AINTSTS,EPWM Accumulator Interrupt Flag Register"
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bitfld.long 0x00 5. "IFAIF5,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 4. "IFAIF4,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 3. "IFAIF3,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 2. "IFAIF2,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 1. "IFAIF1,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "IFAIF0,EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register software can clear this bit by writing 1 to it" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "EPWM_AINTEN,EPWM Accumulator Interrupt Enable Register"
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bitfld.long 0x00 5. "IFAIEN5,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 4. "IFAIEN4,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 3. "IFAIEN3,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 2. "IFAIEN2,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 1. "IFAIEN1,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 0. "IFAIEN0,EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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group.long 0x158++0x03
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line.long 0x00 "EPWM_APDMACTL,EPWM Accumulator PDMA Control Register"
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bitfld.long 0x00 5. "APDMAEN5,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 4. "APDMAEN4,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 3. "APDMAEN3,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 2. "APDMAEN2,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 1. "APDMAEN1,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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bitfld.long 0x00 0. "APDMAEN0,Channel N Accumulator PDMA Enable Bits" "0: Channel n PDMA function Disabled,1: Channel n PDMA function Enabled for the.."
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group.long 0x200++0x03
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line.long 0x00 "EPWM_CAPINEN,EPWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: EPWM Channel capture input path Disabled,1: EPWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "EPWM_CAPCTL,EPWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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newline
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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newline
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "EPWM_CAPSTS,EPWM Capture Status Register"
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bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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newline
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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newline
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1"
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newline
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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newline
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "EPWM_RCAPDAT0,EPWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "EPWM_FCAPDAT0,EPWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "EPWM_RCAPDAT1,EPWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "EPWM_FCAPDAT1,EPWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "EPWM_RCAPDAT2,EPWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "EPWM_FCAPDAT2,EPWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "EPWM_RCAPDAT3,EPWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "EPWM_FCAPDAT3,EPWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "EPWM_RCAPDAT4,EPWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "EPWM_FCAPDAT4,EPWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "EPWM_RCAPDAT5,EPWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "EPWM_FCAPDAT5,EPWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the EPWM counter value will be saved in this register"
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group.long 0x23C++0x03
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line.long 0x00 "EPWM_PDMACTL,EPWM PDMA Control Register"
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bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order" "0: EPWM_FCAPDAT4/5 is the first captured data to..,1: EPWM_RCAPDAT4/5 is the first captured data to.."
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newline
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT4/5,2: EPWM_FCAPDAT4/5,3: Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5"
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order" "0: EPWM_FCAPDAT2/3 is the first captured data to..,1: EPWM_RCAPDAT2/3 is the first captured data to.."
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newline
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT2/3,2: EPWM_FCAPDAT2/3,3: Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3"
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bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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newline
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order" "0: EPWM_FCAPDAT0/1 is the first captured data to..,1: EPWM_RCAPDAT0/1 is the first captured data to.."
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newline
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: EPWM_RCAPDAT0/1,2: EPWM_FCAPDAT0/1,3: Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1"
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bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0x03
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line.long 0x00 "EPWM_PDMACAP0_1,EPWM Capture Channel 01 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x244++0x03
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line.long 0x00 "EPWM_PDMACAP2_3,EPWM Capture Channel 23 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x248++0x03
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line.long 0x00 "EPWM_PDMACAP4_5,EPWM Capture Channel 45 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA"
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group.long 0x250++0x03
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line.long 0x00 "EPWM_CAPIEN,EPWM Capture Interrupt Enable Register"
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bitfld.long 0x00 13. "CAPFIEN5,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 12. "CAPFIEN4,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 11. "CAPFIEN3,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 10. "CAPFIEN2,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 9. "CAPFIEN1,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 8. "CAPFIEN0,EPWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 5. "CAPRIEN5,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 4. "CAPRIEN4,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 3. "CAPRIEN3,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 2. "CAPRIEN2,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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newline
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bitfld.long 0x00 1. "CAPRIEN1,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 0. "CAPRIEN0,EPWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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group.long 0x254++0x03
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line.long 0x00 "EPWM_CAPIF,EPWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CFLIF5,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CFLIF4,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 11. "CFLIF3,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CFLIF2,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 9. "CFLIF1,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CFLIF0,EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x00 5. "CRLIF5,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CRLIF4,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 3. "CRLIF3,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CRLIF2,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x00 1. "CRLIF1,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 0. "CRLIF0,EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x03
|
|
line.long 0x00 "EPWM_PBUF0,EPWM PERIOD0 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EPWM_PBUF1,EPWM PERIOD1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "EPWM_PBUF2,EPWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EPWM_PBUF3,EPWM PERIOD3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "EPWM_PBUF4,EPWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EPWM_PBUF5,EPWM PERIOD5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF0,EPWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EPWM_CMPBUF1,EPWM CMPDAT1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "EPWM_CMPBUF2,EPWM CMPDAT2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EPWM_CMPBUF3,EPWM CMPDAT3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "EPWM_CMPBUF4,EPWM CMPDAT4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EPWM_CMPBUF5,EPWM CMPDAT5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register"
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF0_1,EPWM CLKPSC0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF2_3,EPWM CLKPSC2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "EPWM_CPSCBUF4_5,EPWM CLKPSC4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register"
|
|
rgroup.long 0x340++0x03
|
|
line.long 0x00 "EPWM_FTCBUF0_1,EPWM FTCMPDAT0_1 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "EPWM_FTCBUF2_3,EPWM FTCMPDAT2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EPWM_FTCBUF4_5,EPWM FTCMPDAT4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "EPWM_FTCI,EPWM FTCMPDAT Indicator Register"
|
|
bitfld.long 0x00 10. "FTCMD4,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 9. "FTCMD2,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "FTCMD0,EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 2. "FTCMU4,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FTCMU2,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
bitfld.long 0x00 0. "FTCMU0,EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn software can clear this bit by writing 1 to it" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FMC"
|
|
base ad:0x4000C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x00 24. "INTEN,ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected" "0: ISP INT Disabled,1: ISP INT Enabled"
|
|
bitfld.long 0x00 16. "BL,Boot Loader Booting (Write Protect)\nThis bit is initiated with the inversed value of MBS (CONFIG0[5])" "0: Boot from APROM or LDROM,1: Boot from Boot Loader"
|
|
newline
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself.." "0,1"
|
|
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: LDROM cannot be updated,1: LDROM can be updated"
|
|
newline
|
|
bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: CONFIG cannot be updated,1: CONFIG can be updated"
|
|
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
|
|
newline
|
|
bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nWhen MBS in CONFIG0 is 1 set/clear this bit to select next booting from LDROM/APROM respectively" "0: Boot from APROM when MBS (CONFIG0[5]) is 1,1: Boot from LDROM when MBS (CONFIG0[5]) is 1"
|
|
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe M2351 series is equipped with embedded Flash"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FMC_ISPCMD,ISP Command Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP Command\nISP command table is shown below:\nThe other commands are invalid"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nNote: This bit is write protected" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FMC_ISPSTS,ISP Status Register"
|
|
bitfld.long 0x00 24. "INTFLAG," "0: ISP not finished,1: ISP done or ISPFF set"
|
|
hexmask.long.word 0x00 9.--23. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0] 9'h000} ~ {VECMAP[14:0] 9'h1FF}"
|
|
newline
|
|
bitfld.long 0x00 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash.."
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 5. "PGFF,Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification" "0: Flash Program is success,1: Flash Program is fail"
|
|
rbitfld.long 0x00 4. "FCYCDIS,Flash Access Cycle Auto-tuning Disable Flag (Read Only)\nThis bit is set if Flash access cycle auto-tunning function is disabled" "0: Flash access cycle auto-tuning Enabled,1: Flash access cyle auto-tuning Disabled"
|
|
newline
|
|
rbitfld.long 0x00 3. "MBS,Boot From Boot Loader Selection Flag (Read Only)\nThis bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened" "0: Boot from Boot Loader,1: Boot from LDROM/APROM.(.see CBS bit setting)"
|
|
rbitfld.long 0x00 2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened" "0: LDROM with IAP mode,1: APROM with IAP mode"
|
|
newline
|
|
rbitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FMC_CYCCTL,Flash Access Cycle Control Register"
|
|
bitfld.long 0x00 8. "FADIS,Flash Access Cycle Auto-tuning Disable Bit (Write Protect)\nSet this bit to disable Flash access cycle auto-tuning function\nNote: This bit is write protected" "0: Flash access cycle auto-tuning Enabled,1: Flash access cycle auto-tuning Disabled"
|
|
bitfld.long 0x00 0.--3. "CYCLE,Flash Access Cycle Control (Write Protect)\nThis register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0 and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).When auto-tuning function.." "0: CPU access with zero wait cycle Flash access..,1: CPU access with one wait cycle if cache miss..,2: CPU access with two wait cycles if cache miss..,3: CPU access with three wait cycles if cache..,?..."
|
|
wgroup.long 0x50++0x03
|
|
line.long 0x00 "FMC_KPKEY0,KPROM KEY0 Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "KPKEY0,KPROM KEY0 Data (Write Only)\nWrite KPKEY0 data to this register before KEY Comparison operation"
|
|
wgroup.long 0x54++0x03
|
|
line.long 0x00 "FMC_KPKEY1,KPROM KEY1 Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "KPKEY1,KPROM KEY1 Data (Write Only)\nWrite KPKEY1 data to this register before KEY Comparison operation"
|
|
wgroup.long 0x58++0x03
|
|
line.long 0x00 "FMC_KPKEY2,KPROM KEY2 Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "KPKEY2,KPROM KEY2 Data (Write Only)\nWrite KPKEY2 data to this register before KEY Comparison operation"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "FMC_KPKEYTRG,KPROM KEY Comparison Trigger Control Register"
|
|
bitfld.long 0x00 1. "TCEN,Timeout Counting Enable Bit (Write Protect)\n10 minutes is at least for timeout and average is about 20 minutes.\nNote: This bit is write-protected" "0: Timeout counting Disabled,1: Timeout counting Enabled if input key is.."
|
|
bitfld.long 0x00 0. "KPKEYGO,KPROM KEY Comparison Start Trigger (Write Protect)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished" "0: KEY comparison operation is finished,1: KEY comparison is progressed"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FMC_KPKEYSTS,KPROM KEY Comparison Status Register"
|
|
rbitfld.long 0x00 5. "CFGFLAG,CONFIG Write-protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset" "0: CONFIG write-protection Disabled,1: CONFIG write-protection Enabled"
|
|
rbitfld.long 0x00 4. "KEYFLAG,KEY Protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset" "0: Security Key protection Disabled,1: Security Key protection Enabled"
|
|
newline
|
|
rbitfld.long 0x00 3. "FORBID,KEY Comparison Forbidden Flag (Read Only)\nThis bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8])" "0: KEY comparison is not forbidden,1: KEY comparison is forbidden KEYGO (FMC_KEYTRG.."
|
|
rbitfld.long 0x00 2. "KEYMATCH,KEY Match Flag (Read Only)\nThis bit is set to 1 after KEY comparison complete if the KEY0 KEY1 and KEY2 are matched with the 96-bit security keys in KPROM and cleared to 0 if KEYs are unmatched" "0: KEY0 KEY1 and KEY2 are unmatched with the..,1: KEY0 KEY1 and KEY2 are matched with the KPROM.."
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|
newline
|
|
bitfld.long 0x00 1. "KEYLOCK,KEY LOCK Flag \nThis bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection" "0: KPROM LDROM and APROM is not in write..,1: KPROM LDROM and APROM is in write protection"
|
|
rbitfld.long 0x00 0. "KEYBUSY,KEY Comparison Busy (Read Only)" "0: KEY comparison is finished,1: KEY comparison is busy"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "FMC_KPKEYCNT,KPROM KEY-unmatched Counting Register"
|
|
bitfld.long 0x00 8.--13. "KPKEMAX,Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKPKEMAX is the maximum error key entry number at each power-on" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "KPKECNT,Error Key Entry Counter at Each Power-on (Read Only)\nKPKECNT is increased when entry keys is wrong in Security Key protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "FMC_KPCNT,KPROM KEY-unmatched Power-on Counting Register"
|
|
bitfld.long 0x00 8.--11. "KPMAX,Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "KPCNT,Power-on Counter for Error Key Entry (Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FMC_MPDAT0,ISP Data0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FMC_MPDAT1,ISP Data1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FMC_MPDAT2,ISP Data2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FMC_MPDAT3,ISP Data3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "FMC_MPSTS,ISP Multi-program Status Register"
|
|
bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
|
|
bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
|
|
newline
|
|
bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
|
|
bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_MPDAT0 register has been written and not.."
|
|
newline
|
|
bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
|
|
bitfld.long 0x00 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
|
|
newline
|
|
bitfld.long 0x00 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "FMC_MPADDR,ISP Multi-program Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "FMC_XOMR0STS,XOM Region 0 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0"
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "FMC_XOMR1STS,XOM Region 1 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 1 Base Address (Page-aligned)\nBASE is the base address of XOM Region 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 1 Size (Page-aligned)\nSIZE is the page number of XOM Region 1"
|
|
rgroup.long 0xD8++0x03
|
|
line.long 0x00 "FMC_XOMR2STS,XOM Region 2 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 2 Base Address (Page-aligned)\nBASE is the base address of XOM Region 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 2 Size (Page-aligned)\nSIZE is the page number of XOM Region 2"
|
|
rgroup.long 0xDC++0x03
|
|
line.long 0x00 "FMC_XOMR3STS,XOM Region 3 Status Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BASE,XOM Region 3 Base Address (Page-aligned)\nBASE is the base address of XOM Region 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SIZE,XOM Region 3 Size (Page-aligned)\nSIZE is the page number of XOM Region 3"
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "FMC_XOMSTS,XOM Status Register"
|
|
bitfld.long 0x00 4. "XOMPEF,XOM Page Erase Function Fail\nXOM page erase function status" "0: Sucess,1: Fail"
|
|
bitfld.long 0x00 3. "XOMR3ON,XOM Region 3 On\nXOM Region 3 active status" "0: No active,1: XOM region 3 is active"
|
|
newline
|
|
bitfld.long 0x00 2. "XOMR2ON,XOM Region 2 On\nXOM Region 2 active status" "0: No active,1: XOM region 2 is active"
|
|
bitfld.long 0x00 1. "XOMR1ON,XOM Region 1 On\nXOM Region 1 active status" "0: No active,1: XOM region 1 is active"
|
|
newline
|
|
bitfld.long 0x00 0. "XOMR0ON,XOM Region 0 On\nXOM Region 0 active status" "0: No active,1: XOM region 0 is active"
|
|
tree.end
|
|
tree "GPIO"
|
|
tree "GPIOA"
|
|
base ad:0x40004000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA_MODE,PA I/O Mode Control"
|
|
bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PA_PUSEL,PA Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PA_DBCTL,PA Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOA_NS"
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base ad:0x50004000
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group.long 0x00++0x03
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line.long 0x00 "PA_MODE,PA I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PA_PUSEL,PA Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PA_DBCTL,PA Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOB"
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base ad:0x40004040
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group.long 0x00++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PB_DBCTL,PB Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOB_NS"
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base ad:0x50004040
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group.long 0x00++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PB_PUSEL,PB Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PB_DBCTL,PB Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOC"
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base ad:0x40004080
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group.long 0x00++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PC_DBCTL,PC Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOC_NS"
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base ad:0x50004080
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group.long 0x00++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PC_PUSEL,PC Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PC_DBCTL,PC Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOD"
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base ad:0x400040C0
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group.long 0x00++0x03
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line.long 0x00 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PD_PIN,PD Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PD_DBEN,PD De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PD_SLEWCTL,PD High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PD_PUSEL,PD Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PD_DBCTL,PD Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOD_NS"
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base ad:0x500040C0
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group.long 0x00++0x03
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line.long 0x00 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PD_PIN,PD Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PD_DBEN,PD De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PD_SLEWCTL,PD High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PD_PUSEL,PD Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PD_DBCTL,PD Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOE"
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base ad:0x40004100
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group.long 0x00++0x03
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line.long 0x00 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PE_PIN,PE Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PE_DBEN,PE De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PE_INTEN,PE Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PE_SLEWCTL,PE High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PE_PUSEL,PE Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PE_DBCTL,PE Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOE_NS"
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base ad:0x50004100
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group.long 0x00++0x03
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line.long 0x00 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PE_PIN,PE Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PE_DBEN,PE De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PE_INTEN,PE Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PE_SMTEN,PE Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PE_SLEWCTL,PE High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PE_PUSEL,PE Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PE_DBCTL,PE Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOF"
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base ad:0x40004140
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group.long 0x00++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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newline
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PF_DBCTL,PF Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOF_NS"
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base ad:0x50004140
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group.long 0x00++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PF_DBEN,PF De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PF_PUSEL,PF Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PF_DBCTL,PF Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOG"
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base ad:0x40004180
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group.long 0x00++0x03
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line.long 0x00 "PG_MODE,PG I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PG_DINOFF,PG Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PG_DOUT,PG Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PG_DATMSK,PG Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PG_PIN,PG Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PG_DBEN,PG De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PG_INTTYPE,PG Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PG_INTEN,PG Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PG_INTSRC,PG Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PG_SMTEN,PG Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PG_SLEWCTL,PG High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PG_PUSEL,PG Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PG_DBCTL,PG Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOG_NS"
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base ad:0x50004180
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group.long 0x00++0x03
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line.long 0x00 "PG_MODE,PG I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PG_DINOFF,PG Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PG_DOUT,PG Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PG_DATMSK,PG Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PG_PIN,PG Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PG_DBEN,PG De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PG_INTTYPE,PG Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PG_INTEN,PG Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PG_INTSRC,PG Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PG_SMTEN,PG Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PG_SLEWCTL,PG High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PG_PUSEL,PG Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PG_DBCTL,PG Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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newline
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOH"
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base ad:0x400041C0
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group.long 0x00++0x03
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line.long 0x00 "PH_MODE,PH I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PH_DINOFF,PH Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PH_DOUT,PH Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PH_DATMSK,PH Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PH_PIN,PH Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PH_DBEN,PH De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PH_INTTYPE,PH Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PH_INTEN,PH Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PH_INTSRC,PH Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PH_SMTEN,PH Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PH_SLEWCTL,PH High Slew Rate Control Register"
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bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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group.long 0x30++0x03
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line.long 0x00 "PH_PUSEL,PH Pull-up and Pull-down Selection Register"
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bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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group.long 0x34++0x03
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line.long 0x00 "PH_DBCTL,PH Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
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tree "GPIOH_NS"
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base ad:0x500041C0
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group.long 0x00++0x03
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line.long 0x00 "PH_MODE,PH I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-h I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins" "0: Px.n is in Input mode (tri-state),1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PH_DINOFF,PH Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-h Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PH_DOUT,PH Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-h Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PH_DATMSK,PH Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-h Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PH_PIN,PH Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-h Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PH_DBEN,PH De-bounce Enable Control Register"
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bitfld.long 0x00 15. "DBEN15,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-h Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PH_INTTYPE,PH Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-h Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PH_INTEN,PH Interrupt Enable Control Register"
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bitfld.long 0x00 31. "RHIEN15,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port A-h Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-h Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PH_INTSRC,PH Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-h Pin[n] Interrupt Source Flag\nWrite Operation" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PH_SMTEN,PH Input Schmitt Trigger Enable Register"
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bitfld.long 0x00 15. "SMTEN15,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 3. "SMTEN3,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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|
bitfld.long 0x00 2. "SMTEN2,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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|
newline
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bitfld.long 0x00 1. "SMTEN1,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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|
bitfld.long 0x00 0. "SMTEN0,Port A-h Pin[n] Input Schmitt Trigger Enable Bit" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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|
group.long 0x28++0x03
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|
line.long 0x00 "PH_SLEWCTL,PH High Slew Rate Control Register"
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|
bitfld.long 0x00 30.--31. "HSREN15,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 28.--29. "HSREN14,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 26.--27. "HSREN13,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
bitfld.long 0x00 24.--25. "HSREN12,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 22.--23. "HSREN11,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 20.--21. "HSREN10,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 18.--19. "HSREN9,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 16.--17. "HSREN8,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
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bitfld.long 0x00 14.--15. "HSREN7,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 12.--13. "HSREN6,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 10.--11. "HSREN5,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 8.--9. "HSREN4,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 6.--7. "HSREN3,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 4.--5. "HSREN2,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
newline
|
|
bitfld.long 0x00 2.--3. "HSREN1,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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bitfld.long 0x00 0.--1. "HSREN0,Port A-h Pin[n] High Slew Rate Control" "0: Px.n output with normal slew rate mode..,1: Px.n output with high slew rate mode (maximum..,2: Px.n output with fast slew rate mode (maximum..,3: Reserved"
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|
group.long 0x30++0x03
|
|
line.long 0x00 "PH_PUSEL,PH Pull-up and Pull-down Selection Register"
|
|
bitfld.long 0x00 30.--31. "PUSEL15,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 28.--29. "PUSEL14,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 26.--27. "PUSEL13,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 24.--25. "PUSEL12,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 22.--23. "PUSEL11,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 20.--21. "PUSEL10,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 18.--19. "PUSEL9,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 16.--17. "PUSEL8,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 14.--15. "PUSEL7,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 12.--13. "PUSEL6,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 10.--11. "PUSEL5,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 8.--9. "PUSEL4,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
newline
|
|
bitfld.long 0x00 6.--7. "PUSEL3,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
bitfld.long 0x00 4.--5. "PUSEL2,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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newline
|
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bitfld.long 0x00 2.--3. "PUSEL1,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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bitfld.long 0x00 0.--1. "PUSEL0,Port A-h Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins" "0: Px.n pull-up and pull-down disable,1: Px.n pull-up enable,2: Px.n pull-down enable,3: Px.n pull-up and pull-down disable"
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|
group.long 0x34++0x03
|
|
line.long 0x00 "PH_DBCTL,PH Interrupt De-bounce Control Register"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 10 kHz.."
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|
newline
|
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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tree.end
|
|
tree "PA"
|
|
base ad:0x40004800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
group.long 0x04++0x03
|
|
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
group.long 0x0C++0x03
|
|
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PA_NS"
|
|
base ad:0x50004800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PB"
|
|
base ad:0x40004840
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PB_NS"
|
|
base ad:0x50004840
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PC"
|
|
base ad:0x40004880
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PC_NS"
|
|
base ad:0x50004880
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PD"
|
|
base ad:0x400048C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PD_NS"
|
|
base ad:0x500048C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PE"
|
|
base ad:0x40004900
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PE_NS"
|
|
base ad:0x50004900
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PE14_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PE15_PDIO,GPIO PE.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PF"
|
|
base ad:0x40004940
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PF_NS"
|
|
base ad:0x50004940
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PF8_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PF9_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PF10_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PF11_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PF12_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PF13_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PF14_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PF15_PDIO,GPIO PF.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PG"
|
|
base ad:0x40004980
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PG0_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PG1_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PG2_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PG3_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PG4_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PG5_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PG6_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PG7_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PG8_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PG9_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PG10_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PG11_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PG12_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PG13_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PG14_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PG15_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PG_NS"
|
|
base ad:0x50004980
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PG0_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PG1_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PG2_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PG3_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PG4_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PG5_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PG6_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PG7_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PG8_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PG9_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PG10_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PG11_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PG12_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PG13_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PG14_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PG15_PDIO,GPIO PG.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PH"
|
|
base ad:0x400049C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PH0_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PH1_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PH2_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PH3_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PH12_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PH13_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PH14_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PH15_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree "PH_NS"
|
|
base ad:0x500049C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PH0_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PH1_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PH2_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PH3_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PH4_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PH5_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PH6_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PH7_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PH8_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PH9_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PH10_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PH11_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PH12_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PH13_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PH14_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PH15_PDIO,GPIO PH.n Pin Data Input/Output Register"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C"
|
|
tree "I2C0"
|
|
base ad:0x40080000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
|
|
bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
|
|
bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
|
|
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
|
|
newline
|
|
bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
|
|
bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
|
|
newline
|
|
bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
|
|
bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
|
|
newline
|
|
bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
|
|
bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
|
|
newline
|
|
bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
|
|
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
|
|
bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
|
|
bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
|
|
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
|
|
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
|
|
bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
|
|
bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
|
|
bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
|
|
bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
|
|
newline
|
|
bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
|
|
bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
|
|
tree.end
|
|
tree "I2C0_NS"
|
|
base ad:0x50080000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
|
|
bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
|
|
bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
|
|
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
|
|
newline
|
|
bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
|
|
bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
|
|
newline
|
|
bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
|
|
bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
|
|
newline
|
|
bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
|
|
bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
|
|
newline
|
|
bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
|
|
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
|
|
bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
|
|
bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
|
|
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
|
|
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
|
|
bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
|
|
bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
|
|
bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
|
|
bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
|
|
newline
|
|
bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
|
|
bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x40081000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
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group.long 0x4C++0x03
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line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
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hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
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group.long 0x50++0x03
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line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
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bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
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bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
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bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
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group.long 0x54++0x03
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line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
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bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
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bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
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newline
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bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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group.long 0x58++0x03
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line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
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bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
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bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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newline
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bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
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group.long 0x5C++0x03
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line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
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rgroup.long 0x60++0x03
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line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x03
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line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
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group.long 0x68++0x03
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line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
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tree.end
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tree "I2C1_NS"
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base ad:0x50081000
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group.long 0x00++0x03
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line.long 0x00 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
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bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
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newline
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bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
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bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
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bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x08++0x03
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line.long 0x00 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
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rgroup.long 0x0C++0x03
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line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x03
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line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
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group.long 0x14++0x03
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line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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newline
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bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
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group.long 0x18++0x03
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line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
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bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x1C++0x03
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line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
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bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x20++0x03
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line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
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bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x24++0x03
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line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
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group.long 0x28++0x03
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line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
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group.long 0x2C++0x03
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line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
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group.long 0x30++0x03
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line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
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group.long 0x3C++0x03
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line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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group.long 0x40++0x03
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line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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newline
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bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
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group.long 0x44++0x03
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line.long 0x00 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
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newline
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
|
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bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x48++0x03
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line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
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newline
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bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
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bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
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newline
|
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bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
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group.long 0x4C++0x03
|
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line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
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hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
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hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
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group.long 0x50++0x03
|
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line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
|
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bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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newline
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bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
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|
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
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newline
|
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bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
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bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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newline
|
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bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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newline
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bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
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newline
|
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bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
|
|
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
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newline
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bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
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group.long 0x54++0x03
|
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line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
|
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bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
|
|
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
|
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newline
|
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bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
|
|
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
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newline
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bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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group.long 0x58++0x03
|
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line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
|
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bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
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bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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|
newline
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bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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newline
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bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
|
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bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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|
newline
|
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bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
|
|
bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40082000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
|
|
bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
|
|
bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
|
|
bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
|
|
newline
|
|
bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
|
|
bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
|
|
newline
|
|
bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
|
|
bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
|
|
newline
|
|
bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
|
|
bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
|
|
newline
|
|
bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
|
|
bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
|
|
bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
|
|
bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
|
|
bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
|
|
bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
|
|
bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
|
|
bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
|
|
bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
|
|
bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
|
|
newline
|
|
bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
|
|
bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
|
|
tree.end
|
|
tree "I2C2_NS"
|
|
base ad:0x50082000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL0,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS0,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen enabled the 14-bit time-out counter will start counting when SI is cleared" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen enabled the time-out period is extended 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
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line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x00 1.--10. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
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group.long 0x3C++0x03
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line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received" "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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group.long 0x40++0x03
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line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
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bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
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group.long 0x44++0x03
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line.long 0x00 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x00 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x48++0x03
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line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0x00 8. "ONBUSY,On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 3. "ADMAT3,I2C Address 3 Match Status\nWhen address 3 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 2. "ADMAT2,I2C Address 2 Match Status\nWhen address 2 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 1. "ADMAT1,I2C Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 0. "ADMAT0,I2C Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
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group.long 0x4C++0x03
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line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode"
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hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs"
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group.long 0x50++0x03
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line.long 0x00 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x00 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x00 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x00 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x00 10. "PECCLR,PEC Clear at Repeat START\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected" "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
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bitfld.long 0x00 9. "TIDLE,Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle" "0: BUSTOUT is used to calculate the clock low..,1: BUSTOUT is used to calculate the IDLE period.."
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bitfld.long 0x00 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x00 7. "BUSEN,BUS Enable Bit\nNote: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition" "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x00 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x00 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x00 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x00 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x00 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable,1: Device default address Enabled"
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bitfld.long 0x00 1. "PECEN,Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode the bit should be enabled after wake-up if needed PEC calculation" "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x00 0. "ACKMEN,Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit" "0: Slave byte control Disabled,1: Slave byte control Enabled"
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group.long 0x54++0x03
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line.long 0x00 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x00 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled"
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bitfld.long 0x00 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x00 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCLK low time-out interrupt Disabled.\nBus..,1: SCLK low time-out interrupt Enabled.\nBus.."
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bitfld.long 0x00 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit\nFor Master it calculates the period from START to ACK\nFor Slave it calculates the period from START to STOP" "0: Cumulative clock low time-out detection..,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x00 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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group.long 0x58++0x03
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line.long 0x00 "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x00 7. "PECDONE,PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: PEC transmission/ receive is not finished..,1: PEC transmission/ receive is finished when.."
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bitfld.long 0x00 6. "CLKTO,Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit" "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x00 5. "BUSTO,Bus Time-out Status \nIn bus busy the bit indicates the total clock low time-out event occurred otherwise it indicates the bus idle time-out event occurred.\nNote: Software can write 1 to clear this bit" "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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bitfld.long 0x00 4. "SCTLDIN,Bus Suspend or Control Signal Input Status" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x00 3. "ALERT,SMBus Alert Status \nNote: 1" "0: SMBALERT pin state is low.\nNo SMBALERT event,1: SMBALERT pin state is high.\nThere is.."
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bitfld.long 0x00 2. "PECERR,PEC Error in Reception \nNote: Software can write 1 to clear this bit" "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x00 1. "BCDONE,Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit" "0: Byte count transmission/ receive is not..,1: Byte count transmission/ receive is finished.."
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bitfld.long 0x00 0. "BUSY,Bus Busy\nIndicates that a communication is in progress on the bus" "0: Bus is IDLE (both SCLK and SDA High),1: Bus is busy"
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group.long 0x5C++0x03
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line.long 0x00 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x00 0.--8. 1. "PLDSIZE,Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set"
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rgroup.long 0x60++0x03
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line.long 0x00 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x00 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x03
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line.long 0x00 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x00 0.--7. 1. "BUSTO,Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]).."
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group.long 0x68++0x03
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line.long 0x00 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x00 0.--7. 1. "CLKTO,Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set"
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tree.end
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tree.end
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tree "I2S"
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tree "I2S"
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base ad:0x40048000
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group.long 0x00++0x03
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line.long 0x00 "I2S_CTL0,I2S Control Register 0"
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bitfld.long 0x00 30.--31. "TDMCHNUM,TDM Channel Number" "0: 2 channels in audio frame,1: 4 channels in audio frame,2: 6 channels in audio frame,3: 8 channels in audio frame"
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bitfld.long 0x00 28.--29. "CHWIDTH,Channel Width\nThis bit fields are used to define the length of audio channel" "0: The bit-width of each audio channel is 8-bit,1: The bit-width of each audio channel is 16-bit,2: The bit-width of each audio channel is 24-bit,3: The bit-width of each audio channel is 32-bit"
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bitfld.long 0x00 27. "PCMSYNC,PCM Synchronization Pulse Length Selection\nThis bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\nNote: This bit is only available in master mode" "0: One BCLK period,1: One channel period"
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bitfld.long 0x00 24.--26. "FORMAT,Data Format Selection" "0: I2S standard data format,1: I2S with MSB justified,2: I2S with LSB justified,3: Reserved,4: PCM standard data format,5: PCM with MSB justified,6: PCM with LSB justified,7: Reserved"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive channel1 data in MONO mode,1: Receive channel0 data in MONO mode"
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bitfld.long 0x00 21. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 20. "TXPDMAEN,Transmit PDMA Enable Bit" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 19. "RXFBCLR,Receive FIFO Buffer Clear\nNote1: Write 1 to clear receive FIFO internal pointer is reset to FIFO start point and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically read it.." "0: No Effect,1: Clear RX FIFO"
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bitfld.long 0x00 18. "TXFBCLR,Transmit FIFO Buffer Clear\nNote1: Write 1 to clear transmit FIFO internal pointer is reset to FIFO start point and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed" "0: No Effect,1: Clear TX FIFO"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on I2S_MCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode Enable Bit\nNote: I2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO\nIn 8-bit/16-bit data width this bit is used to select whether the even or odd channel data is stored in higher byte" "0: Even channel data at high byte in..,1: Even channel data at low byte in 8-bit/16-bit.."
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bitfld.long 0x00 6. "MONO,Monaural Data Control\nNote: When chip records data RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "DATWIDTH,Data Width\nThis bit field is used to define the bit-width of data word in each audio channel" "0: The bit-width of data word is 8-bit,1: The bit-width of data word is 16-bit,2: The bit-width of data word is 24-bit,3: The bit-width of data word is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Send zero on transmit channel"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receiving Disabled,1: Data receiving Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmission Disabled,1: Data transmission Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit" "0: I2S controller Disabled,1: I2S controller Enabled"
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group.long 0x04++0x03
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line.long 0x00 "I2S_CLKDIV,I2S Clock Divider Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip"
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group.long 0x08++0x03
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line.long 0x00 "I2S_IEN,I2S Interrupt Enable Register"
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bitfld.long 0x00 23. "CH7ZCIEN,Channel7 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 22. "CH6ZCIEN,Channel6 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 21. "CH5ZCIEN,Channel5 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 20. "CH4ZCIEN,Channel4 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 19. "CH3ZCIEN,Channel3 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 18. "CH2ZCIEN,Channel2 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 17. "CH1ZCIEN,Channel1 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 16. "CH0ZCIEN,Channel0 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8])" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 9. "TXOVFIEN,Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 8. "TXUDFIEN,Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16])" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 1. "RXOVFIEN,Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 0. "RXUDFIEN,Receive FIFO Underflow Interrupt Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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group.long 0x0C++0x03
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line.long 0x00 "I2S_STATUS0,I2S Status Register 0"
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rbitfld.long 0x00 21. "TXBUSY,Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out" "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
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rbitfld.long 0x00 20. "TXEMPTY,Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0x00 19. "TXFULL,Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 16" "0: Not full,1: Full"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1" "0: Data word(s) in FIFO is larger than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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bitfld.long 0x00 17. "TXOVIF,Transmit FIFO Overflow Interrupt Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0" "0: No overflow,1: Overflow"
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bitfld.long 0x00 16. "TXUDIF,Transmit FIFO Underflow Interrupt Flag\nNote1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\nNote2: Write 1 to clear this.." "0: No underflow,1: Underflow"
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rbitfld.long 0x00 12. "RXEMPTY,Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0x00 11. "RXFULL,Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 16" "0: Not full,1: Full"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1" "0: Data word(s) in FIFO is less than or equal to..,1: Data word(s) in FIFO is larger than threshold.."
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bitfld.long 0x00 9. "RXOVIF,Receive FIFO Overflow Interrupt Flag\nNote1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1 data in 1st buffer is overwritten.\nNote2: Write 1 to clear this bit to 0" "0: No overflow occur,1: Overflow occur"
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bitfld.long 0x00 8. "RXUDIF,Receive FIFO Underflow Interrupt Flag\nNote1: When receive FIFO is empty and software reads the receive FIFO again" "0: No underflow occur,1: Underflow occur"
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rbitfld.long 0x00 3.--5. "DATACH,Transmission Data Channel (Read Only)\nThis bit fields are used to indicate which audio channel is current transmit data belong" "0: channel0 (means left channel while 2-channel..,1: channel1 (means right channel while 2-channel..,2: channel2 (available while 4-channel TDM PCM..,3: channel3 (available while 4-channel TDM PCM..,4: channel4 (available while 6-channel TDM PCM..,5: channel5 (available while 6-channel TDM PCM..,6: channel6 (available while 8-channel TDM PCM..,7: channel7 (available while 8-channel TDM PCM.."
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rbitfld.long 0x00 2. "I2STXINT,I2S Transmit Interrupt (Read Only)" "0: No transmit interrupt,1: Transmit interrupt"
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rbitfld.long 0x00 1. "I2SRXINT,I2S Receive Interrupt (Read Only)" "0: No receive interrupt,1: Receive interrupt"
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rbitfld.long 0x00 0. "I2SINT,I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of I2STXINT and I2SRXINT bits" "0: No I2S interrupt,1: I2S interrupt"
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wgroup.long 0x10++0x03
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line.long 0x00 "I2S_TXFIFO,I2S Transmit FIFO Register"
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hexmask.long 0x00 0.--31. 1. "TXFIFO,Transmit FIFO Bits\nThe I2S contains 16 words (16x32 bits) data buffer for data transmit"
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rgroup.long 0x14++0x03
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line.long 0x00 "I2S_RXFIFO,I2S Receive FIFO Register"
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hexmask.long 0x00 0.--31. 1. "RXFIFO,Receive FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data receive"
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group.long 0x20++0x03
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line.long 0x00 "I2S_CTL1,I2S Control Register 1"
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bitfld.long 0x00 25. "PB16ORD,FIFO Read/Write Order in 16-bit Width of Peripheral Bus" "0: Low 16-bit read/write access first,1: High 16-bit read/write access first"
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bitfld.long 0x00 24. "PBWIDTH,Peripheral Bus Data Width Selection\nThis bit is used to choice the available data width of APB bus" "0: 32 bits data width,1: 16 bits data width"
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bitfld.long 0x00 16.--19. "RXTH,Receive FIFO Threshold Level\nNote: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set" "0: 1 data word in receive FIFO,1: 2 data words in receive FIFO,2: 3 data words in receive FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 15 data words in receive FIFO,15: 16 data words in receive FIFO"
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bitfld.long 0x00 8.--11. "TXTH,Transmit FIFO Threshold Level\nNote: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set" "0: 0 data word in transmit FIFO,1: 1 data word in transmit FIFO,2: 2 data words in transmit FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 data words in transmit FIFO,15: 15 data words in transmit FIFO"
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bitfld.long 0x00 7. "CH7ZCEN,Channel7 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\nNote3: If CH7ZCIF flag is set to 1 the channel7 will be.." "0: channel7 zero-cross detect Disabled,1: channel7 zero-cross detect Enabled"
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bitfld.long 0x00 6. "CH6ZCEN,Channel6 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\nNote3: If CH6ZCIF flag is set to 1 the channel6 will be mute" "0: channel6 zero-cross detect Disabled,1: channel6 zero-cross detect Enabled"
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bitfld.long 0x00 5. "CH5ZCEN,Channel5 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\nNote3: If CH5ZCIF flag is set to 1 the channel5 will be mute" "0: channel5 zero-cross detect Disabled,1: channel5 zero-cross detect Enabled"
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bitfld.long 0x00 4. "CH4ZCEN,Channel4 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\nNote3: If CH4ZCIF flag is set to 1 the channel4 will be mute" "0: channel4 zero-cross detect Disabled,1: channel4 zero-cross detect Enabled"
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bitfld.long 0x00 3. "CH3ZCEN,Channel3 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\nNote3: If CH3ZCIF flag is set to 1 the channel3 will be mute" "0: channel3 zero-cross detect Disabled,1: channel3 zero-cross detect Enabled"
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bitfld.long 0x00 2. "CH2ZCEN,Channel2 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\nNote3: If CH2ZCIF flag is set to 1 the channel2 will be mute" "0: channel2 zero-cross detect Disabled,1: channel2 zero-cross detect Enabled"
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bitfld.long 0x00 1. "CH1ZCEN,Channel1 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\nNote3: If CH1ZCIF flag is set to 1 the channel1 will be mute" "0: channel1 zero-cross detect Disabled,1: channel1 zero-cross detect Enabled"
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bitfld.long 0x00 0. "CH0ZCEN,Channel0 Zero-cross Detection Enable Bit\nNote2: If this bit is set to 1 when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\nNote3: If CH0ZCIF flag is set to 1 the channel0 will be.." "0: channel0 zero-cross detect Disabled,1: channel0 zero-cross detect Enabled"
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group.long 0x24++0x03
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line.long 0x00 "I2S_STATUS1,I2S Status Register 1"
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rbitfld.long 0x00 16.--20. "RXCNT,Receive FIFO Level (Read Only)\nThese bits indicate the number of available entries in receive FIFO\nOthers are reserved" "0: No data,1: 1 word in receive FIFO,2: 2 words in receive FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 words in receive FIFO,15: 15 words in receive FIFO,16: 16 words in receive FIFO,?..."
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rbitfld.long 0x00 8.--12. "TXCNT,Transmit FIFO Level (Read Only)\nThese bits indicate the number of available entries in transmit FIFO\nOthers are reserved" "0: No data,1: 1 word in transmit FIFO,2: 2 words in transmit FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 words in transmit FIFO,15: 15 words in transmit FIFO,16: 16 words in transmit FIFO,?..."
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bitfld.long 0x00 7. "CH7ZCIF,Channel7 Zero-cross Interrupt Flag\nIt indicates channel7 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel7,1: Channel7 zero-cross is detected"
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bitfld.long 0x00 6. "CH6ZCIF,Channel6 Zero-cross Interrupt Flag\nIt indicates channel6 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel6,1: Channel6 zero-cross is detected"
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bitfld.long 0x00 5. "CH5ZCIF,Channel5 Zero-cross Interrupt Flag\nIt indicates channel5 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel5,1: Channel5 zero-cross is detected"
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bitfld.long 0x00 4. "CH4ZCIF,Channel4 Zero-cross Interrupt Flag\nIt indicates channel4 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel4,1: Channel4 zero-cross is detected"
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bitfld.long 0x00 3. "CH3ZCIF,Channel3 Zero-cross Interrupt Flag\nIt indicates channel3 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel3,1: Channel3 zero-cross is detected"
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bitfld.long 0x00 2. "CH2ZCIF,Channel2 Zero-cross Interrupt Flag\nIt indicates channel2 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel2,1: Channel2 zero-cross is detected"
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bitfld.long 0x00 1. "CH1ZCIF,Channel1 Zero-cross Interrupt Flag\nIt indicates channel1 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel1,1: Channel1 zero-cross is detected"
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bitfld.long 0x00 0. "CH0ZCIF,Channel0 Zero-cross Interrupt Flag\nIt indicates channel0 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel0,1: Channel0 zero-cross is detected"
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tree.end
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tree "I2S_NS"
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base ad:0x50048000
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group.long 0x00++0x03
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line.long 0x00 "I2S_CTL0,I2S Control Register 0"
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bitfld.long 0x00 30.--31. "TDMCHNUM,TDM Channel Number" "0: 2 channels in audio frame,1: 4 channels in audio frame,2: 6 channels in audio frame,3: 8 channels in audio frame"
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bitfld.long 0x00 28.--29. "CHWIDTH,Channel Width\nThis bit fields are used to define the length of audio channel" "0: The bit-width of each audio channel is 8-bit,1: The bit-width of each audio channel is 16-bit,2: The bit-width of each audio channel is 24-bit,3: The bit-width of each audio channel is 32-bit"
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bitfld.long 0x00 27. "PCMSYNC,PCM Synchronization Pulse Length Selection\nThis bit field is used to select the high pulse length of frame synchronization signal in PCM protocol\nNote: This bit is only available in master mode" "0: One BCLK period,1: One channel period"
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bitfld.long 0x00 24.--26. "FORMAT,Data Format Selection" "0: I2S standard data format,1: I2S with MSB justified,2: I2S with LSB justified,3: Reserved,4: PCM standard data format,5: PCM with MSB justified,6: PCM with LSB justified,7: Reserved"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive channel1 data in MONO mode,1: Receive channel0 data in MONO mode"
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bitfld.long 0x00 21. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 20. "TXPDMAEN,Transmit PDMA Enable Bit" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 19. "RXFBCLR,Receive FIFO Buffer Clear\nNote1: Write 1 to clear receive FIFO internal pointer is reset to FIFO start point and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically read it.." "0: No Effect,1: Clear RX FIFO"
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bitfld.long 0x00 18. "TXFBCLR,Transmit FIFO Buffer Clear\nNote1: Write 1 to clear transmit FIFO internal pointer is reset to FIFO start point and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed" "0: No Effect,1: Clear TX FIFO"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on I2S_MCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode Enable Bit\nNote: I2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO\nIn 8-bit/16-bit data width this bit is used to select whether the even or odd channel data is stored in higher byte" "0: Even channel data at high byte in..,1: Even channel data at low byte in 8-bit/16-bit.."
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bitfld.long 0x00 6. "MONO,Monaural Data Control\nNote: When chip records data RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "DATWIDTH,Data Width\nThis bit field is used to define the bit-width of data word in each audio channel" "0: The bit-width of data word is 8-bit,1: The bit-width of data word is 16-bit,2: The bit-width of data word is 24-bit,3: The bit-width of data word is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Send zero on transmit channel"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receiving Disabled,1: Data receiving Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmission Disabled,1: Data transmission Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit" "0: I2S controller Disabled,1: I2S controller Enabled"
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group.long 0x04++0x03
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line.long 0x00 "I2S_CLKDIV,I2S Clock Divider Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip"
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group.long 0x08++0x03
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line.long 0x00 "I2S_IEN,I2S Interrupt Enable Register"
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bitfld.long 0x00 23. "CH7ZCIEN,Channel7 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 22. "CH6ZCIEN,Channel6 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 21. "CH5ZCIEN,Channel5 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 20. "CH4ZCIEN,Channel4 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 19. "CH3ZCIEN,Channel3 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 18. "CH2ZCIEN,Channel2 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 17. "CH1ZCIEN,Channel1 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 16. "CH0ZCIEN,Channel0 Zero-cross Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than or equal to TXTH (I2S_CTL1[11:8])" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 9. "TXOVFIEN,Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 8. "TXUDFIEN,Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in receive FIFO is larger than RXTH (I2S_CTL1[19:16])" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 1. "RXOVFIEN,Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 0. "RXUDFIEN,Receive FIFO Underflow Interrupt Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
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group.long 0x0C++0x03
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line.long 0x00 "I2S_STATUS0,I2S Status Register 0"
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rbitfld.long 0x00 21. "TXBUSY,Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out" "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
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rbitfld.long 0x00 20. "TXEMPTY,Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0x00 19. "TXFULL,Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 16" "0: Not full,1: Full"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in transmit FIFO is less than or equal to threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1" "0: Data word(s) in FIFO is larger than threshold..,1: Data word(s) in FIFO is less than or equal to.."
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bitfld.long 0x00 17. "TXOVIF,Transmit FIFO Overflow Interrupt Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0" "0: No overflow,1: Overflow"
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bitfld.long 0x00 16. "TXUDIF,Transmit FIFO Underflow Interrupt Flag\nNote1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame.\nNote2: Write 1 to clear this.." "0: No underflow,1: Underflow"
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rbitfld.long 0x00 12. "RXEMPTY,Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is 0" "0: Not empty,1: Empty"
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rbitfld.long 0x00 11. "RXFULL,Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 16" "0: Not full,1: Full"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)\nNote: When data word(s) in receive FIFO is larger than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1" "0: Data word(s) in FIFO is less than or equal to..,1: Data word(s) in FIFO is larger than threshold.."
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bitfld.long 0x00 9. "RXOVIF,Receive FIFO Overflow Interrupt Flag\nNote1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1 data in 1st buffer is overwritten.\nNote2: Write 1 to clear this bit to 0" "0: No overflow occur,1: Overflow occur"
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newline
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bitfld.long 0x00 8. "RXUDIF,Receive FIFO Underflow Interrupt Flag\nNote1: When receive FIFO is empty and software reads the receive FIFO again" "0: No underflow occur,1: Underflow occur"
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rbitfld.long 0x00 3.--5. "DATACH,Transmission Data Channel (Read Only)\nThis bit fields are used to indicate which audio channel is current transmit data belong" "0: channel0 (means left channel while 2-channel..,1: channel1 (means right channel while 2-channel..,2: channel2 (available while 4-channel TDM PCM..,3: channel3 (available while 4-channel TDM PCM..,4: channel4 (available while 6-channel TDM PCM..,5: channel5 (available while 6-channel TDM PCM..,6: channel6 (available while 8-channel TDM PCM..,7: channel7 (available while 8-channel TDM PCM.."
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newline
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rbitfld.long 0x00 2. "I2STXINT,I2S Transmit Interrupt (Read Only)" "0: No transmit interrupt,1: Transmit interrupt"
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rbitfld.long 0x00 1. "I2SRXINT,I2S Receive Interrupt (Read Only)" "0: No receive interrupt,1: Receive interrupt"
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newline
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rbitfld.long 0x00 0. "I2SINT,I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of I2STXINT and I2SRXINT bits" "0: No I2S interrupt,1: I2S interrupt"
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wgroup.long 0x10++0x03
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line.long 0x00 "I2S_TXFIFO,I2S Transmit FIFO Register"
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hexmask.long 0x00 0.--31. 1. "TXFIFO,Transmit FIFO Bits\nThe I2S contains 16 words (16x32 bits) data buffer for data transmit"
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rgroup.long 0x14++0x03
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line.long 0x00 "I2S_RXFIFO,I2S Receive FIFO Register"
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hexmask.long 0x00 0.--31. 1. "RXFIFO,Receive FIFO Bits\nI2S contains 16 words (16x32 bits) data buffer for data receive"
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group.long 0x20++0x03
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line.long 0x00 "I2S_CTL1,I2S Control Register 1"
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bitfld.long 0x00 25. "PB16ORD,FIFO Read/Write Order in 16-bit Width of Peripheral Bus" "0: Low 16-bit read/write access first,1: High 16-bit read/write access first"
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bitfld.long 0x00 24. "PBWIDTH,Peripheral Bus Data Width Selection\nThis bit is used to choice the available data width of APB bus" "0: 32 bits data width,1: 16 bits data width"
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newline
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bitfld.long 0x00 16.--19. "RXTH,Receive FIFO Threshold Level\nNote: When received data word number in receive buffer is larger than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set" "0: 1 data word in receive FIFO,1: 2 data words in receive FIFO,2: 3 data words in receive FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 15 data words in receive FIFO,15: 16 data words in receive FIFO"
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bitfld.long 0x00 8.--11. "TXTH,Transmit FIFO Threshold Level\nNote: If remain data word number in transmit FIFO is less than or equal to threshold level then TXTHIF (I2S_STATUS0[18]) flag is set" "0: 0 data word in transmit FIFO,1: 1 data word in transmit FIFO,2: 2 data words in transmit FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 data words in transmit FIFO,15: 15 data words in transmit FIFO"
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newline
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bitfld.long 0x00 7. "CH7ZCEN,Channel7 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel7 data sign bit change or next shift data bits are all 0 then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1.\nNote3: If CH7ZCIF flag is set to 1 the channel7 will be.." "0: channel7 zero-cross detect Disabled,1: channel7 zero-cross detect Enabled"
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bitfld.long 0x00 6. "CH6ZCEN,Channel6 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel6 data sign bit change or next shift data bits are all 0 then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1.\nNote3: If CH6ZCIF flag is set to 1 the channel6 will be mute" "0: channel6 zero-cross detect Disabled,1: channel6 zero-cross detect Enabled"
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newline
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bitfld.long 0x00 5. "CH5ZCEN,Channel5 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel5 data sign bit change or next shift data bits are all 0 then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1.\nNote3: If CH5ZCIF flag is set to 1 the channel5 will be mute" "0: channel5 zero-cross detect Disabled,1: channel5 zero-cross detect Enabled"
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bitfld.long 0x00 4. "CH4ZCEN,Channel4 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel4 data sign bit change or next shift data bits are all 0 then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1.\nNote3: If CH4ZCIF flag is set to 1 the channel4 will be mute" "0: channel4 zero-cross detect Disabled,1: channel4 zero-cross detect Enabled"
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newline
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bitfld.long 0x00 3. "CH3ZCEN,Channel3 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel3 data sign bit change or next shift data bits are all 0 then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1.\nNote3: If CH3ZCIF flag is set to 1 the channel3 will be mute" "0: channel3 zero-cross detect Disabled,1: channel3 zero-cross detect Enabled"
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bitfld.long 0x00 2. "CH2ZCEN,Channel2 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel2 data sign bit change or next shift data bits are all 0 then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1.\nNote3: If CH2ZCIF flag is set to 1 the channel2 will be mute" "0: channel2 zero-cross detect Disabled,1: channel2 zero-cross detect Enabled"
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newline
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bitfld.long 0x00 1. "CH1ZCEN,Channel1 Zero-cross Detect Enable Bit\nNote2: If this bit is set to 1 when channel1 data sign bit change or next shift data bits are all 0 then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1.\nNote3: If CH1ZCIF flag is set to 1 the channel1 will be mute" "0: channel1 zero-cross detect Disabled,1: channel1 zero-cross detect Enabled"
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bitfld.long 0x00 0. "CH0ZCEN,Channel0 Zero-cross Detection Enable Bit\nNote2: If this bit is set to 1 when channel0 data sign bit change or next shift data bits are all 0 then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1.\nNote3: If CH0ZCIF flag is set to 1 the channel0 will be.." "0: channel0 zero-cross detect Disabled,1: channel0 zero-cross detect Enabled"
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group.long 0x24++0x03
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line.long 0x00 "I2S_STATUS1,I2S Status Register 1"
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rbitfld.long 0x00 16.--20. "RXCNT,Receive FIFO Level (Read Only)\nThese bits indicate the number of available entries in receive FIFO\nOthers are reserved" "0: No data,1: 1 word in receive FIFO,2: 2 words in receive FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 words in receive FIFO,15: 15 words in receive FIFO,16: 16 words in receive FIFO,?..."
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rbitfld.long 0x00 8.--12. "TXCNT,Transmit FIFO Level (Read Only)\nThese bits indicate the number of available entries in transmit FIFO\nOthers are reserved" "0: No data,1: 1 word in transmit FIFO,2: 2 words in transmit FIFO,?,?,?,?,?,?,?,?,?,?,?,14: 14 words in transmit FIFO,15: 15 words in transmit FIFO,16: 16 words in transmit FIFO,?..."
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newline
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bitfld.long 0x00 7. "CH7ZCIF,Channel7 Zero-cross Interrupt Flag\nIt indicates channel7 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel7,1: Channel7 zero-cross is detected"
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bitfld.long 0x00 6. "CH6ZCIF,Channel6 Zero-cross Interrupt Flag\nIt indicates channel6 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel6,1: Channel6 zero-cross is detected"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5ZCIF,Channel5 Zero-cross Interrupt Flag\nIt indicates channel5 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel5,1: Channel5 zero-cross is detected"
|
|
bitfld.long 0x00 4. "CH4ZCIF,Channel4 Zero-cross Interrupt Flag\nIt indicates channel4 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel4,1: Channel4 zero-cross is detected"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3ZCIF,Channel3 Zero-cross Interrupt Flag\nIt indicates channel3 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel3,1: Channel3 zero-cross is detected"
|
|
bitfld.long 0x00 2. "CH2ZCIF,Channel2 Zero-cross Interrupt Flag\nIt indicates channel2 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel2,1: Channel2 zero-cross is detected"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1ZCIF,Channel1 Zero-cross Interrupt Flag\nIt indicates channel1 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel1,1: Channel1 zero-cross is detected"
|
|
bitfld.long 0x00 0. "CH0ZCIF,Channel0 Zero-cross Interrupt Flag\nIt indicates channel0 next sample data sign bit is changed or all data bits are 0" "0: No zero-cross in channel0,1: Channel0 zero-cross is detected"
|
|
tree.end
|
|
tree.end
|
|
tree "NMI"
|
|
base ad:0x40000300
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x00 17. "EINT7,External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.9 or PD.10 pin NMI..,1: External interrupt from PB.9 or PD.10 pin NMI.."
|
|
bitfld.long 0x00 16. "EINT6,External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.8 or PD.11 pin NMI..,1: External interrupt from PB.8 or PD.11 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 15. "UART1INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x00 14. "UART0INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.7 or PD.12 pin NMI..,1: External interrupt from PB.7 or PD.12 pin NMI.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.8 or PB.6 pin NMI..,1: External interrupt from PA.8 or PB.6 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.2 or PC.7pin NMI..,1: External interrupt from PB.2 or PC.7 pin NMI.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PB.3 or PC.6 pin NMI..,1: External interrupt from PB.3 or PC.6 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.7 or PB.4 pin NMI..,1: External interrupt from PA.7 or P4.4 pin NMI.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.6 or PB.5 pin NMI..,1: External interrupt from PA.6 or PB.5 pin NMI.."
|
|
newline
|
|
bitfld.long 0x00 7. "TAMPERINT,Tamper Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Backup register tamper detected interrupt NMI..,1: Backup register tamper detected interrupt NMI.."
|
|
bitfld.long 0x00 6. "RTCINT,RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Clock fail detected interrupt NMI source..,1: Clock fail detected interrupt NMI source.."
|
|
bitfld.long 0x00 3. "SRAMPERR,SRAM Parity Check Error NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: SRAM parity check error NMI source Disabled,1: SRAM parity check error NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWUINT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
bitfld.long 0x00 1. "IRCINT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x00 17. "EINT7,External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.9 or PD.10..,1: External Interrupt from PB.9 or PD.10.."
|
|
bitfld.long 0x00 16. "EINT6,External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.8 or PD.11..,1: External Interrupt from PB.8 or PD.11.."
|
|
newline
|
|
bitfld.long 0x00 15. "UART1INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x00 14. "UART0INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 13. "EINT5,External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.7 or PD.12..,1: External Interrupt from PB.7 or PD.12.."
|
|
bitfld.long 0x00 12. "EINT4,External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.8 or PB.6..,1: External Interrupt from PA.8 or PB.6.."
|
|
newline
|
|
bitfld.long 0x00 11. "EINT3,External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.2 or PC.7..,1: External Interrupt from PB.2 or PC.7.."
|
|
bitfld.long 0x00 10. "EINT2,External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PB.3 or PC.6..,1: External Interrupt from PB.3 or PC.6.."
|
|
newline
|
|
bitfld.long 0x00 9. "EINT1,External Interrupt From PA.7 or PB.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.7 or PB.4..,1: External Interrupt from PA.7 or PB.4.."
|
|
bitfld.long 0x00 8. "EINT0,External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.6 or PB.5..,1: External Interrupt from PA.6 or PB.5.."
|
|
newline
|
|
bitfld.long 0x00 7. "TAMPERINT,Tamper Interrupt Flag (Read Only)" "0: Backup register tamper detected interrupt is..,1: Backup register tamper detected interrupt is.."
|
|
bitfld.long 0x00 6. "RTCINT,RTC Interrupt Flag (Read Only)" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
bitfld.long 0x00 3. "SRAMPERR,SRAM ParityCheck Error Interrupt Flag (Read Only)" "0: SRAM parity check error interrupt is deasserted,1: SRAM parity check error interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 2. "PWRWUINT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
bitfld.long 0x00 1. "IRCINT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC"
|
|
base ad:0xE000E100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVIC_ISER0,IRQ00 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "NVIC_ISER1,IRQ32 ~ IRQ63 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "NVIC_ISER2,IRQ64 ~ IRQ95 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "NVIC_ISER3,IRQ96 ~ IRQ101 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVIC_ICER0,IRQ00 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "NVIC_ICER1,IRQ32 ~ IRQ63 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "NVIC_ICER2,IRQ64 ~ IRQ95 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "NVIC_ICER3,IRQ96 ~ IRQ101 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts and show which interrupts are enabled.\nWrite Operation"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISPR0,IRQ00 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "NVIC_ISPR1,IRQ32 ~ IRQ63 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "NVIC_ISPR2,IRQ64 ~ IRQ95 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "NVIC_ISPR3,IRQ96 ~ IRQ101 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICPR0,IRQ00 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "NVIC_ICPR1,IRQ32 ~ IRQ63 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "NVIC_ICPR2,IRQ64 ~ IRQ95 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "NVIC_ICPR3,IRQ96 ~ IRQ101 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts and show which interrupts are pending.\nWrite Operation"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "NVIC_IABR0,IRQ00 ~ IRQ31 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "NVIC_IABR1,IRQ32 ~ IRQ63 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "NVIC_IABR2,IRQ64 ~ IRQ95 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "NVIC_IABR3,IRQ96 ~ IRQ101 Active Bit Register"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "NVIC_ITNS0,IRQ00 ~ IRQ31 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x00 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS3 registers determines whether each interrupt targets Non-secure or Secure state.\nThis register is RAZ/WI when accessed as Non-secure"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "NVIC_ITNS1,IRQ32 ~ IRQ63 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x00 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS3 registers determines whether each interrupt targets Non-secure or Secure state.\nThis register is RAZ/WI when accessed as Non-secure"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "NVIC_ITNS2,IRQ64 ~ IRQ95 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x00 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS3 registers determines whether each interrupt targets Non-secure or Secure state.\nThis register is RAZ/WI when accessed as Non-secure"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,IRQ96 ~ IRQ101 Interrupt Target Non-secure Register"
|
|
hexmask.long 0x00 0.--31. 1. "ITNS,Interrupt Target Non-secure Register\nThe NVIC_ITNS0-NVIC_INTS3 registers determines whether each interrupt targets Non-secure or Secure state.\nThis register is RAZ/WI when accessed as Non-secure"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "NVIC_IPR1,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "NVIC_IPR2,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "NVIC_IPR3,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "NVIC_IPR4,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "NVIC_IPR5,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "NVIC_IPR6,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "NVIC_IPR7,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "NVIC_IPR8,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "NVIC_IPR9,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "NVIC_IPR10,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "NVIC_IPR11,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "NVIC_IPR12,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "NVIC_IPR13,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "NVIC_IPR14,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x33C++0x03
|
|
line.long 0x00 "NVIC_IPR15,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "NVIC_IPR16,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "NVIC_IPR17,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "NVIC_IPR18,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "NVIC_IPR19,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "NVIC_IPR20,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "NVIC_IPR21,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "NVIC_IPR22,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "NVIC_IPR23,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "NVIC_IPR24,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x364++0x03
|
|
line.long 0x00 "NVIC_IPR25,IRQ0 ~ IRQ101 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_4n_3,Priority of IRQ_4n+3\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_4n_2,Priority of IRQ_4n+2\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "PRI_4n_1,Priority of IRQ_4n+1\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4n_0,Priority of IRQ_4n+0\n'0' denotes the highest priority and '8' denotes the lowest priority" "0,1,2,3"
|
|
tree.end
|
|
tree "OTG"
|
|
tree "OTG"
|
|
base ad:0x4004D000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OTG_CTL,OTG Control Register"
|
|
bitfld.long 0x00 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function..,1: OTG ID pin status change wake-up function.."
|
|
bitfld.long 0x00 4. "OTGEN,OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while USB frame configured as OTG device" "0: OTG function Disabled,1: OTG function Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HNPREQEN,OTG HNP Request Enable Bit\nWhen USB frame as A-device set this bit when A-device allows to process HNP protocol A-device changes role from Host to Peripheral" "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
|
|
bitfld.long 0x00 1. "BUSREQ,OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus setting this bit will drive VBUS high to detect USB device connection" "0: Not launch VBUS in OTG A-device or not..,1: Launch VBUS in OTG A-device or request SRP in.."
|
|
newline
|
|
bitfld.long 0x00 0. "VBUSDROP,Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power set this bit to drop VBUS" "0: Not drop the VBUS,1: Drop the VBUS"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "OTG_PHYCTL,OTG PHY Control Register"
|
|
bitfld.long 0x00 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component" "0: The polarity of off-chip USB VBUS power..,1: The polarity of off-chip USB VBUS power.."
|
|
bitfld.long 0x00 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need" "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
|
|
newline
|
|
bitfld.long 0x00 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
|
|
bitfld.long 0x00 0. "OTGPHYEN,OTG PHY Enable Bit\nWhen USB frame is configured as either OTG-device or ID-dependent user needs to set this bit before using OTG function" "0: OTG PHY Disabled,1: OTG PHY Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "OTG_INTEN,OTG Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 7. "HOSTIEN,Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host an interrupt will be asserted" "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral an interrupt will be asserted" "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
|
|
bitfld.long 0x00 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "GOIDLEIEN,OTG Device Goes to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ROLECHGIEN,Role (Host or Peripheral) Changed Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "OTG_INTSTS,OTG Interrupt Status Register"
|
|
bitfld.long 0x00 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status" "0: SRP not detected,1: SRP detected"
|
|
bitfld.long 0x00 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: SESSEND (OTG_STATUS[2]) not toggled,1: SESSEND (OTG_STATUS[2]) from high to low or.."
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|
newline
|
|
bitfld.long 0x00 10. "VBCHGIF,VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status" "0: VBUSVLD (OTG_STATUS[5]) not toggled,1: VBUSVLD (OTG_STATUS[5]) from high to low or.."
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|
bitfld.long 0x00 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status" "0: AVLD (OTG_STATUS[4]) not toggled,1: AVLD (OTG_STATUS[4]) from high to low or low.."
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|
newline
|
|
bitfld.long 0x00 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status" "0: BVLD (OTG_STATUS[3]) is not toggled,1: BVLD (OTG_STATUS[3]) from high to low or low.."
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bitfld.long 0x00 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a host,1: This device acts as a host"
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|
newline
|
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bitfld.long 0x00 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a peripheral,1: This device acts as a peripheral"
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bitfld.long 0x00 5. "IDCHGIF,ID State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: IDSTS (OTG_STATUS[1]) not toggled,1: IDSTS (OTG_STATUS[1]) from high to low or.."
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|
newline
|
|
bitfld.long 0x00 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state" "0: OTG device does not go back to idle state..,1: OTG device goes back to idle state(a_idle or.."
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bitfld.long 0x00 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state this bit will be set when A-device does not connect after specified interval expires" "0: A-device connects to B-device before..,1: A-device does not connect to B-device before.."
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|
newline
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bitfld.long 0x00 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum defined in OTG specification" "0: OTG B-device gets VBUS high before this..,1: OTG B-device does not get VBUS high before.."
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bitfld.long 0x00 1. "VBEIF,VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high" "0: OTG A-device drives VBUS over threshold..,1: OTG A-device cannot drive VBUS over threshold.."
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|
newline
|
|
bitfld.long 0x00 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag" "0: OTG device role not changed,1: OTG device role changed"
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|
rgroup.long 0x10++0x03
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|
line.long 0x00 "OTG_STATUS,OTG Status Register"
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|
bitfld.long 0x00 7. "ASHOST,As Host Status\nWhen OTG acts as Host this bit is set.\n0: OTG not as Host\n1: OTG as Host" "0,1"
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bitfld.long 0x00 6. "ASPERI,As Peripheral Status\nWhen OTG acts as peripheral this bit is set.\n0: OTG not as peripheral\n1: OTG as peripheral" "0,1"
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|
newline
|
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bitfld.long 0x00 5. "VBUSVLD,VBUS Valid Status\nWhen VBUS is larger than 4.7V this bit will be set to 1" "0: VBUS is not valid,1: VBUS is valid"
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bitfld.long 0x00 4. "AVLD,A-device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
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|
newline
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bitfld.long 0x00 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
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bitfld.long 0x00 2. "SESSEND,Session End Status\nWhen VBUS voltage is lower than 0.4V this bit will be set to 1" "0: Session is not end,1: Session is end"
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|
newline
|
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bitfld.long 0x00 1. "IDSTS,USB_ID Pin State of Mini-/Micro-plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
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bitfld.long 0x00 0. "OVERCUR,Over Current Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold 4.4V minimum within a maximum time of 100ms after OTG A-device drives VBUS high" "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drives VBUS high in this.."
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tree.end
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tree "OTG_NS"
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base ad:0x5004D000
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group.long 0x00++0x03
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line.long 0x00 "OTG_CTL,OTG Control Register"
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bitfld.long 0x00 5. "WKEN,OTG ID Pin Wake-up Enable Bit" "0: OTG ID pin status change wake-up function..,1: OTG ID pin status change wake-up function.."
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bitfld.long 0x00 4. "OTGEN,OTG Function Enable Bit\nUser needs to set this bit to enable OTG function while USB frame configured as OTG device" "0: OTG function Disabled,1: OTG function Enabled"
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newline
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bitfld.long 0x00 2. "HNPREQEN,OTG HNP Request Enable Bit\nWhen USB frame as A-device set this bit when A-device allows to process HNP protocol A-device changes role from Host to Peripheral" "0: HNP request Disabled,1: HNP request Enabled (A-device can change role.."
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bitfld.long 0x00 1. "BUSREQ,OTG Bus Request\nIf OTG A-device wants to do data transfers via USB bus setting this bit will drive VBUS high to detect USB device connection" "0: Not launch VBUS in OTG A-device or not..,1: Launch VBUS in OTG A-device or request SRP in.."
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newline
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bitfld.long 0x00 0. "VBUSDROP,Drop VBUS Control\nIf user application running on this OTG A-device wants to conserve power set this bit to drop VBUS" "0: Not drop the VBUS,1: Drop the VBUS"
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group.long 0x04++0x03
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line.long 0x00 "OTG_PHYCTL,OTG PHY Control Register"
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bitfld.long 0x00 5. "VBSTSPOL,Off-chip USB VBUS Power Switch Status Polarity\nThe polarity of off-chip USB VBUS power switch valid signal depends on the selected component" "0: The polarity of off-chip USB VBUS power..,1: The polarity of off-chip USB VBUS power.."
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bitfld.long 0x00 4. "VBENPOL,Off-chip USB VBUS Power Switch Enable Polarity\nThe OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need" "0: The off-chip USB VBUS power switch enable is..,1: The off-chip USB VBUS power switch enable is.."
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newline
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bitfld.long 0x00 1. "IDDETEN,ID Detection Enable Bit" "0: Detect ID pin status Disabled,1: Detect ID pin status Enabled"
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bitfld.long 0x00 0. "OTGPHYEN,OTG PHY Enable Bit\nWhen USB frame is configured as either OTG-device or ID-dependent user needs to set this bit before using OTG function" "0: OTG PHY Disabled,1: OTG PHY Enabled"
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group.long 0x08++0x03
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line.long 0x00 "OTG_INTEN,OTG Interrupt Enable Register"
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bitfld.long 0x00 13. "SRPDETIEN,SRP Detected Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 11. "SECHGIEN,SESSEND Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 10. "VBCHGIEN,VBUSVLD Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 9. "AVLDCHGIEN,A-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 8. "BVLDCHGIEN,B-device Session Valid Status Changed Interrupt Enable Bit\nIf this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 7. "HOSTIEN,Act As Host Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a host an interrupt will be asserted" "0: This device as a host interrupt Disabled,1: This device as a host interrupt Enabled"
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newline
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bitfld.long 0x00 6. "PDEVIEN,Act As Peripheral Interrupt Enable Bit\nIf this bit is set to 1 and the device is changed as a peripheral an interrupt will be asserted" "0: This device as a peripheral interrupt Disabled,1: This device as a peripheral interrupt Enabled"
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bitfld.long 0x00 5. "IDCHGIEN,IDSTS Changed Interrupt Enable Bit\nIf this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high an interrupt will be asserted" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 4. "GOIDLEIEN,OTG Device Goes to IDLE State Interrupt Enable Bit\nNote: Going to idle state means going to a_idle or b_idle state" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 3. "HNPFIEN,HNP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 2. "SRPFIEN,SRP Fail Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 1. "VBEIEN,VBUS Error Interrupt Enable Bit\nNote: VBUS error means going to a_vbus_err state" "0: Interrupt Disabled,1: Interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 0. "ROLECHGIEN,Role (Host or Peripheral) Changed Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
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group.long 0x0C++0x03
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line.long 0x00 "OTG_INTSTS,OTG Interrupt Status Register"
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|
bitfld.long 0x00 13. "SRPDETIF,SRP Detected Interrupt Status\nNote: Write 1 to clear this status" "0: SRP not detected,1: SRP detected"
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|
bitfld.long 0x00 11. "SECHGIF,SESSEND State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: SESSEND (OTG_STATUS[2]) not toggled,1: SESSEND (OTG_STATUS[2]) from high to low or.."
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|
newline
|
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bitfld.long 0x00 10. "VBCHGIF,VBUSVLD State Change Interrupt Status\nNote: Write 1 to clear this status" "0: VBUSVLD (OTG_STATUS[5]) not toggled,1: VBUSVLD (OTG_STATUS[5]) from high to low or.."
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bitfld.long 0x00 9. "AVLDCHGIF,A-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status" "0: AVLD (OTG_STATUS[4]) not toggled,1: AVLD (OTG_STATUS[4]) from high to low or low.."
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|
newline
|
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bitfld.long 0x00 8. "BVLDCHGIF,B-device Session Valid State Change Interrupt Status\nNote: Write 1 to clear this status" "0: BVLD (OTG_STATUS[3]) is not toggled,1: BVLD (OTG_STATUS[3]) from high to low or low.."
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bitfld.long 0x00 7. "HOSTIF,Act As Host Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a host,1: This device acts as a host"
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|
newline
|
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bitfld.long 0x00 6. "PDEVIF,Act As Peripheral Interrupt Status\nNote: Write 1 to clear this flag" "0: This device does not act as a peripheral,1: This device acts as a peripheral"
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bitfld.long 0x00 5. "IDCHGIF,ID State Change Interrupt Status\nNote: Write 1 to clear this flag" "0: IDSTS (OTG_STATUS[1]) not toggled,1: IDSTS (OTG_STATUS[1]) from high to low or.."
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|
newline
|
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bitfld.long 0x00 4. "GOIDLEIF,OTG Device Goes to IDLE Interrupt Status\nFlag is set if the OTG device transfers from non-idle state to idle state" "0: OTG device does not go back to idle state..,1: OTG device goes back to idle state(a_idle or.."
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bitfld.long 0x00 3. "HNPFIF,HNP Fail Interrupt Status\nWhen A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state this bit will be set when A-device does not connect after specified interval expires" "0: A-device connects to B-device before..,1: A-device does not connect to B-device before.."
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newline
|
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bitfld.long 0x00 2. "SRPFIF,SRP Fail Interrupt Status\nAfter initiating SRP an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum defined in OTG specification" "0: OTG B-device gets VBUS high before this..,1: OTG B-device does not get VBUS high before.."
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bitfld.long 0x00 1. "VBEIF,VBUS Error Interrupt Status\nThis bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high" "0: OTG A-device drives VBUS over threshold..,1: OTG A-device cannot drive VBUS over threshold.."
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|
newline
|
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bitfld.long 0x00 0. "ROLECHGIF,OTG Role Change Interrupt Status\nThis flag is set when the role of an OTG device changed from a host to a peripheral or changed from a peripheral to a host while USB_ID pin status does not change.\nNote: Write 1 to clear this flag" "0: OTG device role not changed,1: OTG device role changed"
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rgroup.long 0x10++0x03
|
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line.long 0x00 "OTG_STATUS,OTG Status Register"
|
|
bitfld.long 0x00 7. "ASHOST,As Host Status\nWhen OTG acts as Host this bit is set.\n0: OTG not as Host\n1: OTG as Host" "0,1"
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bitfld.long 0x00 6. "ASPERI,As Peripheral Status\nWhen OTG acts as peripheral this bit is set.\n0: OTG not as peripheral\n1: OTG as peripheral" "0,1"
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|
newline
|
|
bitfld.long 0x00 5. "VBUSVLD,VBUS Valid Status\nWhen VBUS is larger than 4.7V this bit will be set to 1" "0: VBUS is not valid,1: VBUS is valid"
|
|
bitfld.long 0x00 4. "AVLD,A-device Session Valid Status" "0: A-device session is not valid,1: A-device session is valid"
|
|
newline
|
|
bitfld.long 0x00 3. "BVLD,B-device Session Valid Status" "0: B-device session is not valid,1: B-device session is valid"
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|
bitfld.long 0x00 2. "SESSEND,Session End Status\nWhen VBUS voltage is lower than 0.4V this bit will be set to 1" "0: Session is not end,1: Session is end"
|
|
newline
|
|
bitfld.long 0x00 1. "IDSTS,USB_ID Pin State of Mini-/Micro-plug" "0: Mini-A/Micro-A plug is attached,1: Mini-B/Micro-B plug is attached"
|
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bitfld.long 0x00 0. "OVERCUR,Over Current Condition\nThe voltage on VBUS cannot reach a minimum VBUS valid threshold 4.4V minimum within a maximum time of 100ms after OTG A-device drives VBUS high" "0: OTG A-device drives VBUS successfully,1: OTG A-device cannot drives VBUS high in this.."
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tree.end
|
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tree.end
|
|
tree "PDMA"
|
|
repeat 2. (list 0. 1.) (list ad:0x40008000 ad:0x40018000)
|
|
tree "PDMA$1"
|
|
base $2
|
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group.long 0x00++0x03
|
|
line.long 0x00 "PDMAx_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
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bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
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newline
|
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bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
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|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
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bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
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group.long 0x10++0x03
|
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line.long 0x00 "PDMAx_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
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bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
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bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
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|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
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group.long 0x20++0x03
|
|
line.long 0x00 "PDMAx_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
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bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMAx_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
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|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMAx_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PDMAx_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PDMAx_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PDMAx_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMAx_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMAx_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMAx_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMAx_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMAx_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PDMAx_DSCT5_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PDMAx_DSCT6_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PDMAx_DSCT7_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMAx_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMAx_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMAx_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMAx_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMAx_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PDMAx_DSCT5_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PDMAx_DSCT6_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PDMAx_DSCT7_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMAx_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMAx_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMAx_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMAx_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMAx_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDMAx_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PDMAx_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PDMAx_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PDMAx_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDMAx_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x00 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PDMAx_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x00 7. "PAUSE7,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 6. "PAUSE6,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 5. "PAUSE5,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 4. "PAUSE4,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 3. "PAUSE3,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 2. "PAUSE2,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 1. "PAUSE1,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 0. "PAUSE0,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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wgroup.long 0x408++0x03
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line.long 0x00 "PDMAx_SWREQ,PDMA Software Request Register"
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bitfld.long 0x00 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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rgroup.long 0x40C++0x03
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line.long 0x00 "PDMAx_TRGSTS,PDMA Channel Request Status Register"
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bitfld.long 0x00 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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group.long 0x410++0x03
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line.long 0x00 "PDMAx_PRISET,PDMA Fixed Priority Setting Register"
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bitfld.long 0x00 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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wgroup.long 0x414++0x03
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line.long 0x00 "PDMAx_PRICLR,PDMA Fixed Priority Clear Register"
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bitfld.long 0x00 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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group.long 0x418++0x03
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line.long 0x00 "PDMAx_INTEN,PDMA Interrupt Enable Register"
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bitfld.long 0x00 7. "INTEN7,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 6. "INTEN6,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 5. "INTEN5,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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group.long 0x41C++0x03
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line.long 0x00 "PDMAx_INTSTS,PDMA Interrupt Status Register"
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bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear this bit" "0: No request time-out,1: Peripheral request time-out"
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bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear this bit" "0: No request time-out,1: Peripheral request time-out"
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rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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group.long 0x420++0x03
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line.long 0x00 "PDMAx_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x00 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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group.long 0x424++0x03
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line.long 0x00 "PDMAx_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0x00 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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group.long 0x428++0x03
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line.long 0x00 "PDMAx_ALIGN,PDMA Transfer Alignment Status Register"
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bitfld.long 0x00 7. "ALIGN7,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 6. "ALIGN6,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 5. "ALIGN5,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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rgroup.long 0x42C++0x03
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line.long 0x00 "PDMAx_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x00 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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group.long 0x430++0x03
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line.long 0x00 "PDMAx_TOUTPSC,PDMA Time-out Prescaler Register"
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bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
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bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
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group.long 0x434++0x03
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line.long 0x00 "PDMAx_TOUTEN,PDMA Time-out Enable Register"
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bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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group.long 0x438++0x03
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line.long 0x00 "PDMAx_TOUTIEN,PDMA Time-out Interrupt Enable Register"
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bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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group.long 0x43C++0x03
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line.long 0x00 "PDMAx_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
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group.long 0x440++0x03
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line.long 0x00 "PDMAx_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register"
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hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
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hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0"
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group.long 0x460++0x03
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line.long 0x00 "PDMAx_CHRST,PDMA Channel Reset Register"
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bitfld.long 0x00 7. "CH7RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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bitfld.long 0x00 6. "CH6RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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bitfld.long 0x00 5. "CH5RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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bitfld.long 0x00 4. "CH4RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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bitfld.long 0x00 3. "CH3RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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bitfld.long 0x00 2. "CH2RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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newline
|
|
bitfld.long 0x00 1. "CH1RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
bitfld.long 0x00 0. "CH0RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
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|
group.long 0x480++0x03
|
|
line.long 0x00 "PDMAx_REQSEL0_3,PDMA Request Source Select Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3"
|
|
hexmask.long.byte 0x00 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2"
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|
newline
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hexmask.long.byte 0x00 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1"
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|
abitfld.long 0x00 0.--6. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0x01=1: A peripheral cannot be assigned to two..,0x02=2: This field is useless when transfer.."
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|
group.long 0x484++0x03
|
|
line.long 0x00 "PDMAx_REQSEL4_7,PDMA Request Source Select Register 1"
|
|
bitfld.long 0x00 24.--29. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.byte 0x00 16.--22. 1. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6"
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|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5"
|
|
hexmask.long.byte 0x00 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4"
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|
group.long 0x500++0x03
|
|
line.long 0x00 "PDMAx_STCR0,Stride Transfer Count Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x504++0x03
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|
line.long 0x00 "PDMAx_ASOCR0,Address Stride Offset Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "PDMAx_STCR1,Stride Transfer Count Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "PDMAx_ASOCR1,Address Stride Offset Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "PDMAx_STCR2,Stride Transfer Count Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "PDMAx_ASOCR2,Address Stride Offset Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "PDMAx_STCR3,Stride Transfer Count Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "PDMAx_ASOCR3,Address Stride Offset Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "PDMAx_STCR4,Stride Transfer Count Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "PDMAx_ASOCR4,Address Stride Offset Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "PDMAx_STCR5,Stride Transfer Count Register of PDMA Channel 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "PDMAx_ASOCR5,Address Stride Offset Register of PDMA Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
tree.end
|
|
repeat.end
|
|
tree "PDMA1_NS"
|
|
base ad:0x50018000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA1_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
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|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
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|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PDMA1_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMA1_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMA1_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMA1_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PDMA1_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PDMA1_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "PDMA1_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 65536 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 15. "STRIDEEN,Stride Mode Enable Bit" "0: Stride transfer mode Disabled,1: Stride transfer mode Enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA1_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMA1_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMA1_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMA1_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMA1_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PDMA1_DSCT5_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PDMA1_DSCT6_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PDMA1_DSCT7_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA1_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMA1_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMA1_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMA1_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMA1_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PDMA1_DSCT5_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "PDMA1_DSCT6_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "PDMA1_DSCT7_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMA1_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMA1_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMA1_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMA1_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMA1_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PDMA1_DSCT5_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "PDMA1_DSCT6_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "PDMA1_DSCT7_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n"
|
|
hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PDMA1_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.."
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PDMA1_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x00 7. "CHEN7,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 6. "CHEN6,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "CHEN5,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x03
|
|
line.long 0x00 "PDMA1_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x00 7. "PAUSE7,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 6. "PAUSE6,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 5. "PAUSE5,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 4. "PAUSE4,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 3. "PAUSE3,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 2. "PAUSE2,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x00 1. "PAUSE1,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x00 0. "PAUSE0,PDMA Channel N Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
wgroup.long 0x408++0x03
|
|
line.long 0x00 "PDMA1_SWREQ,PDMA Software Request Register"
|
|
bitfld.long 0x00 7. "SWREQ7,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 6. "SWREQ6,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 5. "SWREQ5,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
newline
|
|
bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "PDMA1_TRGSTS,PDMA Channel Request Status Register"
|
|
bitfld.long 0x00 7. "REQSTS7,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 6. "REQSTS6,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 5. "REQSTS5,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "PDMA1_PRISET,PDMA Fixed Priority Setting Register"
|
|
bitfld.long 0x00 7. "FPRISET7,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 6. "FPRISET6,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
newline
|
|
bitfld.long 0x00 5. "FPRISET5,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
newline
|
|
bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
newline
|
|
bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority clear fixed priority use PDMA_PRICLR register" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
|
|
wgroup.long 0x414++0x03
|
|
line.long 0x00 "PDMA1_PRICLR,PDMA Fixed Priority Clear Register"
|
|
bitfld.long 0x00 7. "FPRICLR7,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
bitfld.long 0x00 6. "FPRICLR6,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
newline
|
|
bitfld.long 0x00 5. "FPRICLR5,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
newline
|
|
bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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|
bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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|
newline
|
|
bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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|
bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "PDMA1_INTEN,PDMA Interrupt Enable Register"
|
|
bitfld.long 0x00 7. "INTEN7,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
bitfld.long 0x00 6. "INTEN6,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
newline
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|
bitfld.long 0x00 5. "INTEN5,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
newline
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bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
|
|
bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
newline
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bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Its\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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|
group.long 0x41C++0x03
|
|
line.long 0x00 "PDMA1_INTSTS,PDMA Interrupt Status Register"
|
|
bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear this bit" "0: No request time-out,1: Peripheral request time-out"
|
|
bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear this bit" "0: No request time-out,1: Peripheral request time-out"
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|
newline
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rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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|
rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
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|
newline
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rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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|
group.long 0x420++0x03
|
|
line.long 0x00 "PDMA1_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
|
|
bitfld.long 0x00 7. "ABTIF7,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 6. "ABTIF6,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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|
newline
|
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bitfld.long 0x00 5. "ABTIF5,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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newline
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bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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|
newline
|
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bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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|
group.long 0x424++0x03
|
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line.long 0x00 "PDMA1_TDSTS,PDMA Channel Transfer Done Flag Register"
|
|
bitfld.long 0x00 7. "TDIF7,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 6. "TDIF6,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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newline
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bitfld.long 0x00 5. "TDIF5,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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|
newline
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bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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newline
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bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "PDMA1_ALIGN,PDMA Transfer Alignment Status Register"
|
|
bitfld.long 0x00 7. "ALIGN7,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 6. "ALIGN6,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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|
newline
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bitfld.long 0x00 5. "ALIGN5,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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newline
|
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bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
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newline
|
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bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.."
|
|
rgroup.long 0x42C++0x03
|
|
line.long 0x00 "PDMA1_TACTSTS,PDMA Transfer Active Flag Register"
|
|
bitfld.long 0x00 7. "TXACTF7,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 6. "TXACTF6,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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newline
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bitfld.long 0x00 5. "TXACTF5,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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|
newline
|
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bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
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bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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newline
|
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bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
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bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "PDMA1_TOUTPSC,PDMA Time-out Prescaler Register"
|
|
bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
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bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "PDMA1_TOUTEN,PDMA Time-out Enable Register"
|
|
bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
|
|
bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "PDMA1_TOUTIEN,PDMA Time-out Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
|
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bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "PDMA1_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "PDMA1_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "PDMA1_CHRST,PDMA Channel Reset Register"
|
|
bitfld.long 0x00 7. "CH7RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
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bitfld.long 0x00 6. "CH6RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
newline
|
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bitfld.long 0x00 5. "CH5RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
bitfld.long 0x00 4. "CH4RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
newline
|
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bitfld.long 0x00 3. "CH3RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
bitfld.long 0x00 2. "CH2RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
newline
|
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bitfld.long 0x00 1. "CH1RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
bitfld.long 0x00 0. "CH0RST,Channel N Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "PDMA1_REQSEL0_3,PDMA Request Source Select Register 0"
|
|
hexmask.long.byte 0x00 24.--30. 1. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3"
|
|
hexmask.long.byte 0x00 16.--22. 1. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2"
|
|
newline
|
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hexmask.long.byte 0x00 8.--14. 1. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1"
|
|
abitfld.long 0x00 0.--6. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0x01=1: A peripheral cannot be assigned to two..,0x02=2: This field is useless when transfer.."
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|
group.long 0x484++0x03
|
|
line.long 0x00 "PDMA1_REQSEL4_7,PDMA Request Source Select Register 1"
|
|
bitfld.long 0x00 24.--29. "REQSRC7,Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.byte 0x00 16.--22. 1. "REQSRC6,Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--14. 1. "REQSRC5,Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5"
|
|
hexmask.long.byte 0x00 0.--6. 1. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "PDMA1_STCR0,Stride Transfer Count Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "PDMA1_ASOCR0,Address Stride Offset Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "PDMA1_STCR1,Stride Transfer Count Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x50C++0x03
|
|
line.long 0x00 "PDMA1_ASOCR1,Address Stride Offset Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "PDMA1_STCR2,Stride Transfer Count Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x514++0x03
|
|
line.long 0x00 "PDMA1_ASOCR2,Address Stride Offset Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x518++0x03
|
|
line.long 0x00 "PDMA1_STCR3,Stride Transfer Count Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x51C++0x03
|
|
line.long 0x00 "PDMA1_ASOCR3,Address Stride Offset Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "PDMA1_STCR4,Stride Transfer Count Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x524++0x03
|
|
line.long 0x00 "PDMA1_ASOCR4,Address Stride Offset Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
group.long 0x528++0x03
|
|
line.long 0x00 "PDMA1_STCR5,Stride Transfer Count Register of PDMA Channel 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "STC,PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row"
|
|
group.long 0x52C++0x03
|
|
line.long 0x00 "PDMA1_ASOCR5,Address Stride Offset Register of PDMA Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. "DASOL,VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row"
|
|
hexmask.long.word 0x00 0.--15. 1. "SASOL,VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row"
|
|
tree.end
|
|
tree.end
|
|
tree "QEI"
|
|
tree "QEI0"
|
|
base ad:0x400B0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "QEI_CNT,QEI Counter Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNT,Quadrature Encoder Interface Counter \nA 32-bit up/down counter"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "QEI_CNTHOLD,QEI Counter Hold Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNTHOLD,Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "QEI_CNTLATCH,QEI Counter Index Latch Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNTLATCH,Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "QEI_CNTCMP,QEI Counter Compare Register"
|
|
hexmask.long 0x00 0.--31. 1. "CNTCMP,Quadrature Encoder Interface Counter Compare"
|
|
group.long 0x14++0x03
|
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line.long 0x00 "QEI_CNTMAX,QEI Pre-set Maximum Count Register"
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hexmask.long 0x00 0.--31. 1. "CNTMAX,Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode"
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group.long 0x18++0x03
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line.long 0x00 "QEI_CTL,QEI Controller Control Register"
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bitfld.long 0x00 29. "QEIEN,Quadrature Encoder Interface Controller Enable Bit" "0: QEI controller function Disabled,1: QEI controller function Enabled"
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bitfld.long 0x00 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]) if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]) the flag CMPF will be set" "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x00 27. "IDXRLDEN,Index Trigger QEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: QEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x00 25. "IDXLATEN,Index Latch QEI_CNT Enable Bit\nIf this bit is set to high the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX" "0: The index signal latch QEI counter function..,1: The index signal latch QEI counter function.."
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newline
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bitfld.long 0x00 24. "HOLDCNT,Hold QEI_CNT Control\nWhen this bit is set from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])" "0: No operation,1: QEI_CNT content is captured and stored in.."
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bitfld.long 0x00 23. "HOLDTMR3,Hold QEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x00 22. "HOLDTMR2,Hold QEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x00 21. "HOLDTMR1,Hold QEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]).."
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newline
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bitfld.long 0x00 20. "HOLDTMR0,Hold QEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x00 19. "IDXIEN,IDXF Trigger QEI Interrupt Enable Bit" "0: The IDXF can trigger QEI interrupt Disabled,1: The IDXF can trigger QEI interrupt Enabled"
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newline
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bitfld.long 0x00 18. "CMPIEN,CMPF Trigger QEI Interrupt Enable Bit" "0: CMPF can trigger QEI controller interrupt..,1: CMPF can trigger QEI controller interrupt.."
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bitfld.long 0x00 17. "DIRIEN,DIRCHGF Trigger QEI Interrupt Enable Bit" "0: DIRCHGF can trigger QEI controller interrupt..,1: DIRCHGF can trigger QEI controller interrupt.."
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newline
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bitfld.long 0x00 16. "OVUNIEN,OVUNF Trigger QEI Interrupt Enable Bit" "0: OVUNF can trigger QEI controller interrupt..,1: OVUNF can trigger QEI controller interrupt.."
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bitfld.long 0x00 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to QEI.."
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bitfld.long 0x00 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 8.--9. "MODE,QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes" "0: X4 Free-counting Mode,1: X2 Free-counting Mode,2: X4 Compare-counting Mode,3: X2 Compare-counting Mode"
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bitfld.long 0x00 6. "IDXEN,IDX Input to QEI Controller Enable Bit" "0: IDX input to QEI Controller Disabled,1: IDX input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 5. "CHBEN,QEB Input to QEI Controller Enable Bit" "0: QEB input to QEI Controller Disabled,1: QEB input to QEI Controller Enabled"
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bitfld.long 0x00 4. "CHAEN,QEA Input to QEI Controller Enable Bit" "0: QEA input to QEI Controller Disabled,1: QEA input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 3. "NFDIS,QEI Controller Input Noise Filter Disable Bit" "0: The noise filter of QEI controller Enabled,1: The noise filter of QEI controller Disabled"
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: QEI_CLK,1: QEI_CLK/2,2: QEI_CLK/4,3: QEI_CLK/16,4: QEI_CLK/32,5: QEI_CLK/64,?..."
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group.long 0x2C++0x03
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line.long 0x00 "QEI_STATUS,QEI Controller Status Register"
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bitfld.long 0x00 8. "DIRF,QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB" "0: QEI Counter is in down-counting,1: QEI Counter is in up-counting"
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bitfld.long 0x00 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed" "0: No change in QEI counter counting direction,1: QEI counter counting direction is changed"
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newline
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bitfld.long 0x00 2. "OVUNF,QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode" "0: No overflow or underflow occurs in QEI counter,1: QEI counter occurs counting overflow or.."
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bitfld.long 0x00 1. "CMPF,Compare-match Flag\nIf the QEI compare function is enabled the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it" "0: QEI counter does not match with..,1: QEI counter counts to the same as.."
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newline
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bitfld.long 0x00 0. "IDXF,IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it" "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree "QEI0_NS"
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base ad:0x500B0000
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group.long 0x00++0x03
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line.long 0x00 "QEI_CNT,QEI Counter Register"
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hexmask.long 0x00 0.--31. 1. "CNT,Quadrature Encoder Interface Counter \nA 32-bit up/down counter"
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group.long 0x04++0x03
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line.long 0x00 "QEI_CNTHOLD,QEI Counter Hold Register"
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hexmask.long 0x00 0.--31. 1. "CNTHOLD,Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register"
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group.long 0x08++0x03
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line.long 0x00 "QEI_CNTLATCH,QEI Counter Index Latch Register"
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hexmask.long 0x00 0.--31. 1. "CNTLATCH,Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register"
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group.long 0x0C++0x03
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line.long 0x00 "QEI_CNTCMP,QEI Counter Compare Register"
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hexmask.long 0x00 0.--31. 1. "CNTCMP,Quadrature Encoder Interface Counter Compare"
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group.long 0x14++0x03
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line.long 0x00 "QEI_CNTMAX,QEI Pre-set Maximum Count Register"
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hexmask.long 0x00 0.--31. 1. "CNTMAX,Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode"
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group.long 0x18++0x03
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line.long 0x00 "QEI_CTL,QEI Controller Control Register"
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bitfld.long 0x00 29. "QEIEN,Quadrature Encoder Interface Controller Enable Bit" "0: QEI controller function Disabled,1: QEI controller function Enabled"
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bitfld.long 0x00 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]) if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]) the flag CMPF will be set" "0: Compare function Disabled,1: Compare function Enabled"
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newline
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bitfld.long 0x00 27. "IDXRLDEN,Index Trigger QEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: QEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x00 25. "IDXLATEN,Index Latch QEI_CNT Enable Bit\nIf this bit is set to high the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX" "0: The index signal latch QEI counter function..,1: The index signal latch QEI counter function.."
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newline
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bitfld.long 0x00 24. "HOLDCNT,Hold QEI_CNT Control\nWhen this bit is set from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])" "0: No operation,1: QEI_CNT content is captured and stored in.."
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bitfld.long 0x00 23. "HOLDTMR3,Hold QEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x00 22. "HOLDTMR2,Hold QEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x00 21. "HOLDTMR1,Hold QEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]).."
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newline
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bitfld.long 0x00 20. "HOLDTMR0,Hold QEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x00 19. "IDXIEN,IDXF Trigger QEI Interrupt Enable Bit" "0: The IDXF can trigger QEI interrupt Disabled,1: The IDXF can trigger QEI interrupt Enabled"
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newline
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bitfld.long 0x00 18. "CMPIEN,CMPF Trigger QEI Interrupt Enable Bit" "0: CMPF can trigger QEI controller interrupt..,1: CMPF can trigger QEI controller interrupt.."
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bitfld.long 0x00 17. "DIRIEN,DIRCHGF Trigger QEI Interrupt Enable Bit" "0: DIRCHGF can trigger QEI controller interrupt..,1: DIRCHGF can trigger QEI controller interrupt.."
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newline
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bitfld.long 0x00 16. "OVUNIEN,OVUNF Trigger QEI Interrupt Enable Bit" "0: OVUNF can trigger QEI controller interrupt..,1: OVUNF can trigger QEI controller interrupt.."
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bitfld.long 0x00 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to QEI.."
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bitfld.long 0x00 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 8.--9. "MODE,QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes" "0: X4 Free-counting Mode,1: X2 Free-counting Mode,2: X4 Compare-counting Mode,3: X2 Compare-counting Mode"
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bitfld.long 0x00 6. "IDXEN,IDX Input to QEI Controller Enable Bit" "0: IDX input to QEI Controller Disabled,1: IDX input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 5. "CHBEN,QEB Input to QEI Controller Enable Bit" "0: QEB input to QEI Controller Disabled,1: QEB input to QEI Controller Enabled"
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bitfld.long 0x00 4. "CHAEN,QEA Input to QEI Controller Enable Bit" "0: QEA input to QEI Controller Disabled,1: QEA input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 3. "NFDIS,QEI Controller Input Noise Filter Disable Bit" "0: The noise filter of QEI controller Enabled,1: The noise filter of QEI controller Disabled"
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: QEI_CLK,1: QEI_CLK/2,2: QEI_CLK/4,3: QEI_CLK/16,4: QEI_CLK/32,5: QEI_CLK/64,?..."
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group.long 0x2C++0x03
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line.long 0x00 "QEI_STATUS,QEI Controller Status Register"
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bitfld.long 0x00 8. "DIRF,QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB" "0: QEI Counter is in down-counting,1: QEI Counter is in up-counting"
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bitfld.long 0x00 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed" "0: No change in QEI counter counting direction,1: QEI counter counting direction is changed"
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newline
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bitfld.long 0x00 2. "OVUNF,QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode" "0: No overflow or underflow occurs in QEI counter,1: QEI counter occurs counting overflow or.."
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bitfld.long 0x00 1. "CMPF,Compare-match Flag\nIf the QEI compare function is enabled the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it" "0: QEI counter does not match with..,1: QEI counter counts to the same as.."
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newline
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bitfld.long 0x00 0. "IDXF,IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it" "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree "QEI1"
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base ad:0x400B1000
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group.long 0x00++0x03
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line.long 0x00 "QEI_CNT,QEI Counter Register"
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hexmask.long 0x00 0.--31. 1. "CNT,Quadrature Encoder Interface Counter \nA 32-bit up/down counter"
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group.long 0x04++0x03
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line.long 0x00 "QEI_CNTHOLD,QEI Counter Hold Register"
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hexmask.long 0x00 0.--31. 1. "CNTHOLD,Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register"
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group.long 0x08++0x03
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line.long 0x00 "QEI_CNTLATCH,QEI Counter Index Latch Register"
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hexmask.long 0x00 0.--31. 1. "CNTLATCH,Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register"
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group.long 0x0C++0x03
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line.long 0x00 "QEI_CNTCMP,QEI Counter Compare Register"
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hexmask.long 0x00 0.--31. 1. "CNTCMP,Quadrature Encoder Interface Counter Compare"
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group.long 0x14++0x03
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line.long 0x00 "QEI_CNTMAX,QEI Pre-set Maximum Count Register"
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hexmask.long 0x00 0.--31. 1. "CNTMAX,Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode"
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group.long 0x18++0x03
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line.long 0x00 "QEI_CTL,QEI Controller Control Register"
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bitfld.long 0x00 29. "QEIEN,Quadrature Encoder Interface Controller Enable Bit" "0: QEI controller function Disabled,1: QEI controller function Enabled"
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bitfld.long 0x00 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]) if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]) the flag CMPF will be set" "0: Compare function Disabled,1: Compare function Enabled"
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newline
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bitfld.long 0x00 27. "IDXRLDEN,Index Trigger QEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: QEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x00 25. "IDXLATEN,Index Latch QEI_CNT Enable Bit\nIf this bit is set to high the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX" "0: The index signal latch QEI counter function..,1: The index signal latch QEI counter function.."
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newline
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bitfld.long 0x00 24. "HOLDCNT,Hold QEI_CNT Control\nWhen this bit is set from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])" "0: No operation,1: QEI_CNT content is captured and stored in.."
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bitfld.long 0x00 23. "HOLDTMR3,Hold QEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x00 22. "HOLDTMR2,Hold QEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x00 21. "HOLDTMR1,Hold QEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]).."
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newline
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bitfld.long 0x00 20. "HOLDTMR0,Hold QEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x00 19. "IDXIEN,IDXF Trigger QEI Interrupt Enable Bit" "0: The IDXF can trigger QEI interrupt Disabled,1: The IDXF can trigger QEI interrupt Enabled"
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newline
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bitfld.long 0x00 18. "CMPIEN,CMPF Trigger QEI Interrupt Enable Bit" "0: CMPF can trigger QEI controller interrupt..,1: CMPF can trigger QEI controller interrupt.."
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bitfld.long 0x00 17. "DIRIEN,DIRCHGF Trigger QEI Interrupt Enable Bit" "0: DIRCHGF can trigger QEI controller interrupt..,1: DIRCHGF can trigger QEI controller interrupt.."
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newline
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bitfld.long 0x00 16. "OVUNIEN,OVUNF Trigger QEI Interrupt Enable Bit" "0: OVUNF can trigger QEI controller interrupt..,1: OVUNF can trigger QEI controller interrupt.."
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bitfld.long 0x00 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to QEI.."
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bitfld.long 0x00 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 8.--9. "MODE,QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes" "0: X4 Free-counting Mode,1: X2 Free-counting Mode,2: X4 Compare-counting Mode,3: X2 Compare-counting Mode"
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bitfld.long 0x00 6. "IDXEN,IDX Input to QEI Controller Enable Bit" "0: IDX input to QEI Controller Disabled,1: IDX input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 5. "CHBEN,QEB Input to QEI Controller Enable Bit" "0: QEB input to QEI Controller Disabled,1: QEB input to QEI Controller Enabled"
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bitfld.long 0x00 4. "CHAEN,QEA Input to QEI Controller Enable Bit" "0: QEA input to QEI Controller Disabled,1: QEA input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 3. "NFDIS,QEI Controller Input Noise Filter Disable Bit" "0: The noise filter of QEI controller Enabled,1: The noise filter of QEI controller Disabled"
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: QEI_CLK,1: QEI_CLK/2,2: QEI_CLK/4,3: QEI_CLK/16,4: QEI_CLK/32,5: QEI_CLK/64,?..."
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group.long 0x2C++0x03
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line.long 0x00 "QEI_STATUS,QEI Controller Status Register"
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bitfld.long 0x00 8. "DIRF,QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB" "0: QEI Counter is in down-counting,1: QEI Counter is in up-counting"
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bitfld.long 0x00 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed" "0: No change in QEI counter counting direction,1: QEI counter counting direction is changed"
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newline
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bitfld.long 0x00 2. "OVUNF,QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode" "0: No overflow or underflow occurs in QEI counter,1: QEI counter occurs counting overflow or.."
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bitfld.long 0x00 1. "CMPF,Compare-match Flag\nIf the QEI compare function is enabled the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it" "0: QEI counter does not match with..,1: QEI counter counts to the same as.."
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newline
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bitfld.long 0x00 0. "IDXF,IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it" "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree "QEI1_NS"
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base ad:0x500B1000
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group.long 0x00++0x03
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line.long 0x00 "QEI_CNT,QEI Counter Register"
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hexmask.long 0x00 0.--31. 1. "CNT,Quadrature Encoder Interface Counter \nA 32-bit up/down counter"
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group.long 0x04++0x03
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line.long 0x00 "QEI_CNTHOLD,QEI Counter Hold Register"
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hexmask.long 0x00 0.--31. 1. "CNTHOLD,Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register"
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group.long 0x08++0x03
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line.long 0x00 "QEI_CNTLATCH,QEI Counter Index Latch Register"
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hexmask.long 0x00 0.--31. 1. "CNTLATCH,Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register"
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group.long 0x0C++0x03
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line.long 0x00 "QEI_CNTCMP,QEI Counter Compare Register"
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hexmask.long 0x00 0.--31. 1. "CNTCMP,Quadrature Encoder Interface Counter Compare"
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group.long 0x14++0x03
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line.long 0x00 "QEI_CNTMAX,QEI Pre-set Maximum Count Register"
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hexmask.long 0x00 0.--31. 1. "CNTMAX,Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode"
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group.long 0x18++0x03
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line.long 0x00 "QEI_CTL,QEI Controller Control Register"
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bitfld.long 0x00 29. "QEIEN,Quadrature Encoder Interface Controller Enable Bit" "0: QEI controller function Disabled,1: QEI controller function Enabled"
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bitfld.long 0x00 28. "CMPEN,The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]) if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]) the flag CMPF will be set" "0: Compare function Disabled,1: Compare function Enabled"
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bitfld.long 0x00 27. "IDXRLDEN,Index Trigger QEI_CNT Reload Enable Bit" "0: Reload function Disabled,1: QEI_CNT re-initialized by Index signal Enabled"
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bitfld.long 0x00 25. "IDXLATEN,Index Latch QEI_CNT Enable Bit\nIf this bit is set to high the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX" "0: The index signal latch QEI counter function..,1: The index signal latch QEI counter function.."
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newline
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bitfld.long 0x00 24. "HOLDCNT,Hold QEI_CNT Control\nWhen this bit is set from low to high the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0])" "0: No operation,1: QEI_CNT content is captured and stored in.."
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bitfld.long 0x00 23. "HOLDTMR3,Hold QEI_CNT by Timer 3" "0: TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER3_INTSTS[0]) in.."
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newline
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bitfld.long 0x00 22. "HOLDTMR2,Hold QEI_CNT by Timer 2" "0: TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER2_INTSTS[0]) in.."
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bitfld.long 0x00 21. "HOLDTMR1,Hold QEI_CNT by Timer 1" "0: TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF (TIMER1_INTSTS[0]).."
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newline
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bitfld.long 0x00 20. "HOLDTMR0,Hold QEI_CNT by Timer 0" "0: TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT,1: A rising edge of bit TIF(TIMER0_INTSTS[0]) in.."
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bitfld.long 0x00 19. "IDXIEN,IDXF Trigger QEI Interrupt Enable Bit" "0: The IDXF can trigger QEI interrupt Disabled,1: The IDXF can trigger QEI interrupt Enabled"
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newline
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bitfld.long 0x00 18. "CMPIEN,CMPF Trigger QEI Interrupt Enable Bit" "0: CMPF can trigger QEI controller interrupt..,1: CMPF can trigger QEI controller interrupt.."
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bitfld.long 0x00 17. "DIRIEN,DIRCHGF Trigger QEI Interrupt Enable Bit" "0: DIRCHGF can trigger QEI controller interrupt..,1: DIRCHGF can trigger QEI controller interrupt.."
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newline
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bitfld.long 0x00 16. "OVUNIEN,OVUNF Trigger QEI Interrupt Enable Bit" "0: OVUNF can trigger QEI controller interrupt..,1: OVUNF can trigger QEI controller interrupt.."
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bitfld.long 0x00 14. "IDXINV,Inverse IDX Input Polarity" "0: Not inverse IDX input polarity,1: IDX input polarity is inversed to QEI.."
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bitfld.long 0x00 13. "CHBINV,Inverse QEB Input Polarity" "0: Not inverse QEB input polarity,1: QEB input polarity is inversed to QEI.."
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bitfld.long 0x00 12. "CHAINV,Inverse QEA Input Polarity" "0: Not inverse QEA input polarity,1: QEA input polarity is inversed to QEI.."
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newline
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bitfld.long 0x00 8.--9. "MODE,QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes" "0: X4 Free-counting Mode,1: X2 Free-counting Mode,2: X4 Compare-counting Mode,3: X2 Compare-counting Mode"
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bitfld.long 0x00 6. "IDXEN,IDX Input to QEI Controller Enable Bit" "0: IDX input to QEI Controller Disabled,1: IDX input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 5. "CHBEN,QEB Input to QEI Controller Enable Bit" "0: QEB input to QEI Controller Disabled,1: QEB input to QEI Controller Enabled"
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bitfld.long 0x00 4. "CHAEN,QEA Input to QEI Controller Enable Bit" "0: QEA input to QEI Controller Disabled,1: QEA input to QEI Controller Enabled"
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newline
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bitfld.long 0x00 3. "NFDIS,QEI Controller Input Noise Filter Disable Bit" "0: The noise filter of QEI controller Enabled,1: The noise filter of QEI controller Disabled"
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bitfld.long 0x00 0.--2. "NFCLKSEL,Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock" "0: QEI_CLK,1: QEI_CLK/2,2: QEI_CLK/4,3: QEI_CLK/16,4: QEI_CLK/32,5: QEI_CLK/64,?..."
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group.long 0x2C++0x03
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line.long 0x00 "QEI_STATUS,QEI Controller Status Register"
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bitfld.long 0x00 8. "DIRF,QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB" "0: QEI Counter is in down-counting,1: QEI Counter is in up-counting"
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bitfld.long 0x00 3. "DIRCHGF,Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed" "0: No change in QEI counter counting direction,1: QEI counter counting direction is changed"
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newline
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bitfld.long 0x00 2. "OVUNF,QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode" "0: No overflow or underflow occurs in QEI counter,1: QEI counter occurs counting overflow or.."
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bitfld.long 0x00 1. "CMPF,Compare-match Flag\nIf the QEI compare function is enabled the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it" "0: QEI counter does not match with..,1: QEI counter counts to the same as.."
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newline
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bitfld.long 0x00 0. "IDXF,IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it" "0: No rising edge detected on signal CHX,1: A rising edge occurs on signal CHX"
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tree.end
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tree.end
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tree "QSPI"
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tree "QSPI0"
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base ad:0x40060000
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group.long 0x00++0x03
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line.long 0x00 "QSPIx_CTL,QSPI Control Register"
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bitfld.long 0x00 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x00 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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newline
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data" "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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newline
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bitfld.long 0x00 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer" "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the QSPIx TX register is.."
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newline
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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newline
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "QSPIx_CLKDIV,QSPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the QSPI bus clock of QSPI Master"
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group.long 0x08++0x03
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line.long 0x00 "QSPIx_SSCTL,QSPI Slave Select Control Register"
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hexmask.long.word 0x00 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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newline
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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newline
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX..,1: When Slave mode time-out event occurs the TX.."
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newline
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bitfld.long 0x00 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x00 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the QSPI controller can work with 3-wire interface including QSPIx_CLK QSPIx_MISO and SPIx_MOSI pins" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)" "0: The slave selection signal QSPIx_SS is active..,1: The slave selection signal QSPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the QSPIx_SS line to inactive..,1: set the QSPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "QSPIx_PDMACTL,QSPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (QSPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The QSPI data out is keep 0 if there is TX..,1: The QSPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "QSPIx_STATUS,QSPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock" "0: QSPI controller Disabled,1: QSPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in QSPI controller logic will be started" "0: Slave time-out is not active,1: Slave time-out is active"
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newline
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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newline
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: QSPI controller has finished one unit transfer"
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newline
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
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wgroup.long 0x20++0x03
|
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line.long 0x00 "QSPIx_TX,QSPI Data Transmit Register"
|
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers"
|
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rgroup.long 0x30++0x03
|
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line.long 0x00 "QSPIx_RX,QSPI Data Receive Register"
|
|
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller"
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tree.end
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tree "QSPI0_NS"
|
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base ad:0x50060000
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group.long 0x00++0x03
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line.long 0x00 "QSPIx_CTL,QSPI Control Register"
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bitfld.long 0x00 22. "QUADIOEN,Quad I/O Mode Enable Bit" "0: Quad I/O mode Disabled,1: Quad I/O mode Enabled"
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bitfld.long 0x00 21. "DUALIOEN,Dual I/O Mode Enable Bit" "0: Dual I/O mode Disabled,1: Dual I/O mode Enabled"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: QSPI data is input direction,1: QSPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: QSPI unit transfer interrupt Disabled,1: QSPI unit transfer interrupt Enabled"
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bitfld.long 0x00 16. "TWOBIT,2-bit Transfer Mode Enable Bit\nNote: When 2-bit Transfer mode is enabled the first serial transmitted bit data is from the first FIFO buffer data and the 2nd serial transmitted bit data is from the second FIFO buffer data" "0: 2-bit Transfer mode Disabled,1: 2-bit Transfer mode Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,QSPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for QSPI transfer" "0: QSPI operates in full-duplex transfer,1: QSPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the QSPIx TX register is.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: QSPI bus clock is idle low,1: QSPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,QSPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "QSPIx_CLKDIV,QSPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the QSPI bus clock of QSPI Master"
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group.long 0x08++0x03
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line.long 0x00 "QSPIx_SSCTL,QSPI Slave Select Control Register"
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hexmask.long.word 0x00 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period\nIn Slave mode these bits indicate the time-out period when there is bus clock input during slave select active"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 6. "SLVTORST,Slave Mode Time-out Reset Control" "0: When Slave mode time-out event occurs the TX..,1: When Slave mode time-out event occurs the TX.."
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bitfld.long 0x00 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Bit" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
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bitfld.long 0x00 4. "SLV3WIRE,Slave 3-wire Mode Enable Bit\nIn Slave 3-wire mode the QSPI controller can work with 3-wire interface including QSPIx_CLK QSPIx_MISO and SPIx_MOSI pins" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (QSPIx_SS)" "0: The slave selection signal QSPIx_SS is active..,1: The slave selection signal QSPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the QSPIx_SS line to inactive..,1: set the QSPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "QSPIx_PDMACTL,QSPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the QSPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In QSPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "QSPIx_FIFOCTL,QSPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (QSPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The QSPI data out is keep 0 if there is TX..,1: The QSPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in QSPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "QSPIx_STATUS,QSPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,QSPI Enable Status (Read Only)\nNote: The QSPI peripheral clock is asynchronous with the system clock" "0: QSPI controller Disabled,1: QSPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag \nWhen the slave select is active and the value of SLVTOCNT is not 0 as the bus clock is detected the slave time-out counter in QSPI controller logic will be started" "0: Slave time-out is not active,1: Slave time-out is active"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: QSPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: QSPI controller is in idle state,1: QSPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "QSPIx_TX,QSPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "QSPIx_RX,QSPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 8-level FIFO buffers in this controller"
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tree.end
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tree.end
|
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tree "RTC"
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tree "RTC"
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base ad:0x40041000
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group.long 0x00++0x03
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line.long 0x00 "RTC_INIT,RTC Initiation Register"
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hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation\nWhen RTC block is powered on RTC is at reset state"
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rbitfld.long 0x00 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
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rgroup.long 0x04++0x03
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line.long 0x00 "RTC_RWEN,RTC Access Enable Register"
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bitfld.long 0x00 24. "RTCBUSY,RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not" "0: RTC registers are writable,1: RTC registers can't be written"
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bitfld.long 0x00 16. "RWENF,RTC Register Access Enable Flag (Read Only)\nNote: RWENF will be masked to 0 during RTCBUSY is 1" "0: RTC register read/write Disabled,1: RTC register read/write Enabled"
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group.long 0x08++0x03
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line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
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hexmask.long.tbyte 0x00 0.--21. 1. "FREQADJ,Frequency Compensation Register\nUser must to get actual LXT frequency for RTC application"
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group.long 0x0C++0x03
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line.long 0x00 "RTC_TIME,RTC Time Loading Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x14++0x03
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line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
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bitfld.long 0x00 8. "HZCNTEN,Sub-second Counter Enable Bit" "0: HZCNT disabled in RTC_TIME and RTC_TALM,1: HZCNT enabled in RTC_TIME and RTC_TALM"
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bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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group.long 0x18++0x03
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line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
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group.long 0x1C++0x03
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line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x20++0x03
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line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
|
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x24++0x03
|
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line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
|
|
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
|
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group.long 0x28++0x03
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line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
|
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bitfld.long 0x00 25. "CLKSTOPIEN,LXT Clock Frequency Monitor STOP Interrupt Enable Bit" "0: LXT Frequency Fail interrupt Disabled,1: LXT Frequency Fail interrupt Enabled"
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bitfld.long 0x00 24. "CLKFIEN,LXT Clock Frequency Monitor Fail Interrupt Enable Bit" "0: LXT Frequency Stop interrupt Disabled,1: LXT Frequency Stop interrupt Enabled"
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newline
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bitfld.long 0x00 13. "TAMP5IEN,Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated" "0: Tamper 5 or Pair 2 interrupt Disabled,1: Tamper 5 or Pair 2 interrupt Enabled"
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bitfld.long 0x00 12. "TAMP4IEN,Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated" "0: Tamper 4 interrupt Disabled,1: Tamper 4 interrupt Enabled"
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bitfld.long 0x00 11. "TAMP3IEN,Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated" "0: Tamper 3 or Pair 1 interrupt Disabled,1: Tamper 3 or Pair 1 interrupt Enabled"
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bitfld.long 0x00 10. "TAMP2IEN,Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated" "0: Tamper 2 interrupt Disabled,1: Tamper 2 interrupt Enabled"
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bitfld.long 0x00 9. "TAMP1IEN,Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated" "0: Tamper 1 or Pair 0 interrupt Disabled,1: Tamper 1 or Pair 0 interrupt Enabled"
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bitfld.long 0x00 8. "TAMP0IEN,Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated" "0: Tamper 0 interrupt Disabled,1: Tamper 0 interrupt Enabled"
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bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
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bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
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group.long 0x2C++0x03
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line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
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bitfld.long 0x00 25. "CLKSPIF,LXT Clock Frequency Monitor STOP Interrupt Flag\nNote1: Write 1 to clear the bit to 0" "0: LXT frequency is normal,1: LXT frequency is almost stop"
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bitfld.long 0x00 24. "CLKFIF,LXT Clock Frequency Monitor Fail Interrupt Flag\nNote1: Write 1 to clear the bit to 0" "0: LXT frequency is normal,1: LXT frequency is abnormal"
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bitfld.long 0x00 13. "TAMP5IF,Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected.." "0: No Tamper 5 or Pair 2 interrupt flag is..,1: Tamper 5 or Pair 2 interrupt flag is generated"
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bitfld.long 0x00 12. "TAMP4IF,Tamper 4 Interrupt Flag\nThis bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not.." "0: No Tamper 4 interrupt flag is generated,1: Tamper 4 interrupt flag is generated"
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bitfld.long 0x00 11. "TAMP3IF,Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected.." "0: No Tamper 3 or Pair 1 interrupt flag is..,1: Tamper 3 or Pair 1 interrupt flag is generated"
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bitfld.long 0x00 10. "TAMP2IF,Tamper 2 Interrupt Flag\nThis bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate agan when Tamper setting condition is not.." "0: No Tamper 2 interrupt flag is generated,1: Tamper 2 interrupt flag is generated"
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bitfld.long 0x00 9. "TAMP1IF,Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote1: Write 1 to clear this.." "0: No Tamper 1 or Pair 0 interrupt flag is..,1: Tamper 1 or Pair 0 interrupt flag is generated"
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bitfld.long 0x00 8. "TAMP0IF,Tamper 0 Interrupt Flag\nThis bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not.." "0: No Tamper 0 interrupt flag is generated,1: Tamper 0 interrupt flag is generated"
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bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit" "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit" "0: Alarm condition is not matched,1: Alarm condition is matched"
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group.long 0x30++0x03
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line.long 0x00 "RTC_TICK,RTC Time Tick Register"
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bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
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group.long 0x34++0x03
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line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
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bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
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bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
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bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
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bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x3C++0x03
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line.long 0x00 "RTC_SPRCTL,RTC Spare Functional Control Register"
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bitfld.long 0x00 16. "LXTFCLR,LXT Clock Fail/Stop to Clear Spare Enable Bit" "0: LXT Fail/Stop to clear Spare register content..,1: LXT Fail/Stop to clear Spare register content.."
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bitfld.long 0x00 5. "SPRCSTS,SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0" "0: Spare register content is not cleared,1: Spare register content is cleared"
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bitfld.long 0x00 2. "SPRRWEN,Spare Register Enable Bit\nNote: When spare register is disabled RTC_SPR0 ~ RTC_SPR19 cannot be accessed" "0: Spare register Disabled,1: Spare register Enabled"
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group.long 0x40++0x03
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line.long 0x00 "RTC_SPR0,RTC Spare Register 0"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x44++0x03
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line.long 0x00 "RTC_SPR1,RTC Spare Register 1"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x48++0x03
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line.long 0x00 "RTC_SPR2,RTC Spare Register 2"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x4C++0x03
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line.long 0x00 "RTC_SPR3,RTC Spare Register 3"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x50++0x03
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line.long 0x00 "RTC_SPR4,RTC Spare Register 4"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x54++0x03
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line.long 0x00 "RTC_SPR5,RTC Spare Register 5"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x58++0x03
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line.long 0x00 "RTC_SPR6,RTC Spare Register 6"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x5C++0x03
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line.long 0x00 "RTC_SPR7,RTC Spare Register 7"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x60++0x03
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line.long 0x00 "RTC_SPR8,RTC Spare Register 8"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x64++0x03
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line.long 0x00 "RTC_SPR9,RTC Spare Register 9"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x68++0x03
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line.long 0x00 "RTC_SPR10,RTC Spare Register 10"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x6C++0x03
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line.long 0x00 "RTC_SPR11,RTC Spare Register 11"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x70++0x03
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line.long 0x00 "RTC_SPR12,RTC Spare Register 12"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x74++0x03
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line.long 0x00 "RTC_SPR13,RTC Spare Register 13"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x78++0x03
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line.long 0x00 "RTC_SPR14,RTC Spare Register 14"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x7C++0x03
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line.long 0x00 "RTC_SPR15,RTC Spare Register 15"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x80++0x03
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line.long 0x00 "RTC_SPR16,RTC Spare Register 16"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x84++0x03
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line.long 0x00 "RTC_SPR17,RTC Spare Register 17"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x88++0x03
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line.long 0x00 "RTC_SPR18,RTC Spare Register 18"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x8C++0x03
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line.long 0x00 "RTC_SPR19,RTC Spare Register 19"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x100++0x03
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line.long 0x00 "RTC_LXTCTL,RTC 32.768 KHz Oscillator Control Register"
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bitfld.long 0x00 14. "RTCPORPD,RTC Power on Reset Power Down\nNote:This bit only can be set to 1" "0: RTC POR active 1sec after first power up,1: RTC POR enter power down"
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bitfld.long 0x00 13. "RTCLVDPD,RTC Low Voltage Detector Power Down" "0: RTC Low Voltage Detector active,1: RTC Low Voltage Detector enter power down"
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bitfld.long 0x00 8.--9. "LVRDGSEL,LVR Output De-glitch Time Select \nNote: These bits are write protected" "0,1,2,3"
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bitfld.long 0x00 7. "C32KS,Clock 32K Source Selection" "0: Internal 32K clock is from 32K crystal,1: Internal 32K clock is from LIRC32K"
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bitfld.long 0x00 1.--2. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range" "0: L0 mode,1: L1 mode,2: L2 mode,3: L3 mode(Default)"
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bitfld.long 0x00 0. "LIRC32KEN,Enable LIRC 32K Source" "0: LIRC32K Disabled,1: LIRC32K Enabled"
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group.long 0x104++0x03
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line.long 0x00 "RTC_GPIOCTL0,RTC GPIO Control 0 Register"
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bitfld.long 0x00 28.--29. "PUSEL3,IO Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.7 pull-up and pull-down disabled,1: PF.7 pull-up enabled,2: PF.7 pull-down enabled,3: PF.7 pull-up and pull-down disabled"
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bitfld.long 0x00 27. "CTLSEL3,IO Pin State Backup Selection\nWhen TAMP1EN is disabled PF.7 pin (TAMPER1 pin) can be used as GPIO function" "0: PF.7 pin I/O function is controlled by GPIO..,1: PF.7 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 26. "DOUT3,IO Output Data" "0: PF.7 output low,1: PF.7 output high"
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bitfld.long 0x00 24.--25. "OPMODE3,IO Operation Mode" "0: PF.7 is input only mode,1: PF.7 is output push pull mode,2: PF.7 is open drain mode,3: PF.7 is quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "PUSEL2,IO Pull-up and Pull-down Enable Bits\nDetermine PF.6 I/O pull-up or pull-down.\nNote1:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.6 pull-up and pull-down disabled,1: PF.6 pull-up enabled,2: PF.6 pull-down enabled,3: PF.6 pull-up and pull-down disabled"
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bitfld.long 0x00 19. "CTLSEL2,IO Pin State Backup Selection\nWhen TAMP0EN is disabled PF.6 pin (TAMPER0 pin) can be used as GPIO function" "0: PF.6 pin I/O function is controlled by GPIO..,1: PF.6 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 18. "DOUT2,IO Output Data" "0: PF.6 output low,1: PF.6 output high"
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bitfld.long 0x00 16.--17. "OPMODE2,IO Operation Mode" "0: PF.6 is input only mode,1: PF.6 is output push pull mode,2: PF.6 is open drain mode,3: PF.6 is quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "PUSEL1,IO Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pullOpull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid.." "0: PF.5 pull-up and pull-down disabled,1: PF.5 pull-up enabled,2: PF.5 pull-down enabled,3: PF.5 pull-up and pull-down disabled"
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bitfld.long 0x00 11. "CTLSEL1,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled PF.5 pin (X32KI pin) can be used as GPIO function" "0: PF.5 pin I/O function is controlled by GPIO..,1: PF.5 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 10. "DOUT1,IO Output Data" "0: PF.5 output low,1: PF.5 output high"
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bitfld.long 0x00 8.--9. "OPMODE1,IO Operation Mode" "0: PF.5 is input only mode,1: PF.5 is output push pull mode,2: PF.5 is open drain mode,3: PF.5 is quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "PUSEL0,IO Pull-up and Pull-down \nDetermine PF.4 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE0 set.." "0: PF.4 pull-up and pull-down disabled,1: PF.4 pull-up enabled,2: PF.4 pull-down enabled,3: PF.4 pull-up and pull-down disabled"
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bitfld.long 0x00 3. "CTLSEL0,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled PF.4 pin (X32KO pin) can be used as GPIO function" "0: PF.4 pin I/O function is controlled by GPIO..,1: PF.4 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 2. "DOUT0,IO Output Data" "0: PF.4 output low,1: PF.4 output high"
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bitfld.long 0x00 0.--1. "OPMODE0,IO Operation Mode" "0: PF.4 is input only mode,1: PF.4 is output push pull mode,2: PF.4 is open drain mode,3: PF.4 is quasi-bidirectional mode"
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group.long 0x108++0x03
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line.long 0x00 "RTC_GPIOCTL1,RTC GPIO Control 1 Register"
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bitfld.long 0x00 28.--29. "PUSEL7,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.11 pull-up and pull-down disabled,1: PF.11 pull-up enabled,2: PF.11 pull-down enabled,3: PF.11 pull-up and pull-down disabled"
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bitfld.long 0x00 27. "CTLSEL7,I/O Pin State Backup Selection\nWhen TAMP5EN is disabled PF.11 pin (TAMPER5 pin) can be used as GPIO function" "0: PF.11 pin I/O function is controlled by GPIO..,1: PF.11 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 26. "DOUT7,I/O Output Data" "0: PF.11 output low,1: PF.11 output high"
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bitfld.long 0x00 24.--25. "OPMODE7,I/O Operation Mode" "0: PF.11 is input only mode,1: PF.11 is output push pull mode,2: PF.11 is open drain mode,3: PF.11 is quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "PUSEL6,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.10 pull-up and pull-down disabled,1: PF.10 pull-up enabled,2: PF.10 pull-down enabled,3: PF.10 pull-up and pull-down disabled"
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bitfld.long 0x00 19. "CTLSEL6,I/O Pin State Backup Selection\nWhen TAMP4EN is disabled PF.10 pin (TAMPER4 pin) can be used as GPIO function" "0: PF.10 pin I/O function is controlled by GPIO..,1: PF.10 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 18. "DOUT6,I/O Output Data" "0: PF.10 output low,1: PF.10 output high"
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bitfld.long 0x00 16.--17. "OPMODE6,I/O Operation Mode" "0: PF.10 is input only mode,1: PF.10 is output push pull mode,2: PF.10 is open drain mode,3: PF.10 is quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "PUSEL5,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.9 pull-up and pull-down disabled,1: PF.9 pull-up enabled,2: PF.9 pull-down enabled,3: PF.9 pull-up and pull-down disabled"
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bitfld.long 0x00 11. "CTLSEL5,I/O Pin State Backup Selection\nWhen TAMP3EN is disabled PF.9 pin (TAMPER3 pin) can be used as GPIO function" "0: PF.9 pin I/O function is controlled by GPIO..,1: PF.9 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 10. "DOUT5,I/O Output Data" "0: PF.9 output low,1: PF.9 output high"
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bitfld.long 0x00 8.--9. "OPMODE5,I/O Operation Mode" "0: PF.9 is input only mode,1: PF.9 is output push pull mode,2: PF.9 is open drain mode,3: PF.9 is quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "PUSEL4,I/O Pull-up and Pull-down \nDetermine PF.8 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE4 set.." "0: PF.8 pull-up and pull-down disabled,1: PF.8 pull-up enabled,2: PF.8 pull-down enabled,3: PF.8 pull-up and pull-down disabled"
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bitfld.long 0x00 3. "CTLSEL4,I/O Pin State Backup Selection\nWhen TAMP2EN is disabled PF.8 pin (TAMPER2 pin) can be used as GPIO function" "0: PF.8 pin I/O function is controlled by GPIO..,1: PF.8 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 2. "DOUT4,I/O Output Data" "0: PF.8 output low,1: PF.8 output high"
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bitfld.long 0x00 0.--1. "OPMODE4,I/O Operation Mode" "0: PF.8 is input only mode,1: PF.8 is output push pull mode,2: PF.8 is open drain mode,3: PF.8 is quasi-bidirectional mode"
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group.long 0x110++0x03
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line.long 0x00 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
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bitfld.long 0x00 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
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bitfld.long 0x00 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted.."
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bitfld.long 0x00 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one.."
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group.long 0x120++0x03
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line.long 0x00 "RTC_TAMPCTL,RTC Tamper Pin Control Register"
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bitfld.long 0x00 31. "DYNPR2EN,Dynamic Pair 2 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 30. "TAMP5DBEN,Tamper 5 De-bounce Enable Bit" "0: Tamper 5 de-bounce Disabled,1: Tamper 5 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 29. "TAMP5LV,Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 28. "TAMP5EN,Tamper 5 Detect Enable Bit\nNote: The reference is RTC-clock" "0: Tamper 5 detect Disabled,1: Tamper 5 detect Enabled"
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bitfld.long 0x00 26. "TAMP4DBEN,Tamper 4 De-bounce Enable Bit" "0: Tamper 4 de-bounce Disabled,1: Tamper 4 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 25. "TAMP4LV,Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 24. "TAMP4EN,Tamper4 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 4 detect Disabled,1: Tamper 4 detect Enabled"
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bitfld.long 0x00 23. "DYNPR1EN,Dynamic Pair 1 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 22. "TAMP3DBEN,Tamper 3 De-bounce Enable Bit" "0: Tamper 3 de-bounce Disabled,1: Tamper 3 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 21. "TAMP3LV,Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 20. "TAMP3EN,Tamper 3 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 3 detect Disabled,1: Tamper 3 detect Enabled"
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bitfld.long 0x00 18. "TAMP2DBEN,Tamper 2 De-bounce Enable Bit" "0: Tamper 2 de-bounce Disabled,1: Tamper 2 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 17. "TAMP2LV,Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 16. "TAMP2EN,Tamper 2 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 2 detect Disabled,1: Tamper 2 detect Enabled"
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bitfld.long 0x00 15. "DYNPR0EN,Dynamic Pair 0 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 14. "TAMP1DBEN,Tamper 1 De-bounce Enable Bit" "0: Tamper 1 de-bounce Disabled,1: Tamper 1 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 13. "TAMP1LV,Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 12. "TAMP1EN,Tamper 1 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 1 detect Disabled,1: Tamper 1 detect Enabled"
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bitfld.long 0x00 10. "TAMP0DBEN,Tamper 0 De-bounce Enable Bit" "0: Tamper 0 de-bounce Disabled,1: Tamper 0 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 9. "TAMP0LV,Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 8. "TAMP0EN,Tamper0 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 0 detect Disabled,1: Tamper 0 detect Enabled"
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bitfld.long 0x00 5.--7. "DYNRATE,Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately" "0: 210 * RTC_CLK,1: 211 * RTC_CLK,2: 212 * RTC_CLK,3: 213 * RTC_CLK,4: 214 * RTC_CLK,5: 215 * RTC_CLK,6: 216 * RTC_CLK,7: 217 * RTC_CLK"
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bitfld.long 0x00 4. "SEEDRLD,Reload New Seed for PRNG Engine\nSetting this bit the tamper configuration will be reload.\nNote: Before this bit is set the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed" "0: Generating key based on the current seed,1: Reload new seed"
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bitfld.long 0x00 2.--3. "DYNSRC,Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified the SEEDRLD (RTC_TAMPCTL[4]) should be set" "?,1: The new reference pattern is repeated..,?,3: The new reference pattern is repeated from.."
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bitfld.long 0x00 1. "DYN2ISS,Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set" "0: Tamper input is from Tamper 4,1: Tamper input is from Tamper 0"
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bitfld.long 0x00 0. "DYN1ISS,Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set" "0: Tamper input is from Tamper 2,1: Tamper input is from Tamper 0"
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group.long 0x128++0x03
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line.long 0x00 "RTC_TAMPSEED,RTC Tamper Dynamic Seed Register"
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hexmask.long 0x00 0.--31. 1. "SEED,Seed Value"
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rgroup.long 0x130++0x03
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line.long 0x00 "RTC_TAMPTIME,RTC Tamper Time Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of TAMPER Time (0~2)Note: 24-hour time scale only" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x134++0x03
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line.long 0x00 "RTC_TAMPCAL,RTC Tamper Calendar Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of TAMPER Calendar (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of TAMPER Calendar (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x140++0x03
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line.long 0x00 "RTC_CLKDCTL,Clock Fail Detector Control Register"
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rbitfld.long 0x00 17. "LXTSLOWF,LXT Slower Than LIRC32K Flag (Read Only ) \nNote: LXTSLOWF is vaild during CLKSPIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising" "0: 32.768 kHz external low speed crystal..,1: LXT frequency is slowly"
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rbitfld.long 0x00 16. "CLKSWLIRCF,LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)" "0: RTC clock source from LXT,1: RTC clock source from LIRC32K"
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bitfld.long 0x00 2. "LXTSPSW,LXT Clock Stop Detector Switch LIRC32K Enable Bit" "0: LXT clock Stop switch LIRC32K Disabled,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 1. "LXTFSW,LXT Clock Fail Detector Switch LIRC32K Enable Bit" "0: LXT clock Fail switch LIRC32K Disabled,1: 32.768 kHz external low speed crystal.."
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newline
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bitfld.long 0x00 0. "LXTFDEN,LXT Clock Fail/Stop Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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group.long 0x144++0x03
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line.long 0x00 "RTC_CDBR,Clock Frequency Detector Boundary Register"
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hexmask.long.byte 0x00 16.--23. 1. "FAILBD,LXT Clock Frequency Detector FAIL Boundary\nThe bits define the fail value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary the LXT frequency detect fail interrupt flag will set to.."
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hexmask.long.byte 0x00 0.--7. 1. "STOPBD,LXT Clock Stop Frequency Detector Stop Boundary\nThe bits define the stop value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary the LXT frequency detect Stop interrupt flag will.."
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tree.end
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tree "RTC_NS"
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base ad:0x50041000
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group.long 0x00++0x03
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line.long 0x00 "RTC_INIT,RTC Initiation Register"
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hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation\nWhen RTC block is powered on RTC is at reset state"
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rbitfld.long 0x00 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
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rgroup.long 0x04++0x03
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line.long 0x00 "RTC_RWEN,RTC Access Enable Register"
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bitfld.long 0x00 24. "RTCBUSY,RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not" "0: RTC registers are writable,1: RTC registers can't be written"
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bitfld.long 0x00 16. "RWENF,RTC Register Access Enable Flag (Read Only)\nNote: RWENF will be masked to 0 during RTCBUSY is 1" "0: RTC register read/write Disabled,1: RTC register read/write Enabled"
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group.long 0x08++0x03
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line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
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hexmask.long.tbyte 0x00 0.--21. 1. "FREQADJ,Frequency Compensation Register\nUser must to get actual LXT frequency for RTC application"
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group.long 0x0C++0x03
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line.long 0x00 "RTC_TIME,RTC Time Loading Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x14++0x03
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line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
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bitfld.long 0x00 8. "HZCNTEN,Sub-second Counter Enable Bit" "0: HZCNT disabled in RTC_TIME and RTC_TALM,1: HZCNT enabled in RTC_TIME and RTC_TALM"
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bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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group.long 0x18++0x03
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line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
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group.long 0x1C++0x03
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line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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newline
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x20++0x03
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line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x24++0x03
|
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line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicator Register"
|
|
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication (Read Only)" "0: This year is not a leap year,1: This year is leap year"
|
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group.long 0x28++0x03
|
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line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
|
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bitfld.long 0x00 25. "CLKSTOPIEN,LXT Clock Frequency Monitor STOP Interrupt Enable Bit" "0: LXT Frequency Fail interrupt Disabled,1: LXT Frequency Fail interrupt Enabled"
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bitfld.long 0x00 24. "CLKFIEN,LXT Clock Frequency Monitor Fail Interrupt Enable Bit" "0: LXT Frequency Stop interrupt Disabled,1: LXT Frequency Stop interrupt Enabled"
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newline
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bitfld.long 0x00 13. "TAMP5IEN,Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated" "0: Tamper 5 or Pair 2 interrupt Disabled,1: Tamper 5 or Pair 2 interrupt Enabled"
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bitfld.long 0x00 12. "TAMP4IEN,Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated" "0: Tamper 4 interrupt Disabled,1: Tamper 4 interrupt Enabled"
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newline
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bitfld.long 0x00 11. "TAMP3IEN,Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated" "0: Tamper 3 or Pair 1 interrupt Disabled,1: Tamper 3 or Pair 1 interrupt Enabled"
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bitfld.long 0x00 10. "TAMP2IEN,Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated" "0: Tamper 2 interrupt Disabled,1: Tamper 2 interrupt Enabled"
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newline
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bitfld.long 0x00 9. "TAMP1IEN,Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated" "0: Tamper 1 or Pair 0 interrupt Disabled,1: Tamper 1 or Pair 0 interrupt Enabled"
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bitfld.long 0x00 8. "TAMP0IEN,Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated" "0: Tamper 0 interrupt Disabled,1: Tamper 0 interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated" "0: RTC Time Tick interrupt Disabled,1: RTC Time Tick interrupt Enabled"
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bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated" "0: RTC Alarm interrupt Disabled,1: RTC Alarm interrupt Enabled"
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group.long 0x2C++0x03
|
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line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
|
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bitfld.long 0x00 25. "CLKSPIF,LXT Clock Frequency Monitor STOP Interrupt Flag\nNote1: Write 1 to clear the bit to 0" "0: LXT frequency is normal,1: LXT frequency is almost stop"
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bitfld.long 0x00 24. "CLKFIF,LXT Clock Frequency Monitor Fail Interrupt Flag\nNote1: Write 1 to clear the bit to 0" "0: LXT frequency is normal,1: LXT frequency is abnormal"
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bitfld.long 0x00 13. "TAMP5IF,Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected.." "0: No Tamper 5 or Pair 2 interrupt flag is..,1: Tamper 5 or Pair 2 interrupt flag is generated"
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bitfld.long 0x00 12. "TAMP4IF,Tamper 4 Interrupt Flag\nThis bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not.." "0: No Tamper 4 interrupt flag is generated,1: Tamper 4 interrupt flag is generated"
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bitfld.long 0x00 11. "TAMP3IF,Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected.." "0: No Tamper 3 or Pair 1 interrupt flag is..,1: Tamper 3 or Pair 1 interrupt flag is generated"
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bitfld.long 0x00 10. "TAMP2IF,Tamper 2 Interrupt Flag\nThis bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate agan when Tamper setting condition is not.." "0: No Tamper 2 interrupt flag is generated,1: Tamper 2 interrupt flag is generated"
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bitfld.long 0x00 9. "TAMP1IF,Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote1: Write 1 to clear this.." "0: No Tamper 1 or Pair 0 interrupt flag is..,1: Tamper 1 or Pair 0 interrupt flag is generated"
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bitfld.long 0x00 8. "TAMP0IF,Tamper 0 Interrupt Flag\nThis bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote1: Write 1 to clear this bit.\nNote2: This interrupt flag will generate again when Tamper setting condition is not.." "0: No Tamper 0 interrupt flag is generated,1: Tamper 0 interrupt flag is generated"
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bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit" "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit" "0: Alarm condition is not matched,1: Alarm condition is matched"
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group.long 0x30++0x03
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line.long 0x00 "RTC_TICK,RTC Time Tick Register"
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bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
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group.long 0x34++0x03
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line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
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bitfld.long 0x00 5. "MTENHR,Mask 10-Hour Time Digit of Alarm Setting (0~2)" "0,1"
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bitfld.long 0x00 4. "MHR,Mask 1-Hour Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of Alarm Setting (0~5)" "0,1"
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bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x38++0x03
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line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
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bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
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bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of Alarm Setting (0~9)" "0,1"
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of Alarm Setting (0~3)" "0,1"
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bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of Alarm Setting (0~9)" "0,1"
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group.long 0x3C++0x03
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line.long 0x00 "RTC_SPRCTL,RTC Spare Functional Control Register"
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bitfld.long 0x00 16. "LXTFCLR,LXT Clock Fail/Stop to Clear Spare Enable Bit" "0: LXT Fail/Stop to clear Spare register content..,1: LXT Fail/Stop to clear Spare register content.."
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bitfld.long 0x00 5. "SPRCSTS,SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0" "0: Spare register content is not cleared,1: Spare register content is cleared"
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bitfld.long 0x00 2. "SPRRWEN,Spare Register Enable Bit\nNote: When spare register is disabled RTC_SPR0 ~ RTC_SPR19 cannot be accessed" "0: Spare register Disabled,1: Spare register Enabled"
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group.long 0x40++0x03
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line.long 0x00 "RTC_SPR0,RTC Spare Register 0"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x44++0x03
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line.long 0x00 "RTC_SPR1,RTC Spare Register 1"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x48++0x03
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line.long 0x00 "RTC_SPR2,RTC Spare Register 2"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x4C++0x03
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line.long 0x00 "RTC_SPR3,RTC Spare Register 3"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x50++0x03
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line.long 0x00 "RTC_SPR4,RTC Spare Register 4"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x54++0x03
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line.long 0x00 "RTC_SPR5,RTC Spare Register 5"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x58++0x03
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line.long 0x00 "RTC_SPR6,RTC Spare Register 6"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x5C++0x03
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line.long 0x00 "RTC_SPR7,RTC Spare Register 7"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x60++0x03
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line.long 0x00 "RTC_SPR8,RTC Spare Register 8"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x64++0x03
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line.long 0x00 "RTC_SPR9,RTC Spare Register 9"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x68++0x03
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line.long 0x00 "RTC_SPR10,RTC Spare Register 10"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x6C++0x03
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line.long 0x00 "RTC_SPR11,RTC Spare Register 11"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x70++0x03
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line.long 0x00 "RTC_SPR12,RTC Spare Register 12"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x74++0x03
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line.long 0x00 "RTC_SPR13,RTC Spare Register 13"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x78++0x03
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line.long 0x00 "RTC_SPR14,RTC Spare Register 14"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x7C++0x03
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line.long 0x00 "RTC_SPR15,RTC Spare Register 15"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x80++0x03
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line.long 0x00 "RTC_SPR16,RTC Spare Register 16"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x84++0x03
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line.long 0x00 "RTC_SPR17,RTC Spare Register 17"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x88++0x03
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line.long 0x00 "RTC_SPR18,RTC Spare Register 18"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x8C++0x03
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line.long 0x00 "RTC_SPR19,RTC Spare Register 19"
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hexmask.long 0x00 0.--31. 1. "SPARE,Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register user should.."
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group.long 0x100++0x03
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line.long 0x00 "RTC_LXTCTL,RTC 32.768 KHz Oscillator Control Register"
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bitfld.long 0x00 14. "RTCPORPD,RTC Power on Reset Power Down\nNote:This bit only can be set to 1" "0: RTC POR active 1sec after first power up,1: RTC POR enter power down"
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bitfld.long 0x00 13. "RTCLVDPD,RTC Low Voltage Detector Power Down" "0: RTC Low Voltage Detector active,1: RTC Low Voltage Detector enter power down"
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bitfld.long 0x00 8.--9. "LVRDGSEL,LVR Output De-glitch Time Select \nNote: These bits are write protected" "0,1,2,3"
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bitfld.long 0x00 7. "C32KS,Clock 32K Source Selection" "0: Internal 32K clock is from 32K crystal,1: Internal 32K clock is from LIRC32K"
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bitfld.long 0x00 1.--2. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range" "0: L0 mode,1: L1 mode,2: L2 mode,3: L3 mode(Default)"
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bitfld.long 0x00 0. "LIRC32KEN,Enable LIRC 32K Source" "0: LIRC32K Disabled,1: LIRC32K Enabled"
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group.long 0x104++0x03
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line.long 0x00 "RTC_GPIOCTL0,RTC GPIO Control 0 Register"
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bitfld.long 0x00 28.--29. "PUSEL3,IO Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.7 pull-up and pull-down disabled,1: PF.7 pull-up enabled,2: PF.7 pull-down enabled,3: PF.7 pull-up and pull-down disabled"
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bitfld.long 0x00 27. "CTLSEL3,IO Pin State Backup Selection\nWhen TAMP1EN is disabled PF.7 pin (TAMPER1 pin) can be used as GPIO function" "0: PF.7 pin I/O function is controlled by GPIO..,1: PF.7 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 26. "DOUT3,IO Output Data" "0: PF.7 output low,1: PF.7 output high"
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bitfld.long 0x00 24.--25. "OPMODE3,IO Operation Mode" "0: PF.7 is input only mode,1: PF.7 is output push pull mode,2: PF.7 is open drain mode,3: PF.7 is quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "PUSEL2,IO Pull-up and Pull-down Enable Bits\nDetermine PF.6 I/O pull-up or pull-down.\nNote1:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.6 pull-up and pull-down disabled,1: PF.6 pull-up enabled,2: PF.6 pull-down enabled,3: PF.6 pull-up and pull-down disabled"
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bitfld.long 0x00 19. "CTLSEL2,IO Pin State Backup Selection\nWhen TAMP0EN is disabled PF.6 pin (TAMPER0 pin) can be used as GPIO function" "0: PF.6 pin I/O function is controlled by GPIO..,1: PF.6 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 18. "DOUT2,IO Output Data" "0: PF.6 output low,1: PF.6 output high"
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bitfld.long 0x00 16.--17. "OPMODE2,IO Operation Mode" "0: PF.6 is input only mode,1: PF.6 is output push pull mode,2: PF.6 is open drain mode,3: PF.6 is quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "PUSEL1,IO Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pullOpull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid.." "0: PF.5 pull-up and pull-down disabled,1: PF.5 pull-up enabled,2: PF.5 pull-down enabled,3: PF.5 pull-up and pull-down disabled"
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bitfld.long 0x00 11. "CTLSEL1,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled PF.5 pin (X32KI pin) can be used as GPIO function" "0: PF.5 pin I/O function is controlled by GPIO..,1: PF.5 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 10. "DOUT1,IO Output Data" "0: PF.5 output low,1: PF.5 output high"
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bitfld.long 0x00 8.--9. "OPMODE1,IO Operation Mode" "0: PF.5 is input only mode,1: PF.5 is output push pull mode,2: PF.5 is open drain mode,3: PF.5 is quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "PUSEL0,IO Pull-up and Pull-down \nDetermine PF.4 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE0 set.." "0: PF.4 pull-up and pull-down disabled,1: PF.4 pull-up enabled,2: PF.4 pull-down enabled,3: PF.4 pull-up and pull-down disabled"
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bitfld.long 0x00 3. "CTLSEL0,IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled PF.4 pin (X32KO pin) can be used as GPIO function" "0: PF.4 pin I/O function is controlled by GPIO..,1: PF.4 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 2. "DOUT0,IO Output Data" "0: PF.4 output low,1: PF.4 output high"
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bitfld.long 0x00 0.--1. "OPMODE0,IO Operation Mode" "0: PF.4 is input only mode,1: PF.4 is output push pull mode,2: PF.4 is open drain mode,3: PF.4 is quasi-bidirectional mode"
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group.long 0x108++0x03
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line.long 0x00 "RTC_GPIOCTL1,RTC GPIO Control 1 Register"
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bitfld.long 0x00 28.--29. "PUSEL7,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.11 pull-up and pull-down disabled,1: PF.11 pull-up enabled,2: PF.11 pull-down enabled,3: PF.11 pull-up and pull-down disabled"
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bitfld.long 0x00 27. "CTLSEL7,I/O Pin State Backup Selection\nWhen TAMP5EN is disabled PF.11 pin (TAMPER5 pin) can be used as GPIO function" "0: PF.11 pin I/O function is controlled by GPIO..,1: PF.11 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 26. "DOUT7,I/O Output Data" "0: PF.11 output low,1: PF.11 output high"
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bitfld.long 0x00 24.--25. "OPMODE7,I/O Operation Mode" "0: PF.11 is input only mode,1: PF.11 is output push pull mode,2: PF.11 is open drain mode,3: PF.11 is quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "PUSEL6,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.10 pull-up and pull-down disabled,1: PF.10 pull-up enabled,2: PF.10 pull-down enabled,3: PF.10 pull-up and pull-down disabled"
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bitfld.long 0x00 19. "CTLSEL6,I/O Pin State Backup Selection\nWhen TAMP4EN is disabled PF.10 pin (TAMPER4 pin) can be used as GPIO function" "0: PF.10 pin I/O function is controlled by GPIO..,1: PF.10 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 18. "DOUT6,I/O Output Data" "0: PF.10 output low,1: PF.10 output high"
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bitfld.long 0x00 16.--17. "OPMODE6,I/O Operation Mode" "0: PF.10 is input only mode,1: PF.10 is output push pull mode,2: PF.10 is open drain mode,3: PF.10 is quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "PUSEL5,I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when.." "0: PF.9 pull-up and pull-down disabled,1: PF.9 pull-up enabled,2: PF.9 pull-down enabled,3: PF.9 pull-up and pull-down disabled"
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bitfld.long 0x00 11. "CTLSEL5,I/O Pin State Backup Selection\nWhen TAMP3EN is disabled PF.9 pin (TAMPER3 pin) can be used as GPIO function" "0: PF.9 pin I/O function is controlled by GPIO..,1: PF.9 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 10. "DOUT5,I/O Output Data" "0: PF.9 output low,1: PF.9 output high"
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bitfld.long 0x00 8.--9. "OPMODE5,I/O Operation Mode" "0: PF.9 is input only mode,1: PF.9 is output push pull mode,2: PF.9 is open drain mode,3: PF.9 is quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "PUSEL4,I/O Pull-up and Pull-down \nDetermine PF.8 I/O pull-up or pull-down.\nNote:\nBasically the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE4 set.." "0: PF.8 pull-up and pull-down disabled,1: PF.8 pull-up enabled,2: PF.8 pull-down enabled,3: PF.8 pull-up and pull-down disabled"
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bitfld.long 0x00 3. "CTLSEL4,I/O Pin State Backup Selection\nWhen TAMP2EN is disabled PF.8 pin (TAMPER2 pin) can be used as GPIO function" "0: PF.8 pin I/O function is controlled by GPIO..,1: PF.8 pin I/O function is controlled by VBAT.."
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bitfld.long 0x00 2. "DOUT4,I/O Output Data" "0: PF.8 output low,1: PF.8 output high"
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bitfld.long 0x00 0.--1. "OPMODE4,I/O Operation Mode" "0: PF.8 is input only mode,1: PF.8 is output push pull mode,2: PF.8 is open drain mode,3: PF.8 is quasi-bidirectional mode"
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group.long 0x110++0x03
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line.long 0x00 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
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bitfld.long 0x00 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Change is not performed,1: Daylight Saving Change is performed"
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bitfld.long 0x00 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted.."
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bitfld.long 0x00 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one.."
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group.long 0x120++0x03
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line.long 0x00 "RTC_TAMPCTL,RTC Tamper Pin Control Register"
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bitfld.long 0x00 31. "DYNPR2EN,Dynamic Pair 2 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 30. "TAMP5DBEN,Tamper 5 De-bounce Enable Bit" "0: Tamper 5 de-bounce Disabled,1: Tamper 5 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 29. "TAMP5LV,Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 28. "TAMP5EN,Tamper 5 Detect Enable Bit\nNote: The reference is RTC-clock" "0: Tamper 5 detect Disabled,1: Tamper 5 detect Enabled"
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bitfld.long 0x00 26. "TAMP4DBEN,Tamper 4 De-bounce Enable Bit" "0: Tamper 4 de-bounce Disabled,1: Tamper 4 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 25. "TAMP4LV,Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 24. "TAMP4EN,Tamper4 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 4 detect Disabled,1: Tamper 4 detect Enabled"
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bitfld.long 0x00 23. "DYNPR1EN,Dynamic Pair 1 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 22. "TAMP3DBEN,Tamper 3 De-bounce Enable Bit" "0: Tamper 3 de-bounce Disabled,1: Tamper 3 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 21. "TAMP3LV,Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 20. "TAMP3EN,Tamper 3 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 3 detect Disabled,1: Tamper 3 detect Enabled"
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bitfld.long 0x00 18. "TAMP2DBEN,Tamper 2 De-bounce Enable Bit" "0: Tamper 2 de-bounce Disabled,1: Tamper 2 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 17. "TAMP2LV,Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 16. "TAMP2EN,Tamper 2 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 2 detect Disabled,1: Tamper 2 detect Enabled"
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bitfld.long 0x00 15. "DYNPR0EN,Dynamic Pair 0 Enable Bit" "0: Static detect,1: Dynamic detect"
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bitfld.long 0x00 14. "TAMP1DBEN,Tamper 1 De-bounce Enable Bit" "0: Tamper 1 de-bounce Disabled,1: Tamper 1 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 13. "TAMP1LV,Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 12. "TAMP1EN,Tamper 1 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 1 detect Disabled,1: Tamper 1 detect Enabled"
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bitfld.long 0x00 10. "TAMP0DBEN,Tamper 0 De-bounce Enable Bit" "0: Tamper 0 de-bounce Disabled,1: Tamper 0 de-bounce Enabled tamper detection.."
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bitfld.long 0x00 9. "TAMP0LV,Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection" "0: Detect voltage level is low,1: Detect voltage level is high"
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bitfld.long 0x00 8. "TAMP0EN,Tamper0 Detect Enable Bit\nNote1: The reference is RTC-clock" "0: Tamper 0 detect Disabled,1: Tamper 0 detect Enabled"
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bitfld.long 0x00 5.--7. "DYNRATE,Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately" "0: 210 * RTC_CLK,1: 211 * RTC_CLK,2: 212 * RTC_CLK,3: 213 * RTC_CLK,4: 214 * RTC_CLK,5: 215 * RTC_CLK,6: 216 * RTC_CLK,7: 217 * RTC_CLK"
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bitfld.long 0x00 4. "SEEDRLD,Reload New Seed for PRNG Engine\nSetting this bit the tamper configuration will be reload.\nNote: Before this bit is set the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed" "0: Generating key based on the current seed,1: Reload new seed"
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bitfld.long 0x00 2.--3. "DYNSRC,Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified the SEEDRLD (RTC_TAMPCTL[4]) should be set" "?,1: The new reference pattern is repeated..,?,3: The new reference pattern is repeated from.."
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bitfld.long 0x00 1. "DYN2ISS,Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set" "0: Tamper input is from Tamper 4,1: Tamper input is from Tamper 0"
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bitfld.long 0x00 0. "DYN1ISS,Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set" "0: Tamper input is from Tamper 2,1: Tamper input is from Tamper 0"
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group.long 0x128++0x03
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line.long 0x00 "RTC_TAMPSEED,RTC Tamper Dynamic Seed Register"
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hexmask.long 0x00 0.--31. 1. "SEED,Seed Value"
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rgroup.long 0x130++0x03
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line.long 0x00 "RTC_TAMPTIME,RTC Tamper Time Register"
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hexmask.long.byte 0x00 24.--30. 1. "HZCNT,Index of sub-second counter(0x00 ~0x7F)"
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of TAMPER Time (0~2)Note: 24-hour time scale only" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of TAMPER Time (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of TAMPER Time (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x134++0x03
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line.long 0x00 "RTC_TAMPCAL,RTC Tamper Calendar Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of TAMPER Calendar (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of TAMPER Calendar (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of TAMPER Calendar (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x140++0x03
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line.long 0x00 "RTC_CLKDCTL,Clock Fail Detector Control Register"
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rbitfld.long 0x00 17. "LXTSLOWF,LXT Slower Than LIRC32K Flag (Read Only ) \nNote: LXTSLOWF is vaild during CLKSPIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising" "0: 32.768 kHz external low speed crystal..,1: LXT frequency is slowly"
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rbitfld.long 0x00 16. "CLKSWLIRCF,LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)" "0: RTC clock source from LXT,1: RTC clock source from LIRC32K"
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bitfld.long 0x00 2. "LXTSPSW,LXT Clock Stop Detector Switch LIRC32K Enable Bit" "0: LXT clock Stop switch LIRC32K Disabled,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 1. "LXTFSW,LXT Clock Fail Detector Switch LIRC32K Enable Bit" "0: LXT clock Fail switch LIRC32K Disabled,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 0. "LXTFDEN,LXT Clock Fail/Stop Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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group.long 0x144++0x03
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line.long 0x00 "RTC_CDBR,Clock Frequency Detector Boundary Register"
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hexmask.long.byte 0x00 16.--23. 1. "FAILBD,LXT Clock Frequency Detector FAIL Boundary\nThe bits define the fail value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector fail Boundary the LXT frequency detect fail interrupt flag will set to.."
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hexmask.long.byte 0x00 0.--7. 1. "STOPBD,LXT Clock Stop Frequency Detector Stop Boundary\nThe bits define the stop value of frequency monitor window.\nWhen LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary the LXT frequency detect Stop interrupt flag will.."
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tree.end
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tree.end
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tree "SC"
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tree "SC0"
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base ad:0x40090000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "SC0_NS"
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base ad:0x50090000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "SC1"
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base ad:0x40091000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "SC1_NS"
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base ad:0x50091000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "SC2"
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base ad:0x40092000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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tree "SC2_NS"
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base ad:0x50092000
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled DAT cannot be programmed.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24 bit timer and two 8 bit timers.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nIf user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.194\nWarm-reset: refer.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stops counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,Rx Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the TX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field but this field must be greater than 0x04"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TBEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt" "0: Receive data reach trigger level interrupt..,1: Receive data reach trigger level interrupt.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading SCn_DAT register to.." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])) deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF,Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by.." "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TBEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active and this bit is set by.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is less than TXRTY..,1: Transmitter retries counts is equal or over.."
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bitfld.long 0x00 29. "TXRERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]).." "0: Receiver retries counts is less than RXRTY..,1: Receiver retries counts is equal or over than.."
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bitfld.long 0x00 21. "RXRERR,Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD" "0: The SCn_CD pin state at low,1: The SCn_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow when Tx buffer is full.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit' +.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte of.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST" "0: SCn_RST pin is low,1: SCn_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR" "0: SCn_PWR pin to low,1: SCn_PWR pin to high"
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rbitfld.long 0x00 16. "DATASTS,SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA" "0: The SCn_DATA pin status is low,1: The SCn_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_DATA pin to low.\nSCn_DATA signal..,1: Drive SCn_DATA pin to high.\nSCn_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "RSTEN,SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be changed automatically" "0: Drive SCn_RST pin to low.\nSCn_RST signal..,1: Drive SCn_RST pin to high.\nSCn_RST signal.."
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bitfld.long 0x00 0. "PWREN,SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage.." "0: SCn_PWR signal status is low,1: SCn_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Internal Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to the SCn_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.193 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base"
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|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC_TMRCTL1,SC Internal Timer1 Control Register"
|
|
rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization software should check this bit when writing a new value to SCn_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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|
bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.193 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC_TMRCTL2,SC Internal Timer2 Control Register"
|
|
rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SCn_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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|
bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.193 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
|
|
bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1 are transmitted or..,1: Odd number of logic 1 are transmitted or.."
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|
bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode this field must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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|
newline
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode this WLS must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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|
bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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|
group.long 0x4C++0x03
|
|
line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
|
|
bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
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tree.end
|
|
tree "SCU"
|
|
tree "SCU"
|
|
base ad:0x4002F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCU_PNSSET0,Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)"
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|
bitfld.long 0x00 24. "PDMA1,Set PDMA1 to Non-secure State\nWrite 1 to set PDMA1 to non-secure state" "0: PDMA1 is a secure module (default),1: PDMA1 is a non-secure module"
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|
bitfld.long 0x00 16. "EBI,Set EBI to Non-secure State\nWrite 1 to set EBI to non-secure state" "0: EBI is a secure module (default),1: EBI is a non-secure module"
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|
newline
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bitfld.long 0x00 13. "SDH0,Set SDH0 to Non-secure State\nWrite 1 to set SDH0 to non-secure state" "0: SDH0 is a secure module (default),1: SDH0 is a non-secure module"
|
|
bitfld.long 0x00 9. "USBH,Set USBH to Non-secure State\nWrite 1 to set USBH to non-secure state" "0: USBH is a secure module (default),1: USBH is a non-secure module"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SCU_PNSSET1,Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)"
|
|
bitfld.long 0x00 18. "CRPT,Set CRPT to Non-secure State\nWrite 1 to set CRPT to non-secure state" "0: CRPT is a secure module (default),1: CRPT is a non-secure module"
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|
bitfld.long 0x00 17. "CRC,Set CRC to Non-secure State\nWrite 1 to set CRC to non-secure state" "0: CRC is a secure module (default),1: CRC is a non-secure module"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCU_PNSSET2,Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)"
|
|
bitfld.long 0x00 27. "BPWM1,Set BPWM1 to Non-secure State\nWrite 1 to set BPWM1 to non-secure state" "0: BPWM1 is a secure module (default),1: BPWM1 is a non-secure module"
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|
bitfld.long 0x00 26. "BPWM0,Set BPWM0 to Non-secure State\nWrite 1 to set BPWM0 to non-secure state" "0: BPWM0 is a secure module (default),1: BPWM0 is a non-secure module"
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bitfld.long 0x00 25. "EPWM1,Set EPWM1 to Non-secure State\nWrite 1 to set EPWM1 to non-secure state" "0: EPWM1 is a secure module (default),1: EPWM1 is a non-secure module"
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bitfld.long 0x00 24. "EPWM0,Set EPWM0 to Non-secure State\nWrite 1 to set EPWM0 to non-secure state" "0: EPWM0 is a secure module (default),1: EPWM0 is a non-secure module"
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|
newline
|
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bitfld.long 0x00 17. "TMR23,Set TMR23 to Non-secure State\nWrite 1 to set TMR23 to non-secure state" "0: TMR23 is a secure module (default),1: TMR23 is a non-secure module"
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|
bitfld.long 0x00 13. "OTG,Set OTG to Non-secure State\nWrite 1 to set OTG to non-secure state" "0: OTG is a secure module (default),1: OTG is a non-secure module"
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|
newline
|
|
bitfld.long 0x00 8. "I2S0,Set I2S0 to Non-secure State\nWrite 1 to set I2S0 to non-secure state" "0: I2S0 is a secure module (default),1: I2S0 is a non-secure module"
|
|
bitfld.long 0x00 7. "DAC,Set DAC to Non-secure State\nWrite 1 to set DAC to non-secure state" "0: DAC is a secure module (default),1: DAC is a non-secure module"
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|
newline
|
|
bitfld.long 0x00 5. "ACMP01,Set ACMP01 to Non-secure State\nWrite 1 to set ACMP0 ACMP1 to non-secure state" "0: ACMP0 ACMP1 are secure modules (default),1: ACMP0 ACMP1 are non-secure modules"
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|
bitfld.long 0x00 3. "EADC,Set EADC to Non-secure State\nWrite 1 to set EADC to non-secure state" "0: EADC is a secure module (default),1: EADC is a non-secure module"
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|
newline
|
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bitfld.long 0x00 1. "RTC,Set RTC to Non-secure State\nWrite 1 to set RTC to non-secure state" "0: RTC is a secure module (default),1: RTC is a non-secure module"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCU_PNSSET3,Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)"
|
|
bitfld.long 0x00 21. "UART5,Set UART5 to Non-secure State\nWrite 1 to set UART5 to non-secure state" "0: UART5 is a secure module (default),1: UART5 is a non-secure module"
|
|
bitfld.long 0x00 20. "UART4,Set UART4 to Non-secure State\nWrite 1 to set UART4 to non-secure state" "0: UART4 is a secure module (default),1: UART4 is a non-secure module"
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|
newline
|
|
bitfld.long 0x00 19. "UART3,Set UART3 to Non-secure State\nWrite 1 to set UART3 to non-secure state" "0: UART3 is a secure module (default),1: UART3 is a non-secure module"
|
|
bitfld.long 0x00 18. "UART2,Set UART2 to Non-secure State\nWrite 1 to set UART2 to non-secure state" "0: UART2 is a secure module (default),1: UART2 is a non-secure module"
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|
newline
|
|
bitfld.long 0x00 17. "UART1,Set UART1 to Non-secure State\nWrite 1 to set UART1 to non-secure state" "0: UART1 is a secure module (default),1: UART1 is a non-secure module"
|
|
bitfld.long 0x00 16. "UART0,Set UART0 to Non-secure State\nWrite 1 to set UART0 to non-secure state" "0: UART0 is a secure module (default),1: UART0 is a non-secure module"
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|
newline
|
|
bitfld.long 0x00 4. "SPI3,Set SPI3 to Non-secure State\nWrite 1 to set SPI3 to non-secure state" "0: SPI3 is a secure module (default),1: SPI3 is a non-secure module"
|
|
bitfld.long 0x00 3. "SPI2,Set SPI2 to Non-secure State\nWrite 1 to set SPI2 to non-secure state" "0: SPI2 is a secure module (default),1: SPI2 is a non-secure module"
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|
newline
|
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bitfld.long 0x00 2. "SPI1,Set SPI1 to Non-secure State\nWrite 1 to set SPI1 to non-secure state" "0: SPI1 is a secure module (default),1: SPI1 is a non-secure module"
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|
bitfld.long 0x00 1. "SPI0,Set SPI0 to Non-secure State\nWrite 1 to set SPI0 to non-secure state" "0: SPI0 is a secure module (default),1: SPI0 is a non-secure module"
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newline
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bitfld.long 0x00 0. "QSPI0,Set QSPI0 to Non-secure State\nWrite 1 to set QSPI0 to non-secure state" "0: QSPI0 is a secure module (default),1: QSPI0 is a non-secure module"
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|
group.long 0x10++0x03
|
|
line.long 0x00 "SCU_PNSSET4,Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)"
|
|
bitfld.long 0x00 18. "SC2,Set SC2 to Non-secure State\nWrite 1 to set SC2 to non-secure state" "0: SC2 is a secure module (default),1: SC2 is a non-secure module"
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bitfld.long 0x00 17. "SC1,Set SC1 to Non-secure State\nWrite 1 to set SC1 to non-secure state" "0: SC1 is a secure module (default),1: SC1 is a non-secure module"
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newline
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bitfld.long 0x00 16. "SC0,Set SC0 to Non-secure State\nWrite 1 to set SC0 to non-secure state" "0: SC0 is a secure module (default),1: SC0 is a non-secure module"
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|
bitfld.long 0x00 2. "I2C2,Set I2C2 to Non-secure State\nWrite 1 to set I2C2 to non-secure state" "0: I2C2 is a secure module (default),1: I2C2 is a non-secure module"
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newline
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bitfld.long 0x00 1. "I2C1,Set I2C1 to Non-secure State\nWrite 1 to set I2C1 to non-secure state" "0: I2C1 is a secure module (default),1: I2C1 is a non-secure module"
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bitfld.long 0x00 0. "I2C0,Set I2C0 to Non-secure State\nWrite 1 to set I2C0 to non-secure state" "0: I2C0 is a secure module (default),1: I2C0 is a non-secure module"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCU_PNSSET5,Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)"
|
|
bitfld.long 0x00 25. "TRNG,Set TRNG to Non-secure State\nWrite 1 to set TRNG to non-secure state" "0: TRNG is a secure module (default),1: TRNG is a non-secure module"
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bitfld.long 0x00 21. "ECAP1,Set ECAP1 to Non-secure State\nWrite 1 to set ECAP1 to non-secure state" "0: ECAP1 is a secure module (default),1: ECAP1 is a non-secure module"
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newline
|
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bitfld.long 0x00 20. "ECAP0,Set ECAP0 to Non-secure State\nWrite 1 to set ECAP0 to non-secure state" "0: ECAP0 is a secure module (default),1: ECAP0 is a non-secure module"
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bitfld.long 0x00 17. "QEI1,Set QEI1 to Non-secure State\nWrite 1 to set QEI1 to non-secure state" "0: QEI1 is a secure module (default),1: QEI1 is a non-secure module"
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newline
|
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bitfld.long 0x00 16. "QEI0,Set QEI0 to Non-secure State\nWrite 1 to set QEI0 to non-secure state" "0: QEI0 is a secure module (default),1: QEI0 is a non-secure module"
|
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bitfld.long 0x00 0. "CAN0,Set CAN0 to Non-secure State\nWrite 1 to set CAN0 to non-secure state" "0: CAN0 is a secure module (default),1: CAN0 is a non-secure module"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SCU_PNSSET6,Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)"
|
|
bitfld.long 0x00 17. "USCI1,Set USCI1 to Non-secure State\nWrite 1 to set USCI1 to non-secure state" "0: USCI1 is a secure module (default),1: USCI1 is a non-secure module"
|
|
bitfld.long 0x00 16. "USCI0,Set USCI0 to Non-secure State\nWrite 1 to set USCI0 to non-secure state" "0: USCI0 is a secure module (default),1: USCI0 is a non-secure module"
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newline
|
|
bitfld.long 0x00 0. "USBD,Set USBD to Non-secure State\nWrite 1 to set USBD to non-secure state" "0: USBD is a secure module (default),1: USBD is a non-secure module"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCU_IONSSET,IO Non-secure Attribution Set Register"
|
|
bitfld.long 0x00 7. "PH,Set GPIO Port H to Non-scecure State\nWrite 1 to set PH to non-secure state" "0: GPIO port H is secure (default),1: GPIO port H is non-secure"
|
|
bitfld.long 0x00 6. "PG,Set GPIO Port G to Non-scecure State\nWrite 1 to set PG to non-secure state" "0: GPIO port G is secure (default),1: GPIO port G is non-secure"
|
|
newline
|
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bitfld.long 0x00 5. "PF,Set GPIO Port F to Non-scecure State\nWrite 1 to set PF to non-secure state" "0: GPIO port F is secure (default),1: GPIO port F is non-secure"
|
|
bitfld.long 0x00 4. "PE,Set GPIO Port E to Non-scecure State\nWrite 1 to set PE to non-secure state" "0: GPIO port E is secure (default),1: GPIO port E is non-secure"
|
|
newline
|
|
bitfld.long 0x00 3. "PD,Set GPIO Port D to Non-scecure State\nWrite 1 to set PD to non-secure state" "0: GPIO port D is secure (default),1: GPIO port D is non-secure"
|
|
bitfld.long 0x00 2. "PC,Set GPIO Port C to Non-scecure State\nWrite 1 to set PC to non-secure state" "0: GPIO port C is secure (default),1: GPIO port C is non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. "PB,Set GPIO Port B to Non-scecure State\nWrite 1 to set PB to non-secure state" "0: GPIO port B is secure (default),1: GPIO port B is non-secure"
|
|
bitfld.long 0x00 0. "PA,Set GPIO Port A to Non-scecure State\nWrite 1 to set PA to non-secure state" "0: GPIO port A is secure (default),1: GPIO port A is non-secure"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCU_SRAMNSSET,SRAM Non-secure Attribution Set Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "SECn,Set SRAM Section N to Non-scecure State\nWrite 1 to set SRAM section n to non-secure state"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCU_FNSADDR,Flash Non-secure Boundary Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "FNSADDR,Flash Non-secure Boundary Address\nIndicate the base address of Non-secure region set in user configuration"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCU_SVIOIEN,Security Violation Interrupt Enable Register"
|
|
bitfld.long 0x00 18. "CRPTIEN,CRPT Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 17. "SYSIEN,SYS Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 16. "SCUIEN,SCU Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 15. "FLASHIEN,FLASH Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 14. "FMCIEN,FMC Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 13. "SRAM1IEN,SRAM Bank 1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
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bitfld.long 0x00 12. "SRAM0IEN,SRAM Bank 0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 11. "PDMA1IEN,PDMA1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
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bitfld.long 0x00 10. "PDMA0IEN,PDMA0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 8. "SDH0IEN,SDH0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 7. "CRCIEN,CRC Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 6. "USBHIEN,USBH Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
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bitfld.long 0x00 5. "EBIIEN,EBI Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 4. "GPIOIEN,GPIO Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
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bitfld.long 0x00 1. "APB1IEN,APB1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 0. "APB0IEN,APB0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCU_SVINTSTS,Security Violation Interrupt Status Register"
|
|
bitfld.long 0x00 18. "CRPTIF,CRPT Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No CRPT violation interrupt event,1: There is CRPT violation interrupt event"
|
|
bitfld.long 0x00 17. "SYSIF,SYS Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SYS violation interrupt event,1: There is SYS violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 16. "SCUIF,SCU Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SCU violation interrupt event,1: There is SCU violation interrupt event"
|
|
bitfld.long 0x00 15. "FLASHIF,FLASH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No FLASH violation interrupt event,1: There is FLASH violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 14. "FMCIF,FMC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No FMC violation interrupt event,1: There is FMC violation interrupt event"
|
|
bitfld.long 0x00 13. "SRAM1IF,SRAM Bank 1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SRAM1 violation interrupt event,1: There is SRAM1 violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 12. "SRAM0IF,SRAM0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SRAM0 violation interrupt event,1: There is SRAM0 violation interrupt event"
|
|
bitfld.long 0x00 11. "PDMA1IF,PDMA1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No PDMA1 violation interrupt event,1: There is PDMA1 violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 10. "PDMA0IF,PDMA0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No PDMA0 violation interrupt event,1: There is PDMA0 violation interrupt event"
|
|
bitfld.long 0x00 8. "SDH0IF,SDH0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SDH0 violation interrupt event,1: There is SDH0 violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 7. "CRCIF,CRC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No CRC violation interrupt event,1: There is CRC violation interrupt event"
|
|
bitfld.long 0x00 6. "USBHIF,USBH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No USBH violation interrupt event,1: There is USBH violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 5. "EBIIF,EBI Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No EBI violation interrupt event,1: There is EBI violation interrupt event"
|
|
bitfld.long 0x00 4. "GPIOIF,GPIO Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No GPIO violation interrupt event,1: There is GPIO violation interrupt event"
|
|
newline
|
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bitfld.long 0x00 1. "APB1IF,APB1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No APB1 violation interrupt event,1: There is APB1 violation interrupt event"
|
|
bitfld.long 0x00 0. "APB0IF,APB0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No APB0 violation interrupt event,1: There is APB0 violation interrupt event"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SCU_APB0VSRC,APB0 Security Policy Violation Source"
|
|
bitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SCU_APB0VA,APB0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SCU_APB1VSRC,APB1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SCU_APB1VA,APB1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SCU_GPIOVSRC,GPIO Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCU_GPIOVA,GPIO Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SCU_EBIVSRC,EBI Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SCU_EBIVA,EBI Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SCU_USBHVSRC,USBH Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SCU_USBHVA,USBH Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SCU_CRCVSRC,CRC Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SCU_CRCVA,CRC Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SCU_SD0VSRC,SDH0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SCU_SD0VA,SDH0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SCU_PDMA0VSRC,PDMA0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SCU_PDMA0VA,PDMA0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SCU_PDMA1VSRC,PDMA1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SCU_PDMA1VA,PDMA1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "SCU_SRAM0VSRC,SRAM0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SCU_SRAM0VA,SRAM0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCU_SRAM1VSRC,SRAM1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SCU_SRAM1VA,SRAM1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SCU_FMCVSRC,FMC Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SCU_FMCVA,FMC Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "SCU_FLASHVSRC,Flash Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SCU_FLASHVA,Flash Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SCU_SCUVSRC,SCU Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "SCU_SCUVA,SCU Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "SCU_SYSVSRC,System Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SCU_SYSVA,System Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SCU_CRPTVSRC,Crypto Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "SCU_CRPTVA,Crypto Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SCU_NSMCTL,Non-secure State Monitor Control Register"
|
|
bitfld.long 0x00 13. "DBGON,Monitor Counter Keep Counting When the Chip is in Debug Mode Enable Bit" "0: The counter will be halted when the core..,1: The counter will keep counting when the core.."
|
|
bitfld.long 0x00 12. "IDLEON,Monitor Counter Keep Counting When the Chip is in Idle Mode Enable Bit\nNote: In monitor mode the counter is always halted when the core processor is in secure state" "0: The counter will be halted when the chip is..,1: The counter will keep counting when the chip.."
|
|
newline
|
|
bitfld.long 0x00 10. "TMRMOD,Non-secure Monitor Mode Enable Bit" "0: Monitor mode,1: Free-counting mode"
|
|
bitfld.long 0x00 9. "AUTORLD,Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1" "0: Disable clearing non-secure state monitor..,1: Enable clearing non-secure state monitor.."
|
|
newline
|
|
bitfld.long 0x00 8. "NSMIEN,Non-secure State Monitor Interrupt Enable Bit" "0: Non-secure state monitor interrupt Disabled,1: Non-secure state monitor interrupt Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Value of Non-secure State Monitor Counter"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SCU_NSMLOAD,Non-secure State Monitor Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Reload Value for Non-secure State Monitor Counter\nThe RELOAD value will be reloaded to the counter whenever the counter counts down to 0"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SCU_NSMVAL,Non-secure State Monitor Counter Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Counter Value of Non-secure State Monitor Counter\nA write of any value clears the VALUE to 0 and also clears NSMIF"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "SCU_NSMSTS,Non-secure State Monitor Status Register"
|
|
bitfld.long 0x00 1. "NSMIF,Non-secure State Monitor Interrupt Flag\nNote: This bit is cleared by writing 1" "0: Counter doesn't count down to 0 since the..,1: Counter counts down to 0"
|
|
bitfld.long 0x00 0. "CURRNS,Current Core Processor Secure/Non-secure State\nNote: This bit can be used to monitor the current secure/non-secure state of the core processor even if the non-secure state monitor counter is disabled" "0: Core processor is in secure state,1: Core processor is in non-secure state"
|
|
tree.end
|
|
tree "SCU_NS"
|
|
base ad:0x5002F000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCU_PNSSET0,Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)"
|
|
bitfld.long 0x00 24. "PDMA1,Set PDMA1 to Non-secure State\nWrite 1 to set PDMA1 to non-secure state" "0: PDMA1 is a secure module (default),1: PDMA1 is a non-secure module"
|
|
bitfld.long 0x00 16. "EBI,Set EBI to Non-secure State\nWrite 1 to set EBI to non-secure state" "0: EBI is a secure module (default),1: EBI is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 13. "SDH0,Set SDH0 to Non-secure State\nWrite 1 to set SDH0 to non-secure state" "0: SDH0 is a secure module (default),1: SDH0 is a non-secure module"
|
|
bitfld.long 0x00 9. "USBH,Set USBH to Non-secure State\nWrite 1 to set USBH to non-secure state" "0: USBH is a secure module (default),1: USBH is a non-secure module"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SCU_PNSSET1,Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)"
|
|
bitfld.long 0x00 18. "CRPT,Set CRPT to Non-secure State\nWrite 1 to set CRPT to non-secure state" "0: CRPT is a secure module (default),1: CRPT is a non-secure module"
|
|
bitfld.long 0x00 17. "CRC,Set CRC to Non-secure State\nWrite 1 to set CRC to non-secure state" "0: CRC is a secure module (default),1: CRC is a non-secure module"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCU_PNSSET2,Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)"
|
|
bitfld.long 0x00 27. "BPWM1,Set BPWM1 to Non-secure State\nWrite 1 to set BPWM1 to non-secure state" "0: BPWM1 is a secure module (default),1: BPWM1 is a non-secure module"
|
|
bitfld.long 0x00 26. "BPWM0,Set BPWM0 to Non-secure State\nWrite 1 to set BPWM0 to non-secure state" "0: BPWM0 is a secure module (default),1: BPWM0 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 25. "EPWM1,Set EPWM1 to Non-secure State\nWrite 1 to set EPWM1 to non-secure state" "0: EPWM1 is a secure module (default),1: EPWM1 is a non-secure module"
|
|
bitfld.long 0x00 24. "EPWM0,Set EPWM0 to Non-secure State\nWrite 1 to set EPWM0 to non-secure state" "0: EPWM0 is a secure module (default),1: EPWM0 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 17. "TMR23,Set TMR23 to Non-secure State\nWrite 1 to set TMR23 to non-secure state" "0: TMR23 is a secure module (default),1: TMR23 is a non-secure module"
|
|
bitfld.long 0x00 13. "OTG,Set OTG to Non-secure State\nWrite 1 to set OTG to non-secure state" "0: OTG is a secure module (default),1: OTG is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 8. "I2S0,Set I2S0 to Non-secure State\nWrite 1 to set I2S0 to non-secure state" "0: I2S0 is a secure module (default),1: I2S0 is a non-secure module"
|
|
bitfld.long 0x00 7. "DAC,Set DAC to Non-secure State\nWrite 1 to set DAC to non-secure state" "0: DAC is a secure module (default),1: DAC is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 5. "ACMP01,Set ACMP01 to Non-secure State\nWrite 1 to set ACMP0 ACMP1 to non-secure state" "0: ACMP0 ACMP1 are secure modules (default),1: ACMP0 ACMP1 are non-secure modules"
|
|
bitfld.long 0x00 3. "EADC,Set EADC to Non-secure State\nWrite 1 to set EADC to non-secure state" "0: EADC is a secure module (default),1: EADC is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 1. "RTC,Set RTC to Non-secure State\nWrite 1 to set RTC to non-secure state" "0: RTC is a secure module (default),1: RTC is a non-secure module"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCU_PNSSET3,Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)"
|
|
bitfld.long 0x00 21. "UART5,Set UART5 to Non-secure State\nWrite 1 to set UART5 to non-secure state" "0: UART5 is a secure module (default),1: UART5 is a non-secure module"
|
|
bitfld.long 0x00 20. "UART4,Set UART4 to Non-secure State\nWrite 1 to set UART4 to non-secure state" "0: UART4 is a secure module (default),1: UART4 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 19. "UART3,Set UART3 to Non-secure State\nWrite 1 to set UART3 to non-secure state" "0: UART3 is a secure module (default),1: UART3 is a non-secure module"
|
|
bitfld.long 0x00 18. "UART2,Set UART2 to Non-secure State\nWrite 1 to set UART2 to non-secure state" "0: UART2 is a secure module (default),1: UART2 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 17. "UART1,Set UART1 to Non-secure State\nWrite 1 to set UART1 to non-secure state" "0: UART1 is a secure module (default),1: UART1 is a non-secure module"
|
|
bitfld.long 0x00 16. "UART0,Set UART0 to Non-secure State\nWrite 1 to set UART0 to non-secure state" "0: UART0 is a secure module (default),1: UART0 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 4. "SPI3,Set SPI3 to Non-secure State\nWrite 1 to set SPI3 to non-secure state" "0: SPI3 is a secure module (default),1: SPI3 is a non-secure module"
|
|
bitfld.long 0x00 3. "SPI2,Set SPI2 to Non-secure State\nWrite 1 to set SPI2 to non-secure state" "0: SPI2 is a secure module (default),1: SPI2 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 2. "SPI1,Set SPI1 to Non-secure State\nWrite 1 to set SPI1 to non-secure state" "0: SPI1 is a secure module (default),1: SPI1 is a non-secure module"
|
|
bitfld.long 0x00 1. "SPI0,Set SPI0 to Non-secure State\nWrite 1 to set SPI0 to non-secure state" "0: SPI0 is a secure module (default),1: SPI0 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 0. "QSPI0,Set QSPI0 to Non-secure State\nWrite 1 to set QSPI0 to non-secure state" "0: QSPI0 is a secure module (default),1: QSPI0 is a non-secure module"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SCU_PNSSET4,Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)"
|
|
bitfld.long 0x00 18. "SC2,Set SC2 to Non-secure State\nWrite 1 to set SC2 to non-secure state" "0: SC2 is a secure module (default),1: SC2 is a non-secure module"
|
|
bitfld.long 0x00 17. "SC1,Set SC1 to Non-secure State\nWrite 1 to set SC1 to non-secure state" "0: SC1 is a secure module (default),1: SC1 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 16. "SC0,Set SC0 to Non-secure State\nWrite 1 to set SC0 to non-secure state" "0: SC0 is a secure module (default),1: SC0 is a non-secure module"
|
|
bitfld.long 0x00 2. "I2C2,Set I2C2 to Non-secure State\nWrite 1 to set I2C2 to non-secure state" "0: I2C2 is a secure module (default),1: I2C2 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 1. "I2C1,Set I2C1 to Non-secure State\nWrite 1 to set I2C1 to non-secure state" "0: I2C1 is a secure module (default),1: I2C1 is a non-secure module"
|
|
bitfld.long 0x00 0. "I2C0,Set I2C0 to Non-secure State\nWrite 1 to set I2C0 to non-secure state" "0: I2C0 is a secure module (default),1: I2C0 is a non-secure module"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCU_PNSSET5,Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)"
|
|
bitfld.long 0x00 25. "TRNG,Set TRNG to Non-secure State\nWrite 1 to set TRNG to non-secure state" "0: TRNG is a secure module (default),1: TRNG is a non-secure module"
|
|
bitfld.long 0x00 21. "ECAP1,Set ECAP1 to Non-secure State\nWrite 1 to set ECAP1 to non-secure state" "0: ECAP1 is a secure module (default),1: ECAP1 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 20. "ECAP0,Set ECAP0 to Non-secure State\nWrite 1 to set ECAP0 to non-secure state" "0: ECAP0 is a secure module (default),1: ECAP0 is a non-secure module"
|
|
bitfld.long 0x00 17. "QEI1,Set QEI1 to Non-secure State\nWrite 1 to set QEI1 to non-secure state" "0: QEI1 is a secure module (default),1: QEI1 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 16. "QEI0,Set QEI0 to Non-secure State\nWrite 1 to set QEI0 to non-secure state" "0: QEI0 is a secure module (default),1: QEI0 is a non-secure module"
|
|
bitfld.long 0x00 0. "CAN0,Set CAN0 to Non-secure State\nWrite 1 to set CAN0 to non-secure state" "0: CAN0 is a secure module (default),1: CAN0 is a non-secure module"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SCU_PNSSET6,Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)"
|
|
bitfld.long 0x00 17. "USCI1,Set USCI1 to Non-secure State\nWrite 1 to set USCI1 to non-secure state" "0: USCI1 is a secure module (default),1: USCI1 is a non-secure module"
|
|
bitfld.long 0x00 16. "USCI0,Set USCI0 to Non-secure State\nWrite 1 to set USCI0 to non-secure state" "0: USCI0 is a secure module (default),1: USCI0 is a non-secure module"
|
|
newline
|
|
bitfld.long 0x00 0. "USBD,Set USBD to Non-secure State\nWrite 1 to set USBD to non-secure state" "0: USBD is a secure module (default),1: USBD is a non-secure module"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCU_IONSSET,IO Non-secure Attribution Set Register"
|
|
bitfld.long 0x00 7. "PH,Set GPIO Port H to Non-scecure State\nWrite 1 to set PH to non-secure state" "0: GPIO port H is secure (default),1: GPIO port H is non-secure"
|
|
bitfld.long 0x00 6. "PG,Set GPIO Port G to Non-scecure State\nWrite 1 to set PG to non-secure state" "0: GPIO port G is secure (default),1: GPIO port G is non-secure"
|
|
newline
|
|
bitfld.long 0x00 5. "PF,Set GPIO Port F to Non-scecure State\nWrite 1 to set PF to non-secure state" "0: GPIO port F is secure (default),1: GPIO port F is non-secure"
|
|
bitfld.long 0x00 4. "PE,Set GPIO Port E to Non-scecure State\nWrite 1 to set PE to non-secure state" "0: GPIO port E is secure (default),1: GPIO port E is non-secure"
|
|
newline
|
|
bitfld.long 0x00 3. "PD,Set GPIO Port D to Non-scecure State\nWrite 1 to set PD to non-secure state" "0: GPIO port D is secure (default),1: GPIO port D is non-secure"
|
|
bitfld.long 0x00 2. "PC,Set GPIO Port C to Non-scecure State\nWrite 1 to set PC to non-secure state" "0: GPIO port C is secure (default),1: GPIO port C is non-secure"
|
|
newline
|
|
bitfld.long 0x00 1. "PB,Set GPIO Port B to Non-scecure State\nWrite 1 to set PB to non-secure state" "0: GPIO port B is secure (default),1: GPIO port B is non-secure"
|
|
bitfld.long 0x00 0. "PA,Set GPIO Port A to Non-scecure State\nWrite 1 to set PA to non-secure state" "0: GPIO port A is secure (default),1: GPIO port A is non-secure"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCU_SRAMNSSET,SRAM Non-secure Attribution Set Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "SECn,Set SRAM Section N to Non-scecure State\nWrite 1 to set SRAM section n to non-secure state"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCU_FNSADDR,Flash Non-secure Boundary Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "FNSADDR,Flash Non-secure Boundary Address\nIndicate the base address of Non-secure region set in user configuration"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SCU_SVIOIEN,Security Violation Interrupt Enable Register"
|
|
bitfld.long 0x00 18. "CRPTIEN,CRPT Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 17. "SYSIEN,SYS Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 16. "SCUIEN,SCU Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 15. "FLASHIEN,FLASH Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 14. "FMCIEN,FMC Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 13. "SRAM1IEN,SRAM Bank 1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 12. "SRAM0IEN,SRAM Bank 0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 11. "PDMA1IEN,PDMA1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 10. "PDMA0IEN,PDMA0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 8. "SDH0IEN,SDH0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 7. "CRCIEN,CRC Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 6. "USBHIEN,USBH Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 5. "EBIIEN,EBI Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 4. "GPIOIEN,GPIO Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
newline
|
|
bitfld.long 0x00 1. "APB1IEN,APB1 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
bitfld.long 0x00 0. "APB0IEN,APB0 Security Violation Interrupt Enable Bit" "0: Interrupt triggered from security violation..,1: Interrupt triggered from security violation.."
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SCU_SVINTSTS,Security Violation Interrupt Status Register"
|
|
bitfld.long 0x00 18. "CRPTIF,CRPT Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No CRPT violation interrupt event,1: There is CRPT violation interrupt event"
|
|
bitfld.long 0x00 17. "SYSIF,SYS Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SYS violation interrupt event,1: There is SYS violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 16. "SCUIF,SCU Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SCU violation interrupt event,1: There is SCU violation interrupt event"
|
|
bitfld.long 0x00 15. "FLASHIF,FLASH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No FLASH violation interrupt event,1: There is FLASH violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 14. "FMCIF,FMC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No FMC violation interrupt event,1: There is FMC violation interrupt event"
|
|
bitfld.long 0x00 13. "SRAM1IF,SRAM Bank 1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SRAM1 violation interrupt event,1: There is SRAM1 violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 12. "SRAM0IF,SRAM0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SRAM0 violation interrupt event,1: There is SRAM0 violation interrupt event"
|
|
bitfld.long 0x00 11. "PDMA1IF,PDMA1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No PDMA1 violation interrupt event,1: There is PDMA1 violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 10. "PDMA0IF,PDMA0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No PDMA0 violation interrupt event,1: There is PDMA0 violation interrupt event"
|
|
bitfld.long 0x00 8. "SDH0IF,SDH0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No SDH0 violation interrupt event,1: There is SDH0 violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 7. "CRCIF,CRC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No CRC violation interrupt event,1: There is CRC violation interrupt event"
|
|
bitfld.long 0x00 6. "USBHIF,USBH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No USBH violation interrupt event,1: There is USBH violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 5. "EBIIF,EBI Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No EBI violation interrupt event,1: There is EBI violation interrupt event"
|
|
bitfld.long 0x00 4. "GPIOIF,GPIO Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No GPIO violation interrupt event,1: There is GPIO violation interrupt event"
|
|
newline
|
|
bitfld.long 0x00 1. "APB1IF,APB1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No APB1 violation interrupt event,1: There is APB1 violation interrupt event"
|
|
bitfld.long 0x00 0. "APB0IF,APB0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag" "0: No APB0 violation interrupt event,1: There is APB0 violation interrupt event"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "SCU_APB0VSRC,APB0 Security Policy Violation Source"
|
|
bitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "SCU_APB0VA,APB0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SCU_APB1VSRC,APB1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SCU_APB1VA,APB1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SCU_GPIOVSRC,GPIO Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SCU_GPIOVA,GPIO Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SCU_EBIVSRC,EBI Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SCU_EBIVA,EBI Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SCU_USBHVSRC,USBH Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SCU_USBHVA,USBH Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SCU_CRCVSRC,CRC Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SCU_CRCVA,CRC Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SCU_SD0VSRC,SDH0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SCU_SD0VA,SDH0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SCU_PDMA0VSRC,PDMA0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SCU_PDMA0VA,PDMA0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SCU_PDMA1VSRC,PDMA1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "SCU_PDMA1VA,PDMA1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "SCU_SRAM0VSRC,SRAM0 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SCU_SRAM0VA,SRAM0 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SCU_SRAM1VSRC,SRAM1 Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SCU_SRAM1VA,SRAM1 Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SCU_FMCVSRC,FMC Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SCU_FMCVA,FMC Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "SCU_FLASHVSRC,Flash Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "SCU_FLASHVA,Flash Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "SCU_SCUVSRC,SCU Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "SCU_SCUVA,SCU Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "SCU_SYSVSRC,System Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "SCU_SYSVA,System Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "SCU_CRPTVSRC,Crypto Security Policy Violation Source"
|
|
rbitfld.long 0x00 0.--3. "MASTER,Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined" "0: core processor,?,?,3: PDMA0,4: SDH0,5: CRYPTO,6: USH,?,?,?,?,11: PDMA1,?..."
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "SCU_CRPTVA,Crypto Violation Address"
|
|
hexmask.long 0x00 0.--31. 1. "VIOADDR,Violation Address\nIndicate the target address of the access which invokes the security violation"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SCU_NSMCTL,Non-secure State Monitor Control Register"
|
|
bitfld.long 0x00 13. "DBGON,Monitor Counter Keep Counting When the Chip is in Debug Mode Enable Bit" "0: The counter will be halted when the core..,1: The counter will keep counting when the core.."
|
|
bitfld.long 0x00 12. "IDLEON,Monitor Counter Keep Counting When the Chip is in Idle Mode Enable Bit\nNote: In monitor mode the counter is always halted when the core processor is in secure state" "0: The counter will be halted when the chip is..,1: The counter will keep counting when the chip.."
|
|
newline
|
|
bitfld.long 0x00 10. "TMRMOD,Non-secure Monitor Mode Enable Bit" "0: Monitor mode,1: Free-counting mode"
|
|
bitfld.long 0x00 9. "AUTORLD,Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1" "0: Disable clearing non-secure state monitor..,1: Enable clearing non-secure state monitor.."
|
|
newline
|
|
bitfld.long 0x00 8. "NSMIEN,Non-secure State Monitor Interrupt Enable Bit" "0: Non-secure state monitor interrupt Disabled,1: Non-secure state monitor interrupt Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Value of Non-secure State Monitor Counter"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SCU_NSMLOAD,Non-secure State Monitor Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Reload Value for Non-secure State Monitor Counter\nThe RELOAD value will be reloaded to the counter whenever the counter counts down to 0"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SCU_NSMVAL,Non-secure State Monitor Counter Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "VALUE,Counter Value of Non-secure State Monitor Counter\nA write of any value clears the VALUE to 0 and also clears NSMIF"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "SCU_NSMSTS,Non-secure State Monitor Status Register"
|
|
bitfld.long 0x00 1. "NSMIF,Non-secure State Monitor Interrupt Flag\nNote: This bit is cleared by writing 1" "0: Counter doesn't count down to 0 since the..,1: Counter counts down to 0"
|
|
bitfld.long 0x00 0. "CURRNS,Current Core Processor Secure/Non-secure State\nNote: This bit can be used to monitor the current secure/non-secure state of the core processor even if the non-secure state monitor counter is disabled" "0: Core processor is in secure state,1: Core processor is in non-secure state"
|
|
tree.end
|
|
tree.end
|
|
tree "SDH"
|
|
tree "SDH0"
|
|
base ad:0x4000D000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SDH_FB_0,Shared Buffer (FIFO)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SDH_FB_1,Shared Buffer (FIFO)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDH_FB_2,Shared Buffer (FIFO)"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SDH_FB_3,Shared Buffer (FIFO)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDH_FB_4,Shared Buffer (FIFO)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SDH_FB_5,Shared Buffer (FIFO)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SDH_FB_6,Shared Buffer (FIFO)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SDH_FB_7,Shared Buffer (FIFO)"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SDH_FB_8,Shared Buffer (FIFO)"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDH_FB_9,Shared Buffer (FIFO)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SDH_FB_10,Shared Buffer (FIFO)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SDH_FB_11,Shared Buffer (FIFO)"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SDH_FB_12,Shared Buffer (FIFO)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SDH_FB_13,Shared Buffer (FIFO)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SDH_FB_14,Shared Buffer (FIFO)"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SDH_FB_15,Shared Buffer (FIFO)"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SDH_FB_16,Shared Buffer (FIFO)"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SDH_FB_17,Shared Buffer (FIFO)"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SDH_FB_18,Shared Buffer (FIFO)"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SDH_FB_19,Shared Buffer (FIFO)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SDH_FB_20,Shared Buffer (FIFO)"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SDH_FB_21,Shared Buffer (FIFO)"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SDH_FB_22,Shared Buffer (FIFO)"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SDH_FB_23,Shared Buffer (FIFO)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SDH_FB_24,Shared Buffer (FIFO)"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SDH_FB_25,Shared Buffer (FIFO)"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SDH_FB_26,Shared Buffer (FIFO)"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SDH_FB_27,Shared Buffer (FIFO)"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "SDH_FB_28,Shared Buffer (FIFO)"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SDH_FB_29,Shared Buffer (FIFO)"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SDH_FB_30,Shared Buffer (FIFO)"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SDH_FB_31,Shared Buffer (FIFO)"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SDH_DMACTL,DMA Control and Status Register"
|
|
bitfld.long 0x00 9. "DMABUSY,DMA Transfer Is in Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not" "0: DMA transfer is not in progress,1: DMA transfer is in progress"
|
|
bitfld.long 0x00 3. "SGEN,Scatter-gather Function Enable Bit" "0: Scatter-gather function Disabled (DMA will..,1: Scatter-gather function Enabled (DMA will.."
|
|
newline
|
|
bitfld.long 0x00 1. "DMARST,Software Engine Reset\nNote: The software reset DMA related registers" "0: No effect,1: Reset internal state machine and pointers"
|
|
bitfld.long 0x00 0. "DMAEN,DMA Engine Enable Bit\nNote1: If this bit is cleared DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote2: If target abort occurred DMAEN will be cleared" "0: DMA Disabled,1: DMA Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SDH_DMASA,DMA Transfer Starting Address Register"
|
|
hexmask.long 0x00 1.--31. 1. "DMASA,DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode this field will be interpreted as a starting.."
|
|
bitfld.long 0x00 0. "ORDER,Determined to the PAD Table Fetching Is in Order or Out of Order" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SDH_DMABCNT,DMA Transfer Byte Count Register"
|
|
hexmask.long 0x00 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMA transfer"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SDH_DMAINTEN,DMA Interrupt Enable Control Register"
|
|
bitfld.long 0x00 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Bit" "0: Interrupt generation Disabled when wrong EOT..,1: Interrupt generation Enabled when wrong EOT.."
|
|
bitfld.long 0x00 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SDH_DMAINTSTS,DMA Interrupt Status Register"
|
|
rbitfld.long 0x00 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag (Read Only)\nWhen DMA Scatter-Gather function is enabled and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
|
|
rbitfld.long 0x00 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag (Read Only)\nNote1: This bit is read only but can be cleared by writing '1' to it.\nNote2: When DMA's bus master received ERROR response it means that target abort is happened" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SDH_GCTL,Global Control and Status Register"
|
|
bitfld.long 0x00 1. "SDEN,Secure Digital Functionality Enable Bit" "0: SD functionality Disabled,1: SD functionality Enabled"
|
|
bitfld.long 0x00 0. "GCTLRST,Software Engine Reset" "0: No effect,1: Reset SD host"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "SDH_GINTEN,Global Interrupt Control Register"
|
|
bitfld.long 0x00 0. "DTAIEN,DMA READ/WRITE Target Abort Interrupt Enable Bit" "0: DMA READ/WRITE target abort interrupt..,1: DMA READ/WRITE target abort interrupt.."
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SDH_GINTSTS,Global Interrupt Status Register"
|
|
rbitfld.long 0x00 0. "DTAIF,DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SDH_CTL,SD Control and Status Register"
|
|
bitfld.long 0x00 24.--27. "SDNWR,NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BLKCNT,Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer"
|
|
newline
|
|
bitfld.long 0x00 15. "DBW,SD Data Bus Width (for 1-bit / 4-bit Selection)" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
|
|
bitfld.long 0x00 14. "CTLRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and counters"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CMDCODE,SD Command Code\nThe bits contain the SD command code (0x00 - 0x3F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 7. "CLKKEEP,SD Clock Enable Control" "0: SD host decided when to output clock and when..,1: SD clock always keeps free running"
|
|
newline
|
|
bitfld.long 0x00 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
bitfld.long 0x00 5. "CLK74OEN,Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "R2EN,Response R2 Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
bitfld.long 0x00 3. "DOEN,Data Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "DIEN,Data Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
bitfld.long 0x00 1. "RIEN,Response Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "COEN,Command Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "SDH_CMDARG,SD Command Argument Register"
|
|
hexmask.long 0x00 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "SDH_INTEN,SD Interrupt Control Register"
|
|
bitfld.long 0x00 30. "CDSRC,SD Card Detect Source Selection" "0: From SD card's DAT3 pin,1: From GPIO pin"
|
|
bitfld.long 0x00 14. "WKIEN,Wake-up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD controller when card is inserted or removed" "0: SD Card interrupt to wake-up chip Disabled,1: SD Card interrupt to wake-up chip Enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "DITOIEN,Data Input Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out" "0: DITOIF (SDH_INTSTS[13]) trigger interrupt..,1: DITOIF (SDH_INTSTS[13]) trigger interrupt.."
|
|
bitfld.long 0x00 12. "RTOIEN,Response Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out" "0: RTOIF (SDH_INTSTS[12]) trigger interrupt..,1: RTOIF (SDH_INTSTS[12]) trigger interrupt.."
|
|
newline
|
|
bitfld.long 0x00 8. "CDIEN,SD Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card is inserted or removed" "0: CDIF (SDH_INTSTS[8]) trigger interrupt Disabled,1: CDIF (SDH_INTSTS[8]) trigger interrupt Enabled"
|
|
bitfld.long 0x00 1. "CRCIEN,CRC7 CRC16 and CRC Status Error Interrupt Enable Bit" "0: CRCIF (SDH_INTSTS[1]) trigger interrupt..,1: CRCIF (SDH_INTSTS[1]) trigger interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BLKDIEN,Block Transfer Done Interrupt Enable Bit" "0: BLKDIF (SDH_INTSTS[0]) trigger interrupt..,1: BLKDIF (SDH_INTSTS[0]) trigger interrupt.."
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "SDH_INTSTS,SD Interrupt Status Register"
|
|
rbitfld.long 0x00 18. "DAT1STS,DAT1 Pin Status of SD Card (Read Only)\nThis bit indicates the DAT1 pin status of SD card" "0,1"
|
|
rbitfld.long 0x00 16. "CDSTS,Card Detect Status of SD (Read Only)\nThis bit indicates the card detect pin status of SD and is used for card detection" "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
|
|
newline
|
|
rbitfld.long 0x00 13. "DITOIF,Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Data input time-out"
|
|
rbitfld.long 0x00 12. "RTOIF,Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Response time-out"
|
|
newline
|
|
rbitfld.long 0x00 8. "CDIF,SD Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card is inserted or removed" "0: No card is inserted or removed,1: There is a card inserted in or removed from SD"
|
|
rbitfld.long 0x00 7. "DAT0STS,DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "CRCSTS,CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer" "?,?,2: Positive CRC status,?,?,5: Negative CRC status,?,7: SD card programming error occurs"
|
|
rbitfld.long 0x00 3. "CRC16,CRC16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer" "0: Fault,1: OK"
|
|
newline
|
|
rbitfld.long 0x00 2. "CRC7,CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in" "0: Fault,1: OK"
|
|
rbitfld.long 0x00 1. "CRCIF,CRC7 CRC16 and CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in data-in or data-out (CRC status error) transfer" "0: No CRC error is occurred,1: CRC error is occurred"
|
|
newline
|
|
rbitfld.long 0x00 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer" "0: Not finished yet,1: Done"
|
|
rgroup.long 0x830++0x03
|
|
line.long 0x00 "SDH_RESP0,SD Receiving Response Token Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "RESPTK0,SD Receiving Response Token 0 (Read Only)\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
|
|
rgroup.long 0x834++0x03
|
|
line.long 0x00 "SDH_RESP1,SD Receiving Response Token Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RESPTK1,SD Receiving Response Token 1 (Read Only)\nThe SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "SDH_BLEN,SD Block Length Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "BLKLEN,SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "SDH_TOUT,SD Response/Data-in Time-out Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TOUT,SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out counts of response and data input"
|
|
tree.end
|
|
tree "SDH0_NS"
|
|
base ad:0x5000D000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SDH_FB_0,Shared Buffer (FIFO)"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SDH_FB_1,Shared Buffer (FIFO)"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SDH_FB_2,Shared Buffer (FIFO)"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SDH_FB_3,Shared Buffer (FIFO)"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SDH_FB_4,Shared Buffer (FIFO)"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SDH_FB_5,Shared Buffer (FIFO)"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SDH_FB_6,Shared Buffer (FIFO)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SDH_FB_7,Shared Buffer (FIFO)"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SDH_FB_8,Shared Buffer (FIFO)"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SDH_FB_9,Shared Buffer (FIFO)"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SDH_FB_10,Shared Buffer (FIFO)"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SDH_FB_11,Shared Buffer (FIFO)"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SDH_FB_12,Shared Buffer (FIFO)"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SDH_FB_13,Shared Buffer (FIFO)"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SDH_FB_14,Shared Buffer (FIFO)"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SDH_FB_15,Shared Buffer (FIFO)"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "SDH_FB_16,Shared Buffer (FIFO)"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "SDH_FB_17,Shared Buffer (FIFO)"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SDH_FB_18,Shared Buffer (FIFO)"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "SDH_FB_19,Shared Buffer (FIFO)"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "SDH_FB_20,Shared Buffer (FIFO)"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "SDH_FB_21,Shared Buffer (FIFO)"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SDH_FB_22,Shared Buffer (FIFO)"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "SDH_FB_23,Shared Buffer (FIFO)"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SDH_FB_24,Shared Buffer (FIFO)"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SDH_FB_25,Shared Buffer (FIFO)"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SDH_FB_26,Shared Buffer (FIFO)"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "SDH_FB_27,Shared Buffer (FIFO)"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "SDH_FB_28,Shared Buffer (FIFO)"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "SDH_FB_29,Shared Buffer (FIFO)"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "SDH_FB_30,Shared Buffer (FIFO)"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "SDH_FB_31,Shared Buffer (FIFO)"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "SDH_DMACTL,DMA Control and Status Register"
|
|
bitfld.long 0x00 9. "DMABUSY,DMA Transfer Is in Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not" "0: DMA transfer is not in progress,1: DMA transfer is in progress"
|
|
bitfld.long 0x00 3. "SGEN,Scatter-gather Function Enable Bit" "0: Scatter-gather function Disabled (DMA will..,1: Scatter-gather function Enabled (DMA will.."
|
|
newline
|
|
bitfld.long 0x00 1. "DMARST,Software Engine Reset\nNote: The software reset DMA related registers" "0: No effect,1: Reset internal state machine and pointers"
|
|
bitfld.long 0x00 0. "DMAEN,DMA Engine Enable Bit\nNote1: If this bit is cleared DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote2: If target abort occurred DMAEN will be cleared" "0: DMA Disabled,1: DMA Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "SDH_DMASA,DMA Transfer Starting Address Register"
|
|
hexmask.long 0x00 1.--31. 1. "DMASA,DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode this field will be interpreted as a starting.."
|
|
bitfld.long 0x00 0. "ORDER,Determined to the PAD Table Fetching Is in Order or Out of Order" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
|
|
rgroup.long 0x40C++0x03
|
|
line.long 0x00 "SDH_DMABCNT,DMA Transfer Byte Count Register"
|
|
hexmask.long 0x00 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMA transfer"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "SDH_DMAINTEN,DMA Interrupt Enable Control Register"
|
|
bitfld.long 0x00 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Bit" "0: Interrupt generation Disabled when wrong EOT..,1: Interrupt generation Enabled when wrong EOT.."
|
|
bitfld.long 0x00 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Bit" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "SDH_DMAINTSTS,DMA Interrupt Status Register"
|
|
rbitfld.long 0x00 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag (Read Only)\nWhen DMA Scatter-Gather function is enabled and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
|
|
rbitfld.long 0x00 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag (Read Only)\nNote1: This bit is read only but can be cleared by writing '1' to it.\nNote2: When DMA's bus master received ERROR response it means that target abort is happened" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "SDH_GCTL,Global Control and Status Register"
|
|
bitfld.long 0x00 1. "SDEN,Secure Digital Functionality Enable Bit" "0: SD functionality Disabled,1: SD functionality Enabled"
|
|
bitfld.long 0x00 0. "GCTLRST,Software Engine Reset" "0: No effect,1: Reset SD host"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "SDH_GINTEN,Global Interrupt Control Register"
|
|
bitfld.long 0x00 0. "DTAIEN,DMA READ/WRITE Target Abort Interrupt Enable Bit" "0: DMA READ/WRITE target abort interrupt..,1: DMA READ/WRITE target abort interrupt.."
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "SDH_GINTSTS,Global Interrupt Status Register"
|
|
rbitfld.long 0x00 0. "DTAIF,DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation" "0: No bus ERROR response received,1: Bus ERROR response received"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "SDH_CTL,SD Control and Status Register"
|
|
bitfld.long 0x00 24.--27. "SDNWR,NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BLKCNT,Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer"
|
|
newline
|
|
bitfld.long 0x00 15. "DBW,SD Data Bus Width (for 1-bit / 4-bit Selection)" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
|
|
bitfld.long 0x00 14. "CTLRST,Software Engine Reset" "0: No effect,1: Reset the internal state machine and counters"
|
|
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bitfld.long 0x00 8.--13. "CMDCODE,SD Command Code\nThe bits contain the SD command code (0x00 - 0x3F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 7. "CLKKEEP,SD Clock Enable Control" "0: SD host decided when to output clock and when..,1: SD clock always keeps free running"
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bitfld.long 0x00 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 5. "CLK74OEN,Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 4. "R2EN,Response R2 Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 3. "DOEN,Data Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 2. "DIEN,Data Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 1. "RIEN,Response Input Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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bitfld.long 0x00 0. "COEN,Command Output Enable Bit\nNote: When operation is finished this bit will be cleared automatically so don't write 0 to this bit (the controller will be abnormal)" "0: No effect,1: Enabled"
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group.long 0x824++0x03
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line.long 0x00 "SDH_CMDARG,SD Command Argument Register"
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hexmask.long 0x00 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card"
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group.long 0x828++0x03
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line.long 0x00 "SDH_INTEN,SD Interrupt Control Register"
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bitfld.long 0x00 30. "CDSRC,SD Card Detect Source Selection" "0: From SD card's DAT3 pin,1: From GPIO pin"
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bitfld.long 0x00 14. "WKIEN,Wake-up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD controller when card is inserted or removed" "0: SD Card interrupt to wake-up chip Disabled,1: SD Card interrupt to wake-up chip Enabled"
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bitfld.long 0x00 13. "DITOIEN,Data Input Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out" "0: DITOIF (SDH_INTSTS[13]) trigger interrupt..,1: DITOIF (SDH_INTSTS[13]) trigger interrupt.."
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bitfld.long 0x00 12. "RTOIEN,Response Time-out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out" "0: RTOIF (SDH_INTSTS[12]) trigger interrupt..,1: RTOIF (SDH_INTSTS[12]) trigger interrupt.."
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bitfld.long 0x00 8. "CDIEN,SD Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card is inserted or removed" "0: CDIF (SDH_INTSTS[8]) trigger interrupt Disabled,1: CDIF (SDH_INTSTS[8]) trigger interrupt Enabled"
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bitfld.long 0x00 1. "CRCIEN,CRC7 CRC16 and CRC Status Error Interrupt Enable Bit" "0: CRCIF (SDH_INTSTS[1]) trigger interrupt..,1: CRCIF (SDH_INTSTS[1]) trigger interrupt Enabled"
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bitfld.long 0x00 0. "BLKDIEN,Block Transfer Done Interrupt Enable Bit" "0: BLKDIF (SDH_INTSTS[0]) trigger interrupt..,1: BLKDIF (SDH_INTSTS[0]) trigger interrupt.."
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group.long 0x82C++0x03
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line.long 0x00 "SDH_INTSTS,SD Interrupt Status Register"
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rbitfld.long 0x00 18. "DAT1STS,DAT1 Pin Status of SD Card (Read Only)\nThis bit indicates the DAT1 pin status of SD card" "0,1"
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rbitfld.long 0x00 16. "CDSTS,Card Detect Status of SD (Read Only)\nThis bit indicates the card detect pin status of SD and is used for card detection" "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
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rbitfld.long 0x00 13. "DITOIF,Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Data input time-out"
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rbitfld.long 0x00 12. "RTOIF,Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: Not time-out,1: Response time-out"
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rbitfld.long 0x00 8. "CDIF,SD Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card is inserted or removed" "0: No card is inserted or removed,1: There is a card inserted in or removed from SD"
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rbitfld.long 0x00 7. "DAT0STS,DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port" "0,1"
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rbitfld.long 0x00 4.--6. "CRCSTS,CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer" "?,?,2: Positive CRC status,?,?,5: Negative CRC status,?,7: SD card programming error occurs"
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rbitfld.long 0x00 3. "CRC16,CRC16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC16 correctness after data-in transfer" "0: Fault,1: OK"
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rbitfld.long 0x00 2. "CRC7,CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in" "0: Fault,1: OK"
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rbitfld.long 0x00 1. "CRCIF,CRC7 CRC16 and CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in data-in or data-out (CRC status error) transfer" "0: No CRC error is occurred,1: CRC error is occurred"
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rbitfld.long 0x00 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer" "0: Not finished yet,1: Done"
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rgroup.long 0x830++0x03
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line.long 0x00 "SDH_RESP0,SD Receiving Response Token Register 0"
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hexmask.long 0x00 0.--31. 1. "RESPTK0,SD Receiving Response Token 0 (Read Only)\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
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rgroup.long 0x834++0x03
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line.long 0x00 "SDH_RESP1,SD Receiving Response Token Register 1"
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hexmask.long.byte 0x00 0.--7. 1. "RESPTK1,SD Receiving Response Token 1 (Read Only)\nThe SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
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group.long 0x838++0x03
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line.long 0x00 "SDH_BLEN,SD Block Length Register"
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hexmask.long.word 0x00 0.--10. 1. "BLKLEN,SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block"
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group.long 0x83C++0x03
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line.long 0x00 "SDH_TOUT,SD Response/Data-in Time-out Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "TOUT,SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out counts of response and data input"
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tree.end
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tree.end
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tree "SPI"
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tree "SPI0"
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base ad:0x40061000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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newline
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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newline
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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newline
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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newline
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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newline
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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newline
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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newline
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI0_NS"
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base ad:0x50061000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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newline
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
|
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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newline
|
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
|
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
|
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
|
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
|
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
|
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
|
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group.long 0x60++0x03
|
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
|
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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newline
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
|
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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newline
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
|
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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newline
|
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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newline
|
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
|
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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newline
|
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
|
|
bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
|
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newline
|
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
|
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group.long 0x64++0x03
|
|
line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
|
|
hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
|
|
rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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newline
|
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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newline
|
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
|
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
|
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
|
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
|
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
|
|
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
|
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tree "SPI1"
|
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base ad:0x40062000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI1_NS"
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base ad:0x50062000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI2"
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base ad:0x40063000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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newline
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI2_NS"
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base ad:0x50063000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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newline
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI3"
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base ad:0x40064000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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newline
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
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rgroup.long 0x30++0x03
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
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group.long 0x60++0x03
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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newline
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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newline
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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newline
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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newline
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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newline
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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newline
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
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group.long 0x64++0x03
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line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
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hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
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group.long 0x68++0x03
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line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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newline
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
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tree.end
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tree "SPI3_NS"
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base ad:0x50064000
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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newline
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.word 0x00 0.--8. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit\nWhen TX underflow event occurs in Slave mode TXUFIF (SPIx_STATUS[19]) will be set to 1" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
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group.long 0x14++0x03
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
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rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurred"
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newline
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurred"
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rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
|
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
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newline
|
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bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x03
|
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line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
|
|
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
|
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rgroup.long 0x30++0x03
|
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line.long 0x00 "SPIx_RX,SPI Data Receive Register"
|
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hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register (Read Only)\nThere are 4-level FIFO buffers in this controller"
|
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group.long 0x60++0x03
|
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line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
|
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bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
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bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
|
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bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
|
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bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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newline
|
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bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
|
|
bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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newline
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
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|
bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
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newline
|
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bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
|
|
bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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newline
|
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bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
|
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bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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newline
|
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bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
|
|
bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
|
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newline
|
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bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
|
|
hexmask.long.word 0x00 8.--17. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
|
|
rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
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newline
|
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
|
|
bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
|
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newline
|
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bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
|
|
bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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|
newline
|
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
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rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: The SPI/I2S control logic is disabled,1: The SPI/I2S control logic is enabled"
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newline
|
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
|
|
bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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newline
|
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
|
|
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
|
|
rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
|
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tree.end
|
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tree.end
|
|
tree "SYS"
|
|
base ad:0x40000000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
|
|
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\nThe CPU Lockup reset flag is set by hardware if Cortex-M23 lockup happened.\nNote1: Write 1 to clear this bit to 0.\nNote2: When CPU lockup happened under ICE is connected This flag will set to 1 but chip will not reset" "0: No reset from CPU lockup happened,1: The Cortex-M23 lockup happened and chip is.."
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bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset the Cortex-M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M23 Core and FMC are reset by.."
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bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from the Cortex-M23,1: The Cortex-M23 had issued the reset signal to.."
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bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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bitfld.long 0x00 1. "PINRF,nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
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bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
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group.long 0x08++0x03
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line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x00 29. "PDMA1RST,PDMA1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA1" "0: PDMA1 controller normal operation,1: PDMA1 controller reset"
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bitfld.long 0x00 12. "CRPTRST,CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller" "0: CRYPTO controller normal operation,1: CRYPTO controller reset"
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bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x00 6. "SDH0RST,SDHOST0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDHOST0 controller" "0: SDHOST0 controller normal operation,1: SDHOST0 controller reset"
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bitfld.long 0x00 4. "USBHRST,USB Host Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the USB Host" "0: USB Host controller normal operation,1: USB Host controller reset"
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bitfld.long 0x00 3. "EBIRST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset"
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bitfld.long 0x00 2. "PDMA0RST,PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0 (always secure)" "0: PDMA0 controller normal operation,1: PDMA0 controller reset"
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bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset"
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group.long 0x0C++0x03
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line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x00 31. "TRNGRST,TRNG Controller Reset" "0: TRNG controller normal operation,1: TRNG controller reset"
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bitfld.long 0x00 29. "I2S0RST,I2S0 Controller Reset" "0: I2S0 controller normal operation,1: I2S0 controller reset"
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bitfld.long 0x00 28. "EADCRST,EADC Controller Reset" "0: EADC controller normal operation,1: EADC controller reset"
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bitfld.long 0x00 27. "USBDRST,USBD Controller Reset" "0: USBD controller normal operation,1: USBD controller reset"
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bitfld.long 0x00 26. "OTGRST,OTG Controller Reset" "0: OTG controller normal operation,1: OTG controller reset"
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bitfld.long 0x00 24. "CAN0RST,CAN0 Controller Reset" "0: CAN0 controller normal operation,1: CAN0 controller reset"
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bitfld.long 0x00 21. "UART5RST,UART5 Controller Reset" "0: UART5 controller normal operation,1: UART5 controller reset"
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bitfld.long 0x00 20. "UART4RST,UART4 Controller Reset" "0: UART4 controller normal operation,1: UART4 controller reset"
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bitfld.long 0x00 19. "UART3RST,UART3 Controller Reset" "0: UART3 controller normal operation,1: UART3 controller reset"
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bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 15. "SPI2RST,SPI2 Controller Reset" "0: SPI2 controller normal operation,1: SPI2 controller reset"
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bitfld.long 0x00 14. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x00 13. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x00 12. "QSPI0RST,QSPI0 Controller Reset" "0: QSPI0 controller normal operation,1: QSPI0 controller reset"
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bitfld.long 0x00 10. "I2C2RST,I2C2 Controller Reset" "0: I2C2 controller normal operation,1: I2C2 controller reset"
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal..,1: Analog Comparator 0/1 controller reset"
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bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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group.long 0x10++0x03
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line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0x00 27. "ECAP1RST,ECAP1 Controller Reset" "0: ECAP1 controller normal operation,1: ECAP1 controller reset"
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bitfld.long 0x00 26. "ECAP0RST,ECAP0 Controller Reset" "0: ECAP0 controller normal operation,1: ECAP0 controller reset"
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bitfld.long 0x00 23. "QEI1RST,QEI1 Controller Reset" "0: QEI1 controller normal operation,1: QEI1 controller reset"
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bitfld.long 0x00 22. "QEI0RST,QEI0 Controller Reset" "0: QEI0 controller normal operation,1: QEI0 controller reset"
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bitfld.long 0x00 19. "BPWM1RST,BPWM1 Controller Reset" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
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bitfld.long 0x00 18. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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bitfld.long 0x00 17. "EPWM1RST,EPWM1 Controller Reset" "0: EPWM1 controller normal operation,1: EPWM1 controller reset"
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bitfld.long 0x00 16. "EPWM0RST,EPWM0 Controller Reset" "0: EPWM0 controller normal operation,1: EPWM0 controller reset"
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bitfld.long 0x00 12. "DACRST,DAC Controller Reset" "0: DAC controller normal operation,1: DAC controller reset"
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bitfld.long 0x00 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset"
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bitfld.long 0x00 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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bitfld.long 0x00 6. "SPI3RST,SPI3 Controller Reset" "0: SPI3 controller normal operation,1: SPI3 controller reset"
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bitfld.long 0x00 2. "SC2RST,SC2 Controller Reset" "0: SC2 controller normal operation,1: SC2 controller reset"
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bitfld.long 0x00 1. "SC1RST,SC1 Controller Reset" "0: SC1 controller normal operation,1: SC1 controller reset"
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bitfld.long 0x00 0. "SC0RST,SC0 Controller Reset" "0: SC0 controller normal operation,1: SC0 controller reset"
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group.long 0x18++0x03
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line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
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bitfld.long 0x00 16.--18. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: These bits are write protected" "0: Brown-out Detector threshold voltage is 1.6V,1: Brown-out Detector threshold voltage is 1.8V,2: Brown-out Detector threshold voltage is 2.0V,3: Brown-out Detector threshold voltage is 2.2V,4: Brown-out Detector threshold voltage is 2.4V,5: Brown-out Detector threshold voltage is 2.6V,6: Brown-out Detector threshold voltage is 2.8V,7: Brown-out Detector threshold voltage is 3.0V"
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bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by LIRC clock,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
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bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .\nNote1: \nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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group.long 0x1C++0x03
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line.long 0x00 "SYS_IVSCTL,Internal Voltage Source Control Register"
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bitfld.long 0x00 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result" "0: VBAT unity gain buffer function Disabled..,1: VBAT unity gain buffer function Enabled"
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bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x03
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line.long 0x00 "SYS_PORCTL0,Power-on Reset Controller Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PORMASK,Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
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group.long 0x28++0x03
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line.long 0x00 "SYS_VREFCTL,VREF Control Register"
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bitfld.long 0x00 6.--7. "PRELOADSEL,Pre-load Timing Selection (Write Protect)\nNote: These bits is write protected" "0: pre-load time is 60us for 0.1uF Capacitor,1: pre-load time is 310us for 1uF Capacitor,2: pre-load time is 2100us for 4.7uF Capacitor,3: pre-load time is 2850us for 10uF Capacitor"
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bitfld.long 0x00 5. "IBIASSEL,VREF Bias Current Selection (Write Protect)\nNote: This bit is write protected" "0: Bias current from MEGBIAS,1: Bias current from internal"
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bitfld.long 0x00 0.--4. "VREFCTL,VREF Control Bits (Write Protect)\nNote: These bits are write protected" "0: VREF is from external pin,?,?,3: VREF is internal 1.6V,?,?,?,7: VREF is internal 2.0V,?,?,?,11: VREF is internal 2.5V,?,?,?,15: VREF is internal 3.0V,?..."
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group.long 0x2C++0x03
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line.long 0x00 "SYS_USBPHY,USB PHY Control Register"
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bitfld.long 0x00 8. "OTGPHYEN,USB OTG PHY Enable \nThis bit is used to enable/disable OTG PHY function" "0: OTG PHY function Disabled (default),1: OTG PHY function Enabled"
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bitfld.long 0x00 2. "SBO,Note: This bit must always be kept 1" "0,1"
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bitfld.long 0x00 0.--1. "USBROLE,USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: These bits are write protected" "0: Standard USB Device mode,1: Standard USB Host mode,2: ID dependent mode,3: On-The-Go device mode (default)"
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group.long 0x30++0x03
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line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0: PA.7,?,2: EBI_AD7,?,4: SPI1_CLK,?,6: SC2_DAT,7: UART0_TXD,8: I2C1_SCL,?,?,11: EPWM1_CH4,12: BPWM1_CH2,13: ACMP0_WLAT,14: TM2,15: INT1"
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bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0: PA.6,?,2: EBI_AD6,?,4: SPI1_SS,?,6: SC2_CLK,7: UART0_RXD,8: I2C1_SDA,?,?,11: EPWM1_CH5,12: BPWM1_CH3,13: ACMP1_WLAT,14: TM3,15: INT0"
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bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0: PA.5,?,?,3: QSPI0_MISO1,4: SPI1_I2SMCLK,?,6: SC2_nCD,7: UART0_nCTS,8: UART5_TXD,9: I2C0_SCL,10: CAN0_TXD,?,12: BPWM0_CH5,13: EPWM0_CH0,14: QEI0_INDEX,?..."
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bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0: PA.4,?,?,3: QSPI0_MOSI1,4: SPI0_I2SMCLK,?,6: SC0_nCD,7: UART0_nRTS,8: UART5_RXD,9: I2C0_SDA,10: CAN0_RXD,?,12: BPWM0_CH4,13: EPWM0_CH1,14: QEI0_A,?..."
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bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0: PA.3,?,?,3: QSPI0_SS,4: SPI0_SS,?,6: SC0_PWR,7: UART4_TXD,8: UART1_TXD,9: I2C1_SCL,?,?,12: BPWM0_CH3,13: EPWM0_CH2,14: QEI0_B,?..."
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bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0: PA.2,?,?,3: QSPI0_CLK,4: SPI0_CLK,?,6: SC0_RST,7: UART4_RXD,8: UART1_RXD,9: I2C1_SDA,?,?,12: BPWM0_CH2,13: EPWM0_CH3,?..."
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bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0: PA.1,?,?,3: QSPI0_MISO0,4: SPI0_MISO,?,6: SC0_DAT,7: UART0_TXD,8: UART1_nCTS,9: I2C2_SCL,?,?,12: BPWM0_CH1,13: EPWM0_CH4,?,15: DAC1_ST"
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bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0: PA.0,?,?,3: QSPI0_MOSI0,4: SPI0_MOSI,?,6: SC0_CLK,7: UART0_RXD,8: UART1_nRTS,9: I2C2_SDA,?,?,12: BPWM0_CH0,13: EPWM0_CH5,?,15: DAC0_ST"
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group.long 0x34++0x03
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line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0: PA.15,?,2: I2S0_DO,3: UART0_RXD,?,5: SPI2_MOSI,6: I2C2_SDA,7: SC2_CLK,?,?,?,11: BPWM1_CH5,12: EPWM0_SYNC_IN,?,14: USB_OTG_ID,?..."
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bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0: PA.14,?,2: I2S0_DI,3: UART0_TXD,?,5: SPI2_MISO,6: I2C2_SCL,7: SC2_DAT,?,?,?,11: BPWM1_CH4,12: QEI1_B,?,14: USB_D+,?..."
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bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0: PA.13,?,2: I2S0_MCLK,3: UART4_RXD,4: I2C1_SDA,5: SPI2_CLK,6: CAN0_RXD,7: SC2_RST,?,?,?,11: BPWM1_CH3,12: QEI1_A,?,14: USB_D,?..."
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bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0: PA.12,?,2: I2S0_BCLK,3: UART4_TXD,4: I2C1_SCL,5: SPI2_SS,6: CAN0_TXD,7: SC2_PWR,?,?,?,11: BPWM1_CH2,12: QEI1_INDEX,?,14: USB_VBUS,?..."
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bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0: PA.11,1: ACMP0_P0,2: EBI_nRD,3: SC2_PWR,4: SPI2_SS,?,6: USCI0_CLK,7: I2C2_SCL,?,9: BPWM0_CH0,10: EPWM0_SYNC_OUT,?,?,13: TM0_EXT,14: DAC1_ST,?..."
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bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0: PA.10,1: ACMP1_P0,2: EBI_nWR,3: SC2_RST,4: SPI2_CLK,?,6: USCI0_DAT0,7: I2C2_SDA,?,9: BPWM0_CH1,10: QEI1_INDEX,11: ECAP0_IC0,?,13: TM1_EXT,14: DAC0_ST,?..."
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bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0: PA.9,?,2: EBI_MCLK,3: SC2_DAT,4: SPI2_MISO,?,6: USCI0_DAT1,7: UART1_TXD,?,9: BPWM0_CH2,10: QEI1_A,11: ECAP0_IC1,?,13: TM2_EXT,?..."
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bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0: PA.8,?,2: EBI_ALE,3: SC2_CLK,4: SPI2_MOSI,?,6: USCI0_CTL1,7: UART1_RXD,?,9: BPWM0_CH3,10: QEI1_B,11: ECAP0_IC2,?,13: TM3_EXT,?,15: INT4"
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group.long 0x38++0x03
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line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0: PB.7,1: EADC0_CH7,2: EBI_nWRL,?,4: USCI1_DAT0,?,6: UART1_TXD,?,8: EBI_nCS0,?,10: BPWM1_CH4,11: EPWM1_BRAKE0,12: EPWM1_CH4,13: INT5,14: USB_VBUS_ST,15: ACMP0_O"
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bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0: PB.6,1: EADC0_CH6,2: EBI_nWRH,?,4: USCI1_DAT1,?,6: UART1_RXD,?,8: EBI_nCS1,?,10: BPWM1_CH5,11: EPWM1_BRAKE1,12: EPWM1_CH5,13: INT4,14: USB_VBUS_EN,15: ACMP1_O"
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bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0: PB.5,1: EADC0_CH5\nACMP1_N,2: EBI_ADR0,3: SD0_DAT3,?,5: SPI1_MISO,6: I2C0_SCL,7: UART5_TXD,8: USCI1_CTL0,9: SC0_CLK,10: I2S0_BCLK,11: EPWM0_CH0,?,?,14: TM0,15: INT0"
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bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0: PB.4,1: EADC0_CH4\nACMP1_P1,2: EBI_ADR1,3: SD0_DAT2,?,5: SPI1_MOSI,6: I2C0_SDA,7: UART5_RXD,8: USCI1_CTL1,9: SC0_DAT,10: I2S0_MCLK,11: EPWM0_CH1,?,?,14: TM1,15: INT1"
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bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0: PB.3,1: EADC0_CH3\nACMP0_N,2: EBI_ADR2,3: SD0_DAT1,?,5: SPI1_CLK,6: UART1_TXD,7: UART5_nRTS,8: USCI1_DAT1,9: SC0_RST,10: I2S0_DI,11: EPWM0_CH2,?,?,14: TM2,15: INT2"
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bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0: PB.2,1: EADC0_CH2\nACMP0_P1,2: EBI_ADR3,3: SD0_DAT0,?,5: SPI1_SS,6: UART1_RXD,7: UART5_nCTS,8: USCI1_DAT0,9: SC0_PWR,10: I2S0_DO,11: EPWM0_CH3,?,?,14: TM3,15: INT3"
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bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0: PB.1,1: EADC0_CH1,2: EBI_ADR8,3: SD0_CLK,?,5: SPI1_I2SMCLK,6: SPI3_I2SMCLK,7: UART2_TXD,8: USCI1_CLK,9: I2C1_SCL,10: I2S0_LRCK,11: EPWM0_CH4,12: EPWM1_CH4,13: EPWM0_BRAKE0,?..."
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bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0: PB.0,1: EADC0_CH0,2: EBI_ADR9,3: SD0_CMD,?,?,?,7: UART2_RXD,8: SPI0_I2SMCLK,9: I2C1_SDA,?,11: EPWM0_CH5,12: EPWM1_CH5,13: EPWM0_BRAKE1,?..."
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group.long 0x3C++0x03
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line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0: PB.15,1: EADC0_CH15,2: EBI_AD12,3: SC1_PWR,4: SPI0_SS,5: USCI0_CTL1,6: UART0_nCTS,7: UART3_TXD,8: I2C2_SMBAL,?,?,11: EPWM1_CH0,?,13: TM0_EXT,14: USB_VBUS_EN,?..."
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bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0: PB.14,1: EADC0_CH14,2: EBI_AD13,3: SC1_RST,4: SPI0_CLK,5: USCI0_DAT1,6: UART0_nRTS,7: UART3_RXD,8: I2C2_SMBSUS,?,?,11: EPWM1_CH1,?,13: TM1_EXT,14: CLKO,15: USB_VBUS_ST"
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bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0: PB.13,1: EADC0_CH13\nDAC1_OUT\nACMP0_P3\nACMP1_P3,2: EBI_AD14,3: SC1_DAT,4: SPI0_MISO,5: USCI0_DAT0,6: UART0_TXD,7: UART3_nRTS,8: I2C2_SCL,?,?,11: EPWM1_CH2,?,13: TM2_EXT,?..."
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bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0: PB.12,1: EADC0_CH12\nDAC0_OUT\nACMP0_P2\nACMP1_P2,2: EBI_AD15,3: SC1_CLK,4: SPI0_MOSI,5: USCI0_CLK,6: UART0_RXD,7: UART3_nCTS,8: I2C2_SDA,9: SD0_nCD,?,11: EPWM1_CH3,?,13: TM3_EXT,?..."
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bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0: PB.11,1: EADC0_CH11,2: EBI_ADR16,?,?,5: UART0_nCTS,6: UART4_TXD,7: I2C1_SCL,8: CAN0_TXD,9: SPI0_I2SMCLK,10: BPWM1_CH0,11: SPI3_CLK,?..."
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bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0: PB.10,1: EADC0_CH10,2: EBI_ADR17,?,4: USCI1_CTL0,5: UART0_nRTS,6: UART4_RXD,7: I2C1_SDA,8: CAN0_RXD,?,10: BPWM1_CH1,11: SPI3_SS,?..."
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bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0: PB.9,1: EADC0_CH9,2: EBI_ADR18,?,4: USCI1_CTL1,5: UART0_TXD,6: UART1_nCTS,7: I2C1_SMBAL,?,?,10: BPWM1_CH2,11: SPI3_MISO,?,13: INT7,?..."
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bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0: PB.8,1: EADC0_CH8,2: EBI_ADR19,?,4: USCI1_CLK,5: UART0_RXD,6: UART1_nRTS,7: I2C1_SMBSUS,?,?,10: BPWM1_CH3,11: SPI3_MOSI,?,13: INT6,?..."
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group.long 0x40++0x03
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line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0: PC.7,?,2: EBI_AD9,?,4: SPI1_MISO,5: UART4_TXD,6: SC2_PWR,7: UART0_nCTS,8: I2C1_SMBAL,?,?,11: EPWM1_CH2,12: BPWM1_CH0,?,14: TM0,15: INT3"
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bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0: PC.6,?,2: EBI_AD8,?,4: SPI1_MOSI,5: UART4_RXD,6: SC2_RST,7: UART0_nRTS,8: I2C1_SMBSUS,?,?,11: EPWM1_CH3,12: BPWM1_CH1,?,14: TM1,15: INT2"
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bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0: PC.5,?,2: EBI_AD5,?,4: QSPI0_MISO1,?,?,?,8: UART2_TXD,9: I2C1_SCL,10: CAN0_TXD,11: UART4_TXD,12: EPWM1_CH0,?..."
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bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0: PC.4,?,2: EBI_AD4,?,4: QSPI0_MOSI1,5: SC1_nCD,6: I2S0_BCLK,7: SPI1_I2SMCLK,8: UART2_RXD,9: I2C1_SDA,10: CAN0_RXD,11: UART4_RXD,12: EPWM1_CH1,?..."
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bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0: PC.3,?,2: EBI_AD3,?,4: QSPI0_SS,5: SC1_PWR,6: I2S0_MCLK,7: SPI1_MISO,8: UART2_nRTS,9: I2C0_SMBAL,?,11: UART3_TXD,12: EPWM1_CH2,?..."
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bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0: PC.2,?,2: EBI_AD2,?,4: QSPI0_CLK,5: SC1_RST,6: I2S0_DI,7: SPI1_MOSI,8: UART2_nCTS,9: I2C0_SMBSUS,?,11: UART3_RXD,12: EPWM1_CH3,?..."
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bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0: PC.1,?,2: EBI_AD1,?,4: QSPI0_MISO0,5: SC1_DAT,6: I2S0_DO,7: SPI1_CLK,8: UART2_TXD,9: I2C0_SCL,?,?,12: EPWM1_CH4,?,14: ACMP0_O,?..."
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bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0: PC.0,?,2: EBI_AD0,?,4: QSPI0_MOSI0,5: SC1_CLK,6: I2S0_LRCK,7: SPI1_SS,8: UART2_RXD,9: I2C0_SDA,?,?,12: EPWM1_CH5,?,14: ACMP1_O,?..."
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group.long 0x44++0x03
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line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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bitfld.long 0x00 20.--23. "PC13MFP,PC.13 Multi-function Pin Selection" "0: PC.13,?,2: EBI_ADR10,3: SC2_nCD,4: SPI2_I2SMCLK,?,6: USCI0_CTL0,7: UART2_TXD,?,9: BPWM0_CH4,?,?,?,13: CLKO,14: EADC0_ST,?..."
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bitfld.long 0x00 16.--19. "PC12MFP,PC.12 Multi-function Pin Selection" "0: PC.12,?,2: EBI_ADR4,3: UART0_TXD,4: I2C0_SCL,?,6: SPI3_MISO,?,?,9: SC0_nCD,?,11: ECAP1_IC2,12: EPWM1_CH0,?,14: ACMP0_O,?..."
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bitfld.long 0x00 12.--15. "PC11MFP,PC.11 Multi-function Pin Selection" "0: PC.11,?,2: EBI_ADR5,3: UART0_RXD,4: I2C0_SDA,?,6: SPI3_MOSI,?,?,?,?,11: ECAP1_IC1,12: EPWM1_CH1,?,14: ACMP1_O,?..."
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bitfld.long 0x00 8.--11. "PC10MFP,PC.10 Multi-function Pin Selection" "0: PC.10,?,2: EBI_ADR6,?,?,?,6: SPI3_CLK,7: UART3_TXD,?,?,?,11: ECAP1_IC0,12: EPWM1_CH2,?..."
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bitfld.long 0x00 4.--7. "PC9MFP,PC.9 Multi-function Pin Selection" "0: PC.9,?,2: EBI_ADR7,?,?,?,6: SPI3_SS,7: UART3_RXD,?,?,?,?,12: EPWM1_CH3,?..."
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bitfld.long 0x00 0.--3. "PC8MFP,PC.8 Multi-function Pin Selection" "0: PC.8,?,2: EBI_ADR16,?,4: I2C0_SDA,5: UART4_nCTS,?,?,8: UART1_RXD,?,?,11: EPWM1_CH1,12: BPWM1_CH4,?..."
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group.long 0x48++0x03
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line.long 0x00 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PD7MFP,PD.7 Multi-function Pin Selection" "0: PD.7,?,?,3: UART1_TXD,4: I2C0_SCL,5: SPI1_MISO,6: USCI1_CLK,?,8: SC1_PWR,?..."
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bitfld.long 0x00 24.--27. "PD6MFP,PD.6 Multi-function Pin Selection" "0: PD.6,?,?,3: UART1_RXD,4: I2C0_SDA,5: SPI1_MOSI,6: USCI1_DAT1,?,8: SC1_RST,?..."
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bitfld.long 0x00 20.--23. "PD5MFP,PD.5 Multi-function Pin Selection" "0: PD.5,?,?,?,4: I2C1_SCL,5: SPI1_CLK,6: USCI1_DAT0,?,8: SC1_DAT,?..."
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bitfld.long 0x00 16.--19. "PD4MFP,PD.4 Multi-function Pin Selection" "0: PD.4,?,?,3: USCI0_CTL0,4: I2C1_SDA,5: SPI1_SS,6: USCI1_CTL1,?,8: SC1_CLK,?,?,?,?,?,14: USB_VBUS_ST,?..."
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bitfld.long 0x00 12.--15. "PD3MFP,PD.3 Multi-function Pin Selection" "0: PD.3,?,2: EBI_AD10,3: USCI0_CTL1,4: SPI0_SS,5: UART3_nRTS,6: USCI1_CTL0,7: SC2_PWR,8: SC1_nCD,9: UART0_TXD,?..."
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bitfld.long 0x00 8.--11. "PD2MFP,PD.2 Multi-function Pin Selection" "0: PD.2,?,2: EBI_AD11,3: USCI0_DAT1,4: SPI0_CLK,5: UART3_nCTS,?,7: SC2_RST,?,9: UART0_RXD,?..."
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bitfld.long 0x00 4.--7. "PD1MFP,PD.1 Multi-function Pin Selection" "0: PD.1,?,2: EBI_AD12,3: USCI0_DAT0,4: SPI0_MISO,5: UART3_TXD,6: I2C2_SCL,7: SC2_DAT,?..."
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bitfld.long 0x00 0.--3. "PD0MFP,PD.0 Multi-function Pin Selection" "0: PD.0,?,2: EBI_AD13,3: USCI0_CLK,4: SPI0_MOSI,5: UART3_RXD,6: I2C2_SDA,7: SC2_CLK,?,?,?,?,?,?,14: TM2,?..."
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group.long 0x4C++0x03
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line.long 0x00 "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
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bitfld.long 0x00 24.--27. "PD14MFP,PD.14 Multi-function Pin Selection" "0: PD.14,?,2: EBI_nCS0,3: SPI3_I2SMCLK,4: SC1_nCD,5: USCI0_CTL0,6: SPI0_I2SMCLK,?,?,?,?,11: EPWM0_CH4,?..."
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bitfld.long 0x00 20.--23. "PD13MFP,PD.13 Multi-function Pin Selection" "0: PD.13,?,2: EBI_AD10,3: SD0_nCD,4: SPI0_I2SMCLK,5: SPI1_I2SMCLK,?,7: SC2_nCD,?..."
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bitfld.long 0x00 16.--19. "PD12MFP,PD.12 Multi-function Pin Selection" "0: PD.12,?,2: EBI_nCS0,?,?,?,?,7: UART2_RXD,?,9: BPWM0_CH5,10: QEI0_INDEX,?,?,13: CLKO,14: EADC0_ST,15: INT5"
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bitfld.long 0x00 12.--15. "PD11MFP,PD.11 Multi-function Pin Selection" "0: PD.11,?,2: EBI_nCS1,3: UART1_TXD,4: CAN0_TXD,?,?,?,?,?,10: QEI0_A,?,?,?,?,15: INT6"
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bitfld.long 0x00 8.--11. "PD10MFP,PD.10 Multi-function Pin Selection" "0: PD.10,?,2: EBI_nCS2,3: UART1_RXD,4: CAN0_RXD,?,?,?,?,?,10: QEI0_B,?,?,?,?,15: INT7"
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bitfld.long 0x00 4.--7. "PD9MFP,PD.9 Multi-function Pin Selection" "0: PD.9,?,2: EBI_AD7,3: I2C2_SCL,4: UART2_nCTS,?..."
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bitfld.long 0x00 0.--3. "PD8MFP,PD.8 Multi-function Pin Selection" "0: PD.8,?,2: EBI_AD6,3: I2C2_SDA,4: UART2_nRTS,?..."
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group.long 0x50++0x03
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line.long 0x00 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PE7MFP,PE.7 Multi-function Pin Selection" "0: PE.7,?,?,3: SD0_CMD,?,?,?,?,8: UART5_TXD,?,?,11: QEI1_INDEX,12: EPWM0_CH0,13: BPWM0_CH5,?..."
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bitfld.long 0x00 24.--27. "PE6MFP,PE.6 Multi-function Pin Selection" "0: PE.6,?,?,3: SD0_CLK,?,5: SPI3_I2SMCLK,6: SC0_nCD,7: USCI0_CTL0,8: UART5_RXD,?,?,11: QEI1_A,12: EPWM0_CH1,13: BPWM0_CH4,?..."
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bitfld.long 0x00 20.--23. "PE5MFP,PE.5 Multi-function Pin Selection" "0: PE.5,?,2: EBI_nRD,3: SD0_DAT3,?,5: SPI3_SS,6: SC0_PWR,7: USCI0_CTL1,?,?,?,11: QEI1_B,12: EPWM0_CH2,13: BPWM0_CH3,?..."
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bitfld.long 0x00 16.--19. "PE4MFP,PE.4 Multi-function Pin Selection" "0: PE.4,?,2: EBI_nWR,3: SD0_DAT2,?,5: SPI3_CLK,6: SC0_RST,7: USCI0_DAT1,?,?,?,11: QEI0_INDEX,12: EPWM0_CH3,13: BPWM0_CH2,?..."
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bitfld.long 0x00 12.--15. "PE3MFP,PE.3 Multi-function Pin Selection" "0: PE.3,?,2: EBI_MCLK,3: SD0_DAT1,?,5: SPI3_MISO,6: SC0_DAT,7: USCI0_DAT0,?,?,?,11: QEI0_A,12: EPWM0_CH4,13: BPWM0_CH1,?..."
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bitfld.long 0x00 8.--11. "PE2MFP,PE.2 Multi-function Pin Selection" "0: PE.2,?,2: EBI_ALE,3: SD0_DAT0,?,5: SPI3_MOSI,6: SC0_CLK,7: USCI0_CLK,?,?,?,11: QEI0_B,12: EPWM0_CH5,13: BPWM0_CH0,?..."
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bitfld.long 0x00 4.--7. "PE1MFP,PE.1 Multi-function Pin Selection" "0: PE.1,?,2: EBI_AD10,3: QSPI0_MISO0,4: SC2_DAT,5: I2S0_BCLK,6: SPI1_MISO,7: UART3_TXD,8: I2C1_SCL,9: UART4_nCTS,?..."
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bitfld.long 0x00 0.--3. "PE0MFP,PE.0 Multi-function Pin Selection" "0: PE.0,?,2: EBI_AD11,3: QSPI0_MOSI0,4: SC2_CLK,5: I2S0_MCLK,6: SPI1_MOSI,7: UART3_RXD,8: I2C1_SDA,9: UART4_nRTS,?..."
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group.long 0x54++0x03
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line.long 0x00 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PE15MFP,PE.15 Multi-function Pin Selection" "0: PE.15,?,2: EBI_AD9,3: UART2_RXD,4: CAN0_RXD,?..."
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bitfld.long 0x00 24.--27. "PE14MFP,PE.14 Multi-function Pin Selection" "0: PE.14,?,2: EBI_AD8,3: UART2_TXD,4: CAN0_TXD,?..."
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bitfld.long 0x00 20.--23. "PE13MFP,PE.13 Multi-function Pin Selection" "0: PE.13,?,2: EBI_ADR15,?,4: I2C0_SCL,5: UART4_nRTS,?,?,8: UART1_TXD,?,10: EPWM0_CH5,11: EPWM1_CH0,12: BPWM1_CH5,13: ECAP1_IC0,?..."
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bitfld.long 0x00 16.--19. "PE12MFP,PE.12 Multi-function Pin Selection" "0: PE.12,?,2: EBI_ADR14,?,4: I2S0_LRCK,5: SPI2_I2SMCLK,6: USCI1_CLK,?,8: UART1_nRTS,?,10: EPWM0_CH4,?,?,13: ECAP1_IC1,14: TRACE_CLK,?..."
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bitfld.long 0x00 12.--15. "PE11MFP,PE.11 Multi-function Pin Selection" "0: PE.11,?,2: EBI_ADR13,?,4: I2S0_DO,5: SPI2_SS,6: USCI1_DAT1,7: UART3_RXD,8: UART1_nCTS,?,10: EPWM0_CH3,11: EPWM1_BRAKE1,?,13: ECAP1_IC2,14: TRACE_DATA0,?..."
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bitfld.long 0x00 8.--11. "PE10MFP,PE.10 Multi-function Pin Selection" "0: PE.10,?,2: EBI_ADR12,?,4: I2S0_DI,5: SPI2_MOSI,6: USCI1_DAT0,7: UART3_TXD,?,?,10: EPWM0_CH2,11: EPWM1_BRAKE0,12: ECAP0_IC2,?,14: TRACE_DATA1,?..."
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bitfld.long 0x00 4.--7. "PE9MFP,PE.9 Multi-function Pin Selection" "0: PE.9,?,2: EBI_ADR11,?,4: I2S0_MCLK,5: SPI2_MISO,6: USCI1_CTL0,7: UART2_RXD,?,?,10: EPWM0_CH1,11: EPWM0_BRAKE1,12: ECAP0_IC1,?,14: TRACE_DATA2,?..."
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bitfld.long 0x00 0.--3. "PE8MFP,PE.8 Multi-function Pin Selection" "0: PE.8,?,2: EBI_ADR10,?,4: I2S0_BCLK,5: SPI2_CLK,6: USCI1_CTL1,7: UART2_TXD,?,?,10: EPWM0_CH0,11: EPWM0_BRAKE0,12: ECAP0_IC0,?,14: TRACE_DATA3,?..."
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group.long 0x58++0x03
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line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0: PF.7,?,2: EBI_ADR18,3: SC0_DAT,4: I2S0_DO,5: SPI0_MISO,6: UART4_TXD,?,?,?,10: TAMPER1,?..."
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bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0: PF.6,?,2: EBI_ADR19,3: SC0_CLK,4: I2S0_LRCK,5: SPI0_MOSI,6: UART4_RXD,7: EBI_nCS0,?,?,10: TAMPER0,?..."
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bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0: PF.5,?,2: UART2_RXD,?,4: UART2_nCTS,?,?,?,8: BPWM0_CH4,9: EPWM0_SYNC_OUT,10: X32_IN,11: EADC0_ST,?..."
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bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection" "0: PF.4,?,2: UART2_TXD,?,4: UART2_nRTS,?,?,?,8: BPWM0_CH5,?,10: X32_OUT,?..."
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newline
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bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection" "0: PF.3,?,2: EBI_nCS0,3: UART0_TXD,4: I2C0_SCL,?,?,?,?,?,10: XT1_IN,11: BPWM1_CH0,?..."
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bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0: PF.2,?,2: EBI_nCS1,3: UART0_RXD,4: I2C0_SDA,5: QSPI0_CLK,?,?,?,?,10: XT1_OUT,11: BPWM1_CH1,?..."
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newline
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bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0: PF.1,?,2: UART1_RXD,3: I2C1_SDA,?,?,?,?,?,?,?,?,12: BPWM1_CH1,?,14: ICE_CLK,?..."
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bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0: PF.0,?,2: UART1_TXD,3: I2C1_SCL,?,?,?,?,?,?,?,?,12: BPWM1_CH0,?,14: ICE_DAT,?..."
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group.long 0x5C++0x03
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line.long 0x00 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
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bitfld.long 0x00 12.--15. "PF11MFP,PF.11 Multi-function Pin Selection" "0: PF.11,?,2: EBI_ADR14,3: SPI2_MOSI,?,?,?,?,?,?,10: TAMPER5,?,?,13: TM3,?..."
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bitfld.long 0x00 8.--11. "PF10MFP,PF.10 Multi-function Pin Selection" "0: PF.10,?,2: EBI_ADR15,3: SC0_nCD,4: I2S0_BCLK,5: SPI0_I2SMCLK,?,?,?,?,10: TAMPER4,?..."
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newline
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bitfld.long 0x00 4.--7. "PF9MFP,PF.9 Multi-function Pin Selection" "0: PF.9,?,2: EBI_ADR16,3: SC0_PWR,4: I2S0_MCLK,5: SPI0_SS,?,?,?,?,10: TAMPER3,?..."
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bitfld.long 0x00 0.--3. "PF8MFP,PF.8 Multi-function Pin Selection" "0: PF.8,?,2: EBI_ADR17,3: SC0_RST,4: I2S0_DI,5: SPI0_CLK,?,?,?,?,10: TAMPER2,?..."
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group.long 0x60++0x03
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line.long 0x00 "SYS_GPG_MFPL,GPIOG Low Byte Multiple Function Control Register"
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bitfld.long 0x00 16.--19. "PG4MFP,PG.4 Multi-function Pin Selection" "0: PG.4,?,2: EBI_ADR13,3: SPI2_MISO,?,?,?,?,?,?,?,?,?,13: TM2,?..."
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bitfld.long 0x00 12.--15. "PG3MFP,PG.3 Multi-function Pin Selection" "0: PG.3,?,2: EBI_ADR12,3: SPI2_CLK,4: I2C0_SMBSUS,5: I2C1_SDA,?,?,?,?,?,?,?,13: TM1,?..."
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newline
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bitfld.long 0x00 8.--11. "PG2MFP,PG.2 Multi-function Pin Selection" "0: PG.2,?,2: EBI_ADR11,3: SPI2_SS,4: I2C0_SMBAL,5: I2C1_SCL,?,?,?,?,?,?,?,13: TM0,?..."
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group.long 0x64++0x03
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line.long 0x00 "SYS_GPG_MFPH,GPIOG High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PG15MFP,PG.15 Multi-function Pin Selection" "0: PG.15,?,?,?,?,?,?,?,?,?,?,?,?,?,14: CLKO,15: EADC0_ST"
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bitfld.long 0x00 24.--27. "PG14MFP,PG.14 Multi-function Pin Selection" "0: PG.14,?,2: EBI_AD5,?,?,?,?,?,?,?,?,?,12: BPWM0_CH0,?..."
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newline
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bitfld.long 0x00 20.--23. "PG13MFP,PG.13 Multi-function Pin Selection" "0: PG.13,?,2: EBI_AD4,?,?,?,?,?,?,?,?,?,12: BPWM0_CH1,?..."
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bitfld.long 0x00 16.--19. "PG12MFP,PG.12 Multi-function Pin Selection" "0: PG.12,?,2: EBI_AD3,?,?,?,?,?,?,?,?,?,12: BPWM0_CH2,?..."
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newline
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bitfld.long 0x00 12.--15. "PG11MFP,PG.11 Multi-function Pin Selection" "0: PG.11,?,2: EBI_AD2,?,?,?,?,?,?,?,?,?,12: BPWM0_CH3,?..."
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bitfld.long 0x00 8.--11. "PG10MFP,PG.10 Multi-function Pin Selection" "0: PG.10,?,2: EBI_AD1,?,?,?,?,?,?,?,?,?,12: BPWM0_CH4,?..."
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newline
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bitfld.long 0x00 4.--7. "PG9MFP,PG.9 Multi-function Pin Selection" "0: PG.9,?,2: EBI_AD0,?,?,?,?,?,?,?,?,?,12: BPWM0_CH5,?..."
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bitfld.long 0x00 0.--3. "PG8MFP,PG.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x68++0x03
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line.long 0x00 "SYS_GPH_MFPL,GPIOH Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PH7MFP,PH.7 Multi-function Pin Selection" "0: PH.7,?,2: EBI_ADR0,3: SPI1_SS,?..."
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bitfld.long 0x00 24.--27. "PH6MFP,PH.6 Multi-function Pin Selection" "0: PH.6,?,2: EBI_ADR1,3: SPI1_CLK,?..."
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newline
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bitfld.long 0x00 20.--23. "PH5MFP,PH.5 Multi-function Pin Selection" "0: PH.5,?,2: EBI_ADR2,3: SPI1_MOSI,?..."
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bitfld.long 0x00 16.--19. "PH4MFP,PH.4 Multi-function Pin Selection" "0: PH.4,?,2: EBI_ADR3,3: SPI1_MISO,?..."
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group.long 0x6C++0x03
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line.long 0x00 "SYS_GPH_MFPH,GPIOH High Byte Multiple Function Control Register"
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bitfld.long 0x00 12.--15. "PH11MFP,PH.11 Multi-function Pin Selection" "0: PH.11,?,2: EBI_AD15,3: QSPI0_MOSI1,?,?,?,7: UART4_RXD,8: UART0_RXD,?,?,11: EPWM0_CH5,?..."
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bitfld.long 0x00 8.--11. "PH10MFP,PH.10 Multi-function Pin Selection" "0: PH.10,?,2: EBI_AD14,3: QSPI0_MISO1,4: SC2_nCD,5: I2S0_LRCK,6: SPI1_I2SMCLK,7: UART4_TXD,8: UART0_TXD,?..."
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newline
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bitfld.long 0x00 4.--7. "PH9MFP,PH.9 Multi-function Pin Selection" "0: PH.9,?,2: EBI_AD13,3: QSPI0_SS,4: SC2_RST,5: I2S0_DO,6: SPI1_SS,7: UART3_nCTS,8: I2C1_SMBSUS,9: I2C2_SDA,10: UART1_RXD,?..."
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bitfld.long 0x00 0.--3. "PH8MFP,PH.8 Multi-function Pin Selection" "0: PH.8,?,2: EBI_AD12,3: QSPI0_CLK,4: SC2_PWR,5: I2S0_DI,6: SPI1_CLK,7: UART3_nRTS,8: I2C1_SMBAL,9: I2C2_SCL,10: UART1_TXD,?..."
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group.long 0x80++0x03
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line.long 0x00 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x84++0x03
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line.long 0x00 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x88++0x03
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line.long 0x00 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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|
bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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|
bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x8C++0x03
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line.long 0x00 "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register"
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|
bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
|
bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
|
bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
|
bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
|
bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
|
bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
|
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x90++0x03
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line.long 0x00 "SYS_GPE_MFOS,GPIOE Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x94++0x03
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line.long 0x00 "SYS_GPF_MFOS,GPIOF Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x98++0x03
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line.long 0x00 "SYS_GPG_MFOS,GPIOG Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0x9C++0x03
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line.long 0x00 "SYS_GPH_MFOS,GPIOH Multiple Function Output Select Register"
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bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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newline
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bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.."
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group.long 0xC0++0x03
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line.long 0x00 "SYS_SRAMICTL,System SRAM Interrupt Enable Control Register"
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bitfld.long 0x00 0. "PERRIEN,SRAM Parity Check Error Interrupt Enable Bit" "0: SRAM parity check error interrupt Disabled,1: SRAM parity check error interrupt Enabled"
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rgroup.long 0xC4++0x03
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line.long 0x00 "SYS_SRAMSTS,System SRAM Parity Error Status Register"
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bitfld.long 0x00 0. "PERRIF,SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred" "0: No System SRAM parity error,1: System SRAM parity error occur"
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rgroup.long 0xC8++0x03
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line.long 0x00 "SYS_SRAMEADR,System SRAM Parity Check Error Address Register"
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hexmask.long 0x00 0.--31. 1. "ERRADDR,System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address"
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group.long 0xDC++0x03
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line.long 0x00 "SYS_SRAMPCTL,System SRAM Power Mode Control Register"
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bitfld.long 0x00 22.--23. "SRAM1PM3,Bank1 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 20.--21. "SRAM1PM2,Bank1 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 18.--19. "SRAM1PM1,Bank1 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 16.--17. "SRAM1PM0,Bank1 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 14.--15. "SRAM0PM3,Bank0 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 12.--13. "SRAM0PM2,Bank0 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 10.--11. "SRAM0PM1,Bank0 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 8.--9. "SRAM0PM0,Bank0 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2000_0000 - 0x2000_1FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 4.--5. "RETCNT,SRAM Retention Count (Write Protect)\nThis field can config SRAM marco retention time in unit of HIRC period.\nNote: These bits are write protected" "0: one HIRC period,1: two HIRC periods,2: three HIRC periods,3: four HIRC periods"
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bitfld.long 0x00 0.--3. "STACK,System SRAM Stack Position (Write Protect)\nThis field must config the system SRAM marco that first SRAM address accessed by CPU in power-on process.\nNote: These bits are write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xE0++0x03
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line.long 0x00 "SYS_SRAMPPCT,Peripheral SRAM Power Mode Control Register"
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bitfld.long 0x00 8.--9. "FMC,FMC SRAM Power Mode Select (Write Protect)\nThis field can control FMC cache sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 6.--7. "PDMA1,PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA1 sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 4.--5. "PDMA0,PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA0 (always secure) sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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bitfld.long 0x00 2.--3. "USBD,USB Device SRAM Power Mode Select (Write Protect)\nThis field can control USB device sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved (Write Ignore)"
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newline
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bitfld.long 0x00 0.--1. "CAN,CAN SRAM Power Mode Select (Write Protect)\nThis field can control CAN sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep.." "0: Normal mode,1: Retention mode,2: Power shut down mode,3: Reserved"
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group.long 0xE4++0x03
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line.long 0x00 "SYS_TCTL48M,HIRC 48M Trim Control Register"
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim 48M reference clock is from..,1: HIRC trim 48M reference clock is from.."
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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newline
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
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|
group.long 0xE8++0x03
|
|
line.long 0x00 "SYS_TIEN48M,HIRC 48M Trim Interrupt Enable Register"
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|
bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_TISTS48M [2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_TISTS48M [2]) status to..,1: Enable CLKERRIF(SYS_TISTS48M [2]) status to.."
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bitfld.long 0x00 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_TISTS48M [1]) status to..,1: Enable TFAILIF(SYS_TISTS48M[1]) status to.."
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|
group.long 0xEC++0x03
|
|
line.long 0x00 "SYS_TISTS48M,HIRC 48M Trim Interrupt Status Register"
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|
bitfld.long 0x00 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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|
bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
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|
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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group.long 0xF0++0x03
|
|
line.long 0x00 "SYS_TCTL12M,HIRC 12M Trim Control Register"
|
|
bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from external..,1: HIRC trim reference clock is from internal.."
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|
bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved"
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|
group.long 0xF4++0x03
|
|
line.long 0x00 "SYS_TIEN12M,HIRC 12M Trim Interrupt Enable Register"
|
|
bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation an interrupt will be.." "0: Disable CLKERRIF(SYS_TISTS12M[2]) status to..,1: Enable CLKERRIF(SYS_TISTS12M[2]) status to.."
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bitfld.long 0x00 1. "TFAILIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]).\nIf this bit.." "0: Disable TFAILIF(SYS_TISTS12M[1]) status to..,1: Enable TFAILIF(SYS_TISTS12M[1]) status to.."
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|
group.long 0xF8++0x03
|
|
line.long 0x00 "SYS_TISTS12M,HIRC 12M Trim Interrupt Status Register"
|
|
bitfld.long 0x00 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.."
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|
group.long 0x100++0x03
|
|
line.long 0x00 "SYS_REGLCTL,Register Lock Control Register"
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|
hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code \nSome registers have write-protection function"
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group.long 0x1EC++0x03
|
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line.long 0x00 "SYS_PORCTL1,Power-on Reset Controller Register 1"
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hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
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group.long 0x1F8++0x03
|
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line.long 0x00 "SYS_PLCTL,Power Level Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "LVSPRD,LDO Voltage Scaling Period (Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step.\nNote: These bits are write protected"
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bitfld.long 0x00 16.--21. "LVSSTEP,LDO Voltage Scaling Step (Write Protect)\nThe LVSSTEP value is LDO voltage rising step.\nNote: These bits are write protected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 4. "MVRS,Main Voltage Regulator Type Select (Write Protect)\nThis bit filed sets main voltage regulator type.\nNote: This bit is write protected" "0: Set main voltage regulator to LDO,1: Set main voltage regulator to DCDC"
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bitfld.long 0x00 0.--1. "PLSEL,Power Level Select (Write Protect)\nNote: These bits are write protected" "0: Set to Power level 0 (PL0),1: Set to Power level 1 (PL1),?..."
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group.long 0x1FC++0x03
|
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line.long 0x00 "SYS_PLSTS,Power Level Status Register"
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rbitfld.long 0x00 12. "CURMVR,Current Main Voltage Regulator Type (Read Only)\nThis bit field reflects current main voltage regulator type" "0: Current main voltage regulator in active and..,1: Current main voltage regulator in active mode.."
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rbitfld.long 0x00 8.--9. "PLSTATUS,Power Level Status (Read Only)\nThis bit field reflect the current power level" "0: Power level is PL0,1: Power level is PL1,?..."
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bitfld.long 0x00 4. "PDINVTRF,Power-down Mode Invalid Transition Flag (Write Protect)\nThis bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid" "0: No Power-dwon mode invalid transition.\nNo..,1: Power-dwon mode invalid transition.."
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rbitfld.long 0x00 3. "LCONS,Inductor for DC-dC Connect Status (Read Only) \nNote: This bit is 1 when main viltage regulator is LDO" "0: Inductor connect between Vsw and LDO_CAP pin,1: No Inductor connect between Vsw and LDO_CAP pin"
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bitfld.long 0x00 2. "MVRCERR,Main Voltage Regulator Type Change Error Bit (Write Protect)\nThis bit Is set by Hardware When Main Voltage Regulator Type Change From LDO to DCDC Error Occurred\nThis bit is set to 1 when main voltage regulator type change from LDO to DCDC.." "0: No main voltage regulator type change..,1: Main voltage regulator type change to DCDC.."
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rbitfld.long 0x00 1. "MVRCBUSY,Main Voltage Regulator Type Change Busy Bit (Read Only)\nThis bit is set by hardware when main voltage regulator type is changing" "0: Main voltage regulator type change is completed,1: Main voltage regulator type change is ongoing"
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rbitfld.long 0x00 0. "PLCBUSY,Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing" "0: Power level change is completed,1: Power level change is ongoing"
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tree.end
|
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tree "SYST_SCR"
|
|
base ad:0xE000E000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYST_CTRL,SysTick Control and Status Register"
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bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
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bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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group.long 0x14++0x03
|
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line.long 0x00 "SYST_LOAD,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0"
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group.long 0x18++0x03
|
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line.long 0x00 "SYST_VAL,SysTick Current Value Register"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
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group.long 0xD04++0x03
|
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
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bitfld.long 0x00 30. "NMIPENDCLR,NMI Bit-pending Bit\nNote: If AIRCR.BFHFNMINS is 0 this bit is RAZ/WI from Non-secure state" "0: No effect,1: Clear pending status"
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bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
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rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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|
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hexmask.long.word 0x00 12.--20. 1. "VECTPENDING,Number of the Highest Pended Exception"
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hexmask.long.word 0x00 0.--8. 1. "VECTACTIVE,Number of the Current Active Exception"
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group.long 0xD08++0x03
|
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line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state"
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group.long 0xD0C++0x03
|
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the.."
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bitfld.long 0x00 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian"
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bitfld.long 0x00 14. "PRIS,Priority Secure Exceptions Bit" "0: Priority ranges of Secure and Non-secure..,?..."
|
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bitfld.long 0x00 13. "BFHFNMINS,BusFault HardFault AndNMI Non-secure Enable Bit" "0: BusFault HardFault and NMI are Secure.1 =..,?..."
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bitfld.long 0x00 3. "SYSRESETREQS,System Reset Request Secure Only Bit" "0: SYSRESETREQ functionality is available to..,?..."
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bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1"
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bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1"
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|
group.long 0xD10++0x03
|
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x00 3. "SLEEPDEEPS,SLEEPDEEP Bit Is Only Accessible From Secure State" "0: The SLEEPDEEP bit is accessible from both..,1: The SLEEPDEEP bit behaves as RAZ/WI when.."
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bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep"
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enters sleep or deep sleep on return from an.."
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group.long 0xD14++0x03
|
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line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 18. "BP,Branch Prediction Enable Bit\nThis bit is RAZ/WI" "0,1"
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bitfld.long 0x00 17. "IC,Instruction Cache Enable Bit\nThis bit is RAZ/WI" "0,1"
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bitfld.long 0x00 16. "DC,Data Cache Enable Bit\nThis bit is RAZ/WI" "0,1"
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bitfld.long 0x00 10. "STKOFHFNMIGN,Stack Overflow in HardFault and NMI Ignore\nThis bit is RAZ/WI" "0,1"
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bitfld.long 0x00 8. "BFHFNMIGN,BusFault in HardFault or NMI Ignore\nThis bit is RAZ/WI" "0,1"
|
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bitfld.long 0x00 4. "DIV_0_TRP,Divide by Zero Trap\nThis bit is RAZ/WI" "0,1"
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newline
|
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bitfld.long 0x00 3. "UNALIGN_TRP,Unaligned Trap\nThis bit is RAO/WI" "0,1"
|
|
group.long 0xD1C++0x03
|
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3"
|
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group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3"
|
|
group.long 0xD24++0x03
|
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line.long 0x00 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x00 21. "HARDFAULTPENDED,HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state of\nthe HardFault exception corresponding to the selected Security state.\nThis bit is banked between Security states.\nThe possible.." "0: HardFault exception not pending for the..,1: HardFault exception pending for the selected.."
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|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. "ALLNS,All Non-secure" "0: All Memory region is marked as Secure and is..,1: All Memory region is marked as Non-secure by.."
|
|
bitfld.long 0x00 0. "ENABLE,SAU Enable Bit" "0: SAU Disabled,1: SAU Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SREGION,SAU Regions\nIndicates the number of regions implemented by the Security Attribution Unit"
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REGION,Current Region of SAU\nIndicates the SAU region accessed by SAU_RBAR and SAU_RLAR.\nSet a value to select the region to be configure through SAU_RBAR and SAU_RLAR.\nIt can be set to 0 ~ the value of SAU_TYPE -1"
|
|
group.long 0xDDC++0x03
|
|
line.long 0x00 "SAU_RBAR,SAU Region Base Address Register"
|
|
hexmask.long 0x00 5.--31. 1. "BADDR,Base Address of Currently Selected Region\nThe base address of the region selected by SAU_RNR.\nSAU region is 32-byte-aligned"
|
|
group.long 0xDE0++0x03
|
|
line.long 0x00 "SAU_RLAR,SAU Region Limit Address Register"
|
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hexmask.long 0x00 5.--31. 1. "LADDR,Limit Address of Currently Selected Region\nThe limited address of the region selected by SAU_RNR.\nThe region of the selected SAU region is [SAU_RBAR.BADDR 5'b00000] ~ [LADDR 5'b11111]"
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bitfld.long 0x00 1. "NSC,Non-secure Callable Setting Bit\nControls whether Non-secure state is permitted to execute an SG instruction\nfrom this region" "0: Region is not Non-secure callable,1: Region is Non-secure callable"
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newline
|
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bitfld.long 0x00 0. "RENABLE,Region Enable Bit\nEnable or disable the currently selected region set by SAU_RNR" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
tree "TIMER"
|
|
tree "TMR0"
|
|
base ad:0x40050000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIMER0_CTL,Timer0 Control Register"
|
|
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
|
|
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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|
bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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|
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
|
|
bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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|
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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|
bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER0_ALTCTL,Timer0 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER0_PWMCTL,Timer0 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER0_PWMCLKSRC,Timer0 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER0_PWMPERIOD,Timer0 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER0_PWMDTCTL,Timer0 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER0_PWMCNT,Timer0 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER0_PWMMSKEN,Timer0 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER0_PWMMSK,Timer0 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER0_PWMBNF,Timer0 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER0_PWMFAILBRK,Timer0 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER0_PWMBRKCTL,Timer0 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER0_PWMPOEN,Timer0 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER0_PWMSWBRK,Timer0 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER0_PWMINTEN1,Timer0 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER0_PWMINTSTS1,Timer0 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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newline
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER0_PWMADCTS,Timer0 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER0_PWMSCTL,Timer0 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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wgroup.long 0x98++0x03
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line.long 0x00 "TIMER0_PWMSTRG,Timer0 PWM Synchronous Trigger Register"
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bitfld.long 0x00 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER0_PWMSTATUS,Timer0 PWM Status Register"
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR1"
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base ad:0x40050100
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group.long 0x00++0x03
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line.long 0x00 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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newline
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER1_ALTCTL,Timer1 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER1_PWMCTL,Timer1 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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newline
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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newline
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER1_PWMCLKSRC,Timer1 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER1_PWMPERIOD,Timer1 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER1_PWMDTCTL,Timer1 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER1_PWMCNT,Timer1 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER1_PWMMSKEN,Timer1 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER1_PWMMSK,Timer1 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER1_PWMBNF,Timer1 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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newline
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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newline
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER1_PWMFAILBRK,Timer1 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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newline
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER1_PWMBRKCTL,Timer1 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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newline
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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newline
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER1_PWMPOEN,Timer1 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER1_PWMSWBRK,Timer1 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER1_PWMINTEN1,Timer1 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER1_PWMINTSTS1,Timer1 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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newline
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER1_PWMADCTS,Timer1 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER1_PWMSCTL,Timer1 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER1_PWMSTATUS,Timer1 PWM Status Register"
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR2"
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base ad:0x40051000
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group.long 0x00++0x03
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line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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newline
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER2_ALTCTL,Timer2 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER2_PWMCTL,Timer2 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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newline
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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newline
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER2_PWMCLKSRC,Timer2 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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|
line.long 0x00 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER2_PWMDTCTL,Timer2 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER2_PWMMSKEN,Timer2 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER2_PWMMSK,Timer2 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER2_PWMBNF,Timer2 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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newline
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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newline
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER2_PWMFAILBRK,Timer2 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER2_PWMBRKCTL,Timer2 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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newline
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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newline
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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newline
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER2_PWMPOEN,Timer2 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER2_PWMSWBRK,Timer2 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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newline
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER2_PWMINTEN1,Timer2 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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newline
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER2_PWMINTSTS1,Timer2 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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newline
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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newline
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER2_PWMADCTS,Timer2 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER2_PWMSCTL,Timer2 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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wgroup.long 0x98++0x03
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line.long 0x00 "TIMER2_PWMSTRG,Timer2 PWM Synchronous Trigger Register"
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bitfld.long 0x00 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR2_NS"
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base ad:0x50051000
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group.long 0x00++0x03
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line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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|
group.long 0x04++0x03
|
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line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
|
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
|
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER2_ALTCTL,Timer2 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER2_PWMCTL,Timer2 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER2_PWMCLKSRC,Timer2 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER2_PWMDTCTL,Timer2 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER2_PWMMSKEN,Timer2 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER2_PWMMSK,Timer2 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER2_PWMBNF,Timer2 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER2_PWMFAILBRK,Timer2 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER2_PWMBRKCTL,Timer2 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER2_PWMPOEN,Timer2 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER2_PWMSWBRK,Timer2 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER2_PWMINTEN1,Timer2 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER2_PWMINTSTS1,Timer2 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER2_PWMADCTS,Timer2 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER2_PWMSCTL,Timer2 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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wgroup.long 0x98++0x03
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line.long 0x00 "TIMER2_PWMSTRG,Timer2 PWM Synchronous Trigger Register"
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bitfld.long 0x00 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR3"
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base ad:0x40051100
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group.long 0x00++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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newline
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER3_ALTCTL,Timer3 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER3_PWMCTL,Timer3 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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newline
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER3_PWMCLKSRC,Timer3 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER3_PWMDTCTL,Timer3 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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newline
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER3_PWMMSKEN,Timer3 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER3_PWMMSK,Timer3 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER3_PWMBNF,Timer3 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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newline
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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newline
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER3_PWMFAILBRK,Timer3 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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newline
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER3_PWMBRKCTL,Timer3 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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newline
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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newline
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER3_PWMPOEN,Timer3 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER3_PWMSWBRK,Timer3 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER3_PWMINTEN1,Timer3 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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newline
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER3_PWMINTSTS1,Timer3 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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newline
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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newline
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER3_PWMADCTS,Timer3 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER3_PWMSCTL,Timer3 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
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bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR3_NS"
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base ad:0x50051100
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group.long 0x00++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not" "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.."
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newline
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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newline
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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newline
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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newline
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation.\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Event Counter input source is from USB.."
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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newline
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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newline
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
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newline
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the TMx_EXT capture pin input function" "0: TMx_EXT (x= 0~3) pin Disabled,1: TMx_EXT (x= 0~3) pin Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 3. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can be triggered DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled"
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newline
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bitfld.long 0x00 2. "TRGEADC,Trigger EADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered EADC conversion" "0: Timer interrupt trigger EADC Disabled,1: Timer interrupt trigger EADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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newline
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER3_ALTCTL,Timer3 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: timer controller is used as timer function,1: timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER3_PWMCTL,Timer3 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt disable,1: ICE debug mode counter halt enable"
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newline
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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newline
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER3_PWMCLKSRC,Timer3 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
|
|
line.long 0x00 "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
|
|
bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TIMER3_PWMDTCTL,Timer3 PWM Dead-time Control Register"
|
|
bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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|
bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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|
newline
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This bit is write protected"
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|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
|
|
bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down count,1: Counter is active up count"
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|
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TIMER3_PWMMSKEN,Timer3 PWM Output Mask Enable Register"
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|
bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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|
bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TIMER3_PWMMSK,Timer3 PWM Output Mask Data Control Register"
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|
bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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|
bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "TIMER3_PWMBNF,Timer3 PWM Brake Pin Noise Filter Register"
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|
bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from PWM0_BRAKE0 pin,1: Brake pin source comes from PWM0_BRAKE1 pin,2: Brake pin source comes from PWM1_BRAKE0 pin,3: Brake pin source comes from PWM1_BRAKE1 pin"
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|
bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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|
newline
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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|
newline
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of PWMx_BRAKEy Disabled,1: Pin noise filter detect of PWMx_BRAKEy Enabled"
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|
group.long 0x6C++0x03
|
|
line.long 0x00 "TIMER3_PWMFAILBRK,Timer3 PWM System Fail Brake Control Register"
|
|
bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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|
bitfld.long 0x00 2. "RAMBRKEN,SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by SRAM parity error..,1: Brake Function triggered by SRAM parity error.."
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newline
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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|
group.long 0x70++0x03
|
|
line.long 0x00 "TIMER3_PWMBRKCTL,Timer3 PWM Brake Control Register"
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|
bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH1 output tri-state when PWMx_BRAKEy..,2: PWMx_CH1 output low level when PWMx_BRAKEy..,3: PWMx_CH1 output high level when PWMx_BRAKEy.."
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|
bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy brake event will not affect..,1: PWMx_CH0 output tri-state when PWMx_BRAKEy..,2: PWMx_CH0 output low level when PWMx_BRAKEy..,3: PWMx_CH0 output high level when PWMx_BRAKEy.."
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newline
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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|
bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as level-detect brake..,1: PWMx_BRAKEy pin event as level-detect brake.."
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|
newline
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|
bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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newline
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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|
bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKEy pin event as edge-detect brake..,1: PWMx_BRAKEy pin event as edge-detect brake.."
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newline
|
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This bit is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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|
group.long 0x74++0x03
|
|
line.long 0x00 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
|
|
bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
|
|
line.long 0x00 "TIMER3_PWMPOEN,Timer3 PWM Pin Output Enable Register"
|
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
|
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line.long 0x00 "TIMER3_PWMSWBRK,Timer3 PWM Software Trigger Brake Control Register"
|
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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|
group.long 0x80++0x03
|
|
line.long 0x00 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
|
|
bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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|
bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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newline
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
|
|
line.long 0x00 "TIMER3_PWMINTEN1,Timer3 PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
|
|
line.long 0x00 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
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|
bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type.\nNote2: This bit is.." "0,1"
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|
newline
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: In up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches 0.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
|
|
line.long 0x00 "TIMER3_PWMINTSTS1,Timer3 PWM Interrupt Status Register 1"
|
|
rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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|
rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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newline
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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|
rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
|
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 level-detect brake event do not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 level-detect brake event do not..,1: PWMx_CH0 level-detect brake event happened"
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|
newline
|
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH1 edge-detect brake event do not..,1: PWMx_CH1 edge-detect brake event happened"
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|
bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This bit is write protected" "0: PWMx_CH0 edge-detect brake event do not..,1: PWMx_CH0 edge-detect brake event happened"
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|
group.long 0x90++0x03
|
|
line.long 0x00 "TIMER3_PWMADCTS,Timer3 PWM ADC Trigger Source Select Register"
|
|
bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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|
bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger EADC Conversion" "0: Trigger EADC conversion at zero point (ZIF),1: Trigger EADC conversion at period point (PIF),2: Trigger EADC conversion at zero or period..,3: Trigger EADC conversion at compare up count..,4: Trigger EADC conversion at compare down count..,?..."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "TIMER3_PWMSCTL,Timer3 PWM Synchronous Control Register"
|
|
bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIMER0_PWMSCTL[8] TIMER1_PWMSCTL[8] TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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|
bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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|
group.long 0x9C++0x03
|
|
line.long 0x00 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
|
|
bitfld.long 0x00 16. "EADCTRGF,Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger EADC start..,1: PWM counter event trigger EADC start.."
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|
bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: The PWM counter value never reached its..,1: The PWM counter value has reached its maximum.."
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|
rgroup.long 0xA0++0x03
|
|
line.long 0x00 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
|
|
rgroup.long 0xA4++0x03
|
|
line.long 0x00 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
|
|
tree.end
|
|
tree.end
|
|
tree "TRNG"
|
|
tree "TRNG"
|
|
base ad:0x400B9000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TRNG_CTL,TRNG Control Register and Status"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "Reversed,Reversed"
|
|
rbitfld.long 0x00 7. "READY,Random Number Generator Ready (Read Only)\nAfter ACT (TRNG_ACT[7]) bit is set the READY bit become to 1 after a delay of 90us~120us" "0: RNG is not ready or was not activated,1: RNG is ready to be enabled"
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|
newline
|
|
bitfld.long 0x00 6. "DVIEN,Data Valid Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 2.--5. "CLKPSC,Clock Prescaler\nThe CLKPSC is the peripheral clock frequency range for the selected value the CLKPSC setting must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation)" "0: 80 ~ 100 MHz,1: 60 ~ 80 MHz,2: 50 ~60 MHz,3: 40 ~50 MHz,4: 30 ~40 MHz,5: 25 ~30 MHz,6: 20 ~25 MHz,7: 15 ~20 MHz,8: 12 ~15 MHz,9: 9 ~12 MHz,10: 7 ~9 MHz,11: 6 ~7 MHz,12: 5 ~6 MHz,13: 4 ~5 MHz,?,15: Reserved"
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|
newline
|
|
rbitfld.long 0x00 1. "DVIF,Data Valid (Read Only)\nThis bit is cleared to '0' by read TRNG_DATA" "0: Data is not valid,1: Data is valid"
|
|
bitfld.long 0x00 0. "TRNGEN,Random Number Generator Enable Bit\nThis bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.\nNote: TRNGEN is an enable bit of digital part" "0: TRNG Disabled,1: TRNG Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TRNG_DATA,TRNG Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Random Number Generator Data (Read Only)\nThe DATA store the random number generated by TRNG and can be read only once"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRNG_ACT,TRNG Activation Register"
|
|
bitfld.long 0x00 7. "ACT,Random Number Generator Activation\nAfter enable the ACT bit it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\nNote: ACT is an enable bit of analog part" "0: TRNG inactive,1: TRNG active"
|
|
tree.end
|
|
tree "TRNG_NS"
|
|
base ad:0x500B9000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TRNG_CTL,TRNG Control Register and Status"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "Reversed,Reversed"
|
|
rbitfld.long 0x00 7. "READY,Random Number Generator Ready (Read Only)\nAfter ACT (TRNG_ACT[7]) bit is set the READY bit become to 1 after a delay of 90us~120us" "0: RNG is not ready or was not activated,1: RNG is ready to be enabled"
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|
newline
|
|
bitfld.long 0x00 6. "DVIEN,Data Valid Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 2.--5. "CLKPSC,Clock Prescaler\nThe CLKPSC is the peripheral clock frequency range for the selected value the CLKPSC setting must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation)" "0: 80 ~ 100 MHz,1: 60 ~ 80 MHz,2: 50 ~60 MHz,3: 40 ~50 MHz,4: 30 ~40 MHz,5: 25 ~30 MHz,6: 20 ~25 MHz,7: 15 ~20 MHz,8: 12 ~15 MHz,9: 9 ~12 MHz,10: 7 ~9 MHz,11: 6 ~7 MHz,12: 5 ~6 MHz,13: 4 ~5 MHz,?,15: Reserved"
|
|
newline
|
|
rbitfld.long 0x00 1. "DVIF,Data Valid (Read Only)\nThis bit is cleared to '0' by read TRNG_DATA" "0: Data is not valid,1: Data is valid"
|
|
bitfld.long 0x00 0. "TRNGEN,Random Number Generator Enable Bit\nThis bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.\nNote: TRNGEN is an enable bit of digital part" "0: TRNG Disabled,1: TRNG Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "TRNG_DATA,TRNG Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Random Number Generator Data (Read Only)\nThe DATA store the random number generated by TRNG and can be read only once"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRNG_ACT,TRNG Activation Register"
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bitfld.long 0x00 7. "ACT,Random Number Generator Activation\nAfter enable the ACT bit it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\nNote: ACT is an enable bit of analog part" "0: TRNG inactive,1: TRNG active"
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tree.end
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tree.end
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tree "UART"
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tree "UART0"
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base ad:0x40070000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.18.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART0_NS"
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base ad:0x50070000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.18.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART1"
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base ad:0x40071000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.18.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART1_NS"
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base ad:0x50071000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.18.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART2"
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base ad:0x40072000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART2_NS"
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base ad:0x50072000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART3"
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base ad:0x40073000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART3_NS"
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base ad:0x50073000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART4"
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base ad:0x40074000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART4_NS"
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base ad:0x50074000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART5"
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base ad:0x40075000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART5_NS"
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base ad:0x50075000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1813 and Figure 6.1814 for UART function mode.\nNote2: Refer to Figure 6.1824 and Figure 6.1825 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled"
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold\nwake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is woken up from Power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree.end
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tree "USBD"
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tree "USBD"
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base ad:0x400C0000
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group.long 0x00++0x03
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line.long 0x00 "USBD_INTEN,USB Device Interrupt Enable Register"
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bitfld.long 0x00 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS0.."
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bitfld.long 0x00 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x00 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
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bitfld.long 0x00 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x00 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
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bitfld.long 0x00 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x00 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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|
group.long 0x04++0x03
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line.long 0x00 "USBD_INTSTS,USB Device Interrupt Event Status Register"
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bitfld.long 0x00 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by write 1 to.."
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bitfld.long 0x00 27. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11 check.."
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bitfld.long 0x00 26. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10 check.."
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bitfld.long 0x00 25. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9 check.."
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bitfld.long 0x00 24. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8 check.."
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bitfld.long 0x00 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
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bitfld.long 0x00 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
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bitfld.long 0x00 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x00 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
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bitfld.long 0x00 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x00 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
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bitfld.long 0x00 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x00 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
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bitfld.long 0x00 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.."
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bitfld.long 0x00 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event does not occur,1: No-event-wake-up event occurred cleared by.."
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bitfld.long 0x00 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB.."
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bitfld.long 0x00 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus" "0: No USB event occurred,1: USB event occurred check EPSTS0~11[3:0] to.."
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bitfld.long 0x00 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus" "0: No BUS event occurred,1: Bus event occurred check USBD_ATTR[3:0] to.."
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group.long 0x08++0x03
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line.long 0x00 "USBD_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Device Function Address"
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rgroup.long 0x0C++0x03
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line.long 0x00 "USBD_EPSTS,USB Device Endpoint Status Register"
|
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bitfld.long 0x00 7. "OV,Overrun\nIt indicates that the received data is over the maximum payload number or not" "0: No overrun,1: Out Data is more than the Max Payload in.."
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group.long 0x10++0x03
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line.long 0x00 "USBD_ATTR,USB Device Bus Status and Attribution Register"
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bitfld.long 0x00 13. "L1RESUME,LPM L1 Resume\nNote: This bit is read only" "0: Bus no LPM L1 state resume,1: LPM L1 state Resume from LPM L1 state suspend"
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bitfld.long 0x00 12. "L1SUSPEND,LPM L1 Suspend\nNote: This bit is read only" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM.."
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bitfld.long 0x00 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: the valid LPM Token will be NYET,1: the valid LPM Token will be ACK"
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bitfld.long 0x00 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode,1: Byte mode"
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bitfld.long 0x00 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x00 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x00 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).."
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bitfld.long 0x00 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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bitfld.long 0x00 3. "TOUT,Time-out Status\nNote: This bit is read only" "0: No time-out,1: No Bus response more than 18 bits time"
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bitfld.long 0x00 2. "RESUME,Resume Status\nNote: This bit is read only" "0: No bus resume,1: Resume from suspend"
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bitfld.long 0x00 1. "SUSPEND,Suspend Status\nNote: This bit is read only" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
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bitfld.long 0x00 0. "USBRST,USB Reset Status\nNote: This bit is read only" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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rgroup.long 0x14++0x03
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line.long 0x00 "USBD_VBUSDET,USB Device VBUS Detection Register"
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|
bitfld.long 0x00 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
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group.long 0x18++0x03
|
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line.long 0x00 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
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bitfld.long 0x00 3.--8. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG 3'b000} \nNote: It is used for SETUP token.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rgroup.long 0x20++0x03
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line.long 0x00 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
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bitfld.long 0x00 28.--31. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 24.--27. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 20.--23. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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rgroup.long 0x24++0x03
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line.long 0x00 "USBD_EPSTS1,USB Device Endpoint Status Register 1"
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bitfld.long 0x00 12.--15. "EPSTS11,Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 8.--11. "EPSTS10,Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 4.--7. "EPSTS9,Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 0.--3. "EPSTS8,Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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rgroup.long 0x88++0x03
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line.long 0x00 "USBD_LPMATTR,USB LPM Attribution Register"
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bitfld.long 0x00 8. "LPMRWAKUP,LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
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bitfld.long 0x00 4.--7. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token" "0: 125us,1: 150us,2: 200us,3: 300us,4: 400us,5: 500us,6: 1000us,7: 2000us,8: 3000us,9: 4000us,10: 5000us,11: 6000us,12: 7000us,13: 8000us,14: 9000us,15: 10000us"
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bitfld.long 0x00 0.--3. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token" "0: Reserve,1: L1 (Sleep),?..."
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rgroup.long 0x8C++0x03
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line.long 0x00 "USBD_FN,USB Frame Number Register"
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hexmask.long.word 0x00 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet"
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group.long 0x90++0x03
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line.long 0x00 "USBD_SE0,USB Device Drive SE0 Control Register"
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bitfld.long 0x00 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low" "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
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group.long 0x500++0x03
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line.long 0x00 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
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bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x504++0x03
|
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line.long 0x00 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
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group.long 0x508++0x03
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line.long 0x00 "USBD_CFG0,Endpoint 0 Configuration Register"
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bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
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bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
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bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x50C++0x03
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line.long 0x00 "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
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group.long 0x510++0x03
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line.long 0x00 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
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bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x514++0x03
|
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line.long 0x00 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
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group.long 0x518++0x03
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line.long 0x00 "USBD_CFG1,Endpoint 1 Configuration Register"
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bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
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bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
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bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x51C++0x03
|
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line.long 0x00 "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
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group.long 0x520++0x03
|
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line.long 0x00 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
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bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x524++0x03
|
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line.long 0x00 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
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group.long 0x528++0x03
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line.long 0x00 "USBD_CFG2,Endpoint 2 Configuration Register"
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bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
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bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
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bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x52C++0x03
|
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line.long 0x00 "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
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group.long 0x530++0x03
|
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line.long 0x00 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "USBD_CFG3,Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x53C++0x03
|
|
line.long 0x00 "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "USBD_CFG4,Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "USBD_CFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "USBD_CFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "USBD_CFG7,Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "USBD_BUFSEG8,Endpoint 8 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "USBD_MXPLD8,Endpoint 8 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "USBD_CFG8,Endpoint 8 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "USBD_CFGP8,Endpoint 8 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "USBD_BUFSEG9,Endpoint 9 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "USBD_MXPLD9,Endpoint 9 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "USBD_CFG9,Endpoint 9 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "USBD_CFGP9,Endpoint 9 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "USBD_BUFSEG10,Endpoint 10 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "USBD_MXPLD10,Endpoint 10 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "USBD_CFG10,Endpoint 10 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "USBD_CFGP10,Endpoint 10 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "USBD_BUFSEG11,Endpoint 11 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "USBD_MXPLD11,Endpoint 11 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "USBD_CFG11,Endpoint 11 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "USBD_CFGP11,Endpoint 11 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
tree.end
|
|
tree "USBD_NS"
|
|
base ad:0x500C0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USBD_INTEN,USB Device Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS0.."
|
|
bitfld.long 0x00 8. "WKEN,Wake-up Function Enable Bit" "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
|
|
bitfld.long 0x00 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
|
|
bitfld.long 0x00 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USBD_INTSTS,USB Device Interrupt Event Status Register"
|
|
bitfld.long 0x00 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred cleared by write 1 to.."
|
|
bitfld.long 0x00 27. "EPEVT11,Endpoint 11's USB Event Status" "0: No event occurred in endpoint 11,1: USB event occurred on Endpoint 11 check.."
|
|
newline
|
|
bitfld.long 0x00 26. "EPEVT10,Endpoint 10's USB Event Status" "0: No event occurred in endpoint 10,1: USB event occurred on Endpoint 10 check.."
|
|
bitfld.long 0x00 25. "EPEVT9,Endpoint 9's USB Event Status" "0: No event occurred in endpoint 9,1: USB event occurred on Endpoint 9 check.."
|
|
newline
|
|
bitfld.long 0x00 24. "EPEVT8,Endpoint 8's USB Event Status" "0: No event occurred in endpoint 8,1: USB event occurred on Endpoint 8 check.."
|
|
bitfld.long 0x00 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
|
|
newline
|
|
bitfld.long 0x00 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
|
|
bitfld.long 0x00 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
|
|
newline
|
|
bitfld.long 0x00 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
|
|
bitfld.long 0x00 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
|
|
newline
|
|
bitfld.long 0x00 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
|
|
bitfld.long 0x00 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
|
|
newline
|
|
bitfld.long 0x00 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
|
|
bitfld.long 0x00 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event does not occur,1: SOF event occurred cleared by write 1 to.."
|
|
newline
|
|
bitfld.long 0x00 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event does not occur,1: No-event-wake-up event occurred cleared by.."
|
|
bitfld.long 0x00 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is not attached/detached event in the USB,1: There is attached/detached event in the USB.."
|
|
newline
|
|
bitfld.long 0x00 1. "USBIF,USB Event Interrupt Status\nThe USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus" "0: No USB event occurred,1: USB event occurred check EPSTS0~11[3:0] to.."
|
|
bitfld.long 0x00 0. "BUSIF,BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus" "0: No BUS event occurred,1: Bus event occurred check USBD_ATTR[3:0] to.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USBD_FADDR,USB Device Function Address Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Device Function Address"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USBD_EPSTS,USB Device Endpoint Status Register"
|
|
bitfld.long 0x00 7. "OV,Overrun\nIt indicates that the received data is over the maximum payload number or not" "0: No overrun,1: Out Data is more than the Max Payload in.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USBD_ATTR,USB Device Bus Status and Attribution Register"
|
|
bitfld.long 0x00 13. "L1RESUME,LPM L1 Resume\nNote: This bit is read only" "0: Bus no LPM L1 state resume,1: LPM L1 state Resume from LPM L1 state suspend"
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|
bitfld.long 0x00 12. "L1SUSPEND,LPM L1 Suspend\nNote: This bit is read only" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM.."
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|
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bitfld.long 0x00 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: the valid LPM Token will be NYET,1: the valid LPM Token will be ACK"
|
|
bitfld.long 0x00 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode,1: Byte mode"
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|
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bitfld.long 0x00 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
|
|
bitfld.long 0x00 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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|
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bitfld.long 0x00 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).."
|
|
bitfld.long 0x00 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
|
|
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bitfld.long 0x00 3. "TOUT,Time-out Status\nNote: This bit is read only" "0: No time-out,1: No Bus response more than 18 bits time"
|
|
bitfld.long 0x00 2. "RESUME,Resume Status\nNote: This bit is read only" "0: No bus resume,1: Resume from suspend"
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|
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bitfld.long 0x00 1. "SUSPEND,Suspend Status\nNote: This bit is read only" "0: Bus no suspend,1: Bus idle more than 3ms either cable is.."
|
|
bitfld.long 0x00 0. "USBRST,USB Reset Status\nNote: This bit is read only" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "USBD_VBUSDET,USB Device VBUS Detection Register"
|
|
bitfld.long 0x00 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "STBUFSEG,SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG 3'b000} \nNote: It is used for SETUP token.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "USBD_EPSTS0,USB Device Endpoint Status Register 0"
|
|
bitfld.long 0x00 28.--31. "EPSTS7,Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
bitfld.long 0x00 24.--27. "EPSTS6,Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
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bitfld.long 0x00 20.--23. "EPSTS5,Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "USBD_EPSTS1,USB Device Endpoint Status Register 1"
|
|
bitfld.long 0x00 12.--15. "EPSTS11,Endpoint 11 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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bitfld.long 0x00 8.--11. "EPSTS10,Endpoint 10 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
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bitfld.long 0x00 4.--7. "EPSTS9,Endpoint 9 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
bitfld.long 0x00 0.--3. "EPSTS8,Endpoint 8 Status\nThese bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,2: Out Packet Data0 ACK,3: Setup ACK,?,?,6: Out Packet Data1 ACK,7: Isochronous transfer end,?..."
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|
rgroup.long 0x88++0x03
|
|
line.long 0x00 "USBD_LPMATTR,USB LPM Attribution Register"
|
|
bitfld.long 0x00 8. "LPMRWAKUP,LPM Remote Wakeup\nThis bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
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|
bitfld.long 0x00 4.--7. "LPMBESL,LPM Best Effort Service Latency\nThese bits contain the BESL value received with last ACK LPM Token" "0: 125us,1: 150us,2: 200us,3: 300us,4: 400us,5: 500us,6: 1000us,7: 2000us,8: 3000us,9: 4000us,10: 5000us,11: 6000us,12: 7000us,13: 8000us,14: 9000us,15: 10000us"
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|
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bitfld.long 0x00 0.--3. "LPMLINKSTS,LPM Link State\nThese bits contain the bLinkState received with last ACK LPM Token" "0: Reserve,1: L1 (Sleep),?..."
|
|
rgroup.long 0x8C++0x03
|
|
line.long 0x00 "USBD_FN,USB Frame Number Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "FN,Frame Number\nThese bits contain the 11-bits frame number in the last received SOF packet"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "USBD_SE0,USB Device Drive SE0 Control Register"
|
|
bitfld.long 0x00 0. "SE0,Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low" "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x504++0x03
|
|
line.long 0x00 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
|
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x508++0x03
|
|
line.long 0x00 "USBD_CFG0,Endpoint 0 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x50C++0x03
|
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line.long 0x00 "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
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|
group.long 0x510++0x03
|
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line.long 0x00 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x514++0x03
|
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line.long 0x00 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
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group.long 0x518++0x03
|
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line.long 0x00 "USBD_CFG1,Endpoint 1 Configuration Register"
|
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bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
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bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
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bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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|
newline
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x51C++0x03
|
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line.long 0x00 "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
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bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
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|
group.long 0x520++0x03
|
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line.long 0x00 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
|
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bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x524++0x03
|
|
line.long 0x00 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
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group.long 0x528++0x03
|
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line.long 0x00 "USBD_CFG2,Endpoint 2 Configuration Register"
|
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bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
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bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
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bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x52C++0x03
|
|
line.long 0x00 "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x530++0x03
|
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line.long 0x00 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x534++0x03
|
|
line.long 0x00 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x538++0x03
|
|
line.long 0x00 "USBD_CFG3,Endpoint 3 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x53C++0x03
|
|
line.long 0x00 "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x540++0x03
|
|
line.long 0x00 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x544++0x03
|
|
line.long 0x00 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x548++0x03
|
|
line.long 0x00 "USBD_CFG4,Endpoint 4 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
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|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54C++0x03
|
|
line.long 0x00 "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x550++0x03
|
|
line.long 0x00 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x554++0x03
|
|
line.long 0x00 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x558++0x03
|
|
line.long 0x00 "USBD_CFG5,Endpoint 5 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
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|
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bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x55C++0x03
|
|
line.long 0x00 "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x560++0x03
|
|
line.long 0x00 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x564++0x03
|
|
line.long 0x00 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x568++0x03
|
|
line.long 0x00 "USBD_CFG6,Endpoint 6 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
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|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x56C++0x03
|
|
line.long 0x00 "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x570++0x03
|
|
line.long 0x00 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x574++0x03
|
|
line.long 0x00 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x578++0x03
|
|
line.long 0x00 "USBD_CFG7,Endpoint 7 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x57C++0x03
|
|
line.long 0x00 "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x580++0x03
|
|
line.long 0x00 "USBD_BUFSEG8,Endpoint 8 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x584++0x03
|
|
line.long 0x00 "USBD_MXPLD8,Endpoint 8 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x588++0x03
|
|
line.long 0x00 "USBD_CFG8,Endpoint 8 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
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bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58C++0x03
|
|
line.long 0x00 "USBD_CFGP8,Endpoint 8 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x590++0x03
|
|
line.long 0x00 "USBD_BUFSEG9,Endpoint 9 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x594++0x03
|
|
line.long 0x00 "USBD_MXPLD9,Endpoint 9 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x598++0x03
|
|
line.long 0x00 "USBD_CFG9,Endpoint 9 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x59C++0x03
|
|
line.long 0x00 "USBD_CFGP9,Endpoint 9 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5A0++0x03
|
|
line.long 0x00 "USBD_BUFSEG10,Endpoint 10 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5A4++0x03
|
|
line.long 0x00 "USBD_MXPLD10,Endpoint 10 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5A8++0x03
|
|
line.long 0x00 "USBD_CFG10,Endpoint 10 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5AC++0x03
|
|
line.long 0x00 "USBD_CFGP10,Endpoint 10 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
group.long 0x5B0++0x03
|
|
line.long 0x00 "USBD_BUFSEG11,Endpoint 11 Buffer Segmentation Register"
|
|
bitfld.long 0x00 3.--8. "BUFSEG,Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5B4++0x03
|
|
line.long 0x00 "USBD_MXPLD11,Endpoint 11 Maximal Payload Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "MXPLD,Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token)"
|
|
group.long 0x5B8++0x03
|
|
line.long 0x00 "USBD_CFG11,Endpoint 11 Configuration Register"
|
|
bitfld.long 0x00 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL..,1: Clear the device to response STALL handshake.."
|
|
bitfld.long 0x00 7. "DSQSYNC,Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction" "0: DATA0 PID,1: DATA1 PID"
|
|
newline
|
|
bitfld.long 0x00 5.--6. "STATE,Endpoint STATE" "0: Endpoint is Disabled,1: Out endpoint,2: IN endpoint,3: Undefined"
|
|
bitfld.long 0x00 4. "ISOCH,Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint no handshake" "0: No Isochronous endpoint,1: Isochronous endpoint"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "EPNUM,Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5BC++0x03
|
|
line.long 0x00 "USBD_CFGP11,Endpoint 11 Set Stall and Clear In/Out Ready Control Register"
|
|
bitfld.long 0x00 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
|
|
bitfld.long 0x00 0. "CLRRDY,Clear Ready\nWhen the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "USBH"
|
|
tree "USBH"
|
|
base ad:0x40009000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "HcRevision,Host Controller Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HcControl,Host Controller Control Register"
|
|
bitfld.long 0x00 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state" "0: USBSUSPEND,1: USBOPERATIONAL,2: USBRESUME,3: USBRESET"
|
|
bitfld.long 0x00 5. "BLE,Bulk List Enable Bit" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
|
|
newline
|
|
bitfld.long 0x00 4. "CLE,Control List Enable Bit" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next.."
|
|
bitfld.long 0x00 3. "IE,Isochronous List Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list" "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the.."
|
|
newline
|
|
bitfld.long 0x00 2. "PLE,Periodic List Enable Bit\nWhen set this bit enables processing of the Periodic (interrupt and isochronous) list" "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
|
|
bitfld.long 0x00 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs" "0: Number of Control EDs over Bulk EDs served is..,1: Number of Control EDs over Bulk EDs served is..,2: Number of Control EDs over Bulk EDs served is..,3: Number of Control EDs over Bulk EDs served is.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HcCommandStatus,Host Controller Command Status Register"
|
|
bitfld.long 0x00 16.--17. "SOC,Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error" "0,1,2,3"
|
|
bitfld.long 0x00 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Bulk list"
|
|
newline
|
|
bitfld.long 0x00 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Control list"
|
|
bitfld.long 0x00 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller" "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HcInterruptStatus,Host Controller Interrupt Status Register"
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed" "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1" "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to.."
|
|
newline
|
|
bitfld.long 0x00 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port" "0: No resume signaling detected on a downstream..,1: Resume signaling detected on a downstream port"
|
|
bitfld.long 0x00 2. "SF,Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event" "0: Not the start of a frame,1: Indicate the start of a frame and Host.."
|
|
newline
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead" "0: Host Controller didn't update HccaDoneHead,1: Host Controller has written HcDoneHead to.."
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred" "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HcInterruptEnable,Host Controller Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start of Frame Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
|
|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HcInterruptDisable,Host Controller Interrupt Disable Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start of Frame Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
|
|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "HcHCCA,Host Controller Communication Area Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HcPeriodCurrentED,Host Controller Period Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "HcControlHeadED,Host Controller Control Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CHED,Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HcControlCurrentED,Host Controller Control Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HcBulkHeadED,Host Controller Bulk Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HcBulkCurrentED,Host Controller Bulk Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HcDoneHead,Host Controller Done Head Register"
|
|
hexmask.long 0x00 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HcFmInterval,Host Controller Frame Interval Register"
|
|
bitfld.long 0x00 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0])" "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into.."
|
|
hexmask.long.word 0x00 16.--30. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1)"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "HcFmRemaining,Host Controller Frame Remaining Register"
|
|
bitfld.long 0x00 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "HcFmNumber,Host Controller Frame Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HcPeriodicStart,Host Controller Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "HcLSThreshold,Host Controller Low-speed Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "LST,Low-speed Threshold"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "HcRhDescriptorA,Host Controller Root Hub Descriptor A Register"
|
|
bitfld.long 0x00 12. "NOCP,No over Current Protection\nThis bit describes how the over current status for the Root Hub ports reported" "0: Over current status is reported,1: Over current status is not reported"
|
|
bitfld.long 0x00 11. "OCPM,over Current Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported" "0: Global Over current,1: Individual Over current"
|
|
newline
|
|
bitfld.long 0x00 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled" "0: Global Switching,1: Individual Switching"
|
|
hexmask.long.byte 0x00 0.--7. 1. "NDP,Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "HcRhDescriptorB,Host Controller Root Hub Descriptor B Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "HcRhStatus,Host Controller Root Hub Status Register"
|
|
bitfld.long 0x00 31. "CRWE,Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
|
|
bitfld.long 0x00 17. "OCIC,over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero" "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) change"
|
|
newline
|
|
bitfld.long 0x00 16. "LPSC,Set Global Power" "0: No effect,1: Set global power"
|
|
bitfld.long 0x00 15. "DRWE,Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation" "0: No effect.\nConnect Status Change as a remote..,1: Connect Status Change as a remote wake-up.."
|
|
newline
|
|
bitfld.long 0x00 1. "OCI,over Current Indicator\nThis bit reflects the state of the over current status pin" "0: No over current condition,1: Over current condition"
|
|
bitfld.long 0x00 0. "LPS,Clear Global Power" "0: No effect,1: Clear global power"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "HcRhPortStatus1,Host Controller Root Hub Port Status [1]"
|
|
bitfld.long 0x00 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero" "0: Port reset is not complete,1: Port reset is complete"
|
|
bitfld.long 0x00 19. "OCIC,Port over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero" "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changes"
|
|
newline
|
|
bitfld.long 0x00 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero" "0: Port resume is not completed,1: Port resume completed"
|
|
bitfld.long 0x00 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero" "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
|
|
newline
|
|
bitfld.long 0x00 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero" "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect.."
|
|
bitfld.long 0x00 9. "LSDA,Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed.."
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newline
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bitfld.long 0x00 8. "PPS,Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation" "0: No effect.\nPort power is Disabled,1: Port Power Enabled.\nPort power is Enabled"
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|
bitfld.long 0x00 4. "PRS,Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
|
|
newline
|
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bitfld.long 0x00 3. "POCI,Port over Current Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port" "0: No effect.\nNo over current condition,1: Clear port suspend.\nOver current condition"
|
|
bitfld.long 0x00 2. "PSS,Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively.."
|
|
newline
|
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bitfld.long 0x00 1. "PES,Port Enable Status\nWrite Operation" "0: No effect.\nPort Disabled,1: Set port enable.\nPort Enabled"
|
|
bitfld.long 0x00 0. "CCS,CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\nWrite Operation" "0: No effect.\nNo device connected,1: Clear port enable.\nDevice connected"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "HcPhyControl,Host Controller PHY Control Register"
|
|
bitfld.long 0x00 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption" "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "HcMiscControl,Host Controller Miscellaneous Control Register"
|
|
bitfld.long 0x00 16. "DPRT1,Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
|
|
bitfld.long 0x00 4. "PPCAL,Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC" "0: Port power control is high active,1: Port power control is low active"
|
|
newline
|
|
bitfld.long 0x00 3. "OCAL,Over Current Active Low\nThis bit controls the polarity of over current flag from external power IC" "0: Over current flag is high active,1: Over current flag is low active"
|
|
bitfld.long 0x00 1. "ABORT,AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus" "0: No ERROR response received,1: ERROR response received"
|
|
tree.end
|
|
tree "USBH_NS"
|
|
base ad:0x50009000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "HcRevision,Host Controller Revision Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision Number\nIndicates the Open HCI Specification revision number implemented by the Hardware"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HcControl,Host Controller Control Register"
|
|
bitfld.long 0x00 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state" "0: USBSUSPEND,1: USBOPERATIONAL,2: USBRESUME,3: USBRESET"
|
|
bitfld.long 0x00 5. "BLE,Bulk List Enable Bit" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
|
|
newline
|
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bitfld.long 0x00 4. "CLE,Control List Enable Bit" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next.."
|
|
bitfld.long 0x00 3. "IE,Isochronous List Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list" "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the.."
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|
newline
|
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bitfld.long 0x00 2. "PLE,Periodic List Enable Bit\nWhen set this bit enables processing of the Periodic (interrupt and isochronous) list" "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
|
|
bitfld.long 0x00 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs" "0: Number of Control EDs over Bulk EDs served is..,1: Number of Control EDs over Bulk EDs served is..,2: Number of Control EDs over Bulk EDs served is..,3: Number of Control EDs over Bulk EDs served is.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HcCommandStatus,Host Controller Command Status Register"
|
|
bitfld.long 0x00 16.--17. "SOC,Schedule Overrun Count\nThese bits are incremented on each scheduling overrun error" "0,1,2,3"
|
|
bitfld.long 0x00 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Bulk list"
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|
newline
|
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bitfld.long 0x00 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Control list"
|
|
bitfld.long 0x00 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller" "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HcInterruptStatus,Host Controller Interrupt Status Register"
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed" "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1" "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to.."
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|
newline
|
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bitfld.long 0x00 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port" "0: No resume signaling detected on a downstream..,1: Resume signaling detected on a downstream port"
|
|
bitfld.long 0x00 2. "SF,Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event" "0: Not the start of a frame,1: Indicate the start of a frame and Host.."
|
|
newline
|
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bitfld.long 0x00 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead" "0: Host Controller didn't update HccaDoneHead,1: Host Controller has written HcDoneHead to.."
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred" "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "HcInterruptEnable,Host Controller Interrupt Enable Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
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bitfld.long 0x00 2. "SF,Start of Frame Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
|
|
newline
|
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bitfld.long 0x00 0. "SO,Scheduling Overrun Enable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "HcInterruptDisable,Host Controller Interrupt Disable Register"
|
|
bitfld.long 0x00 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
|
|
newline
|
|
bitfld.long 0x00 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
|
|
bitfld.long 0x00 3. "RD,Resume Detected Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
|
|
newline
|
|
bitfld.long 0x00 2. "SF,Start of Frame Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
|
|
bitfld.long 0x00 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
|
|
newline
|
|
bitfld.long 0x00 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "HcHCCA,Host Controller Communication Area Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA)"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HcPeriodCurrentED,Host Controller Period Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "HcControlHeadED,Host Controller Control Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CHED,Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "HcControlCurrentED,Host Controller Control Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "HcBulkHeadED,Host Controller Bulk Head ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "HcBulkCurrentED,Host Controller Bulk Current ED Register"
|
|
hexmask.long 0x00 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "HcDoneHead,Host Controller Done Head Register"
|
|
hexmask.long 0x00 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "HcFmInterval,Host Controller Frame Interval Register"
|
|
bitfld.long 0x00 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0])" "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into.."
|
|
hexmask.long.word 0x00 16.--30. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame"
|
|
newline
|
|
hexmask.long.word 0x00 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1)"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "HcFmRemaining,Host Controller Frame Remaining Register"
|
|
bitfld.long 0x00 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "HcFmNumber,Host Controller Frame Number Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0])"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "HcPeriodicStart,Host Controller Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "HcLSThreshold,Host Controller Low-speed Threshold Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "LST,Low-speed Threshold"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "HcRhDescriptorA,Host Controller Root Hub Descriptor A Register"
|
|
bitfld.long 0x00 12. "NOCP,No over Current Protection\nThis bit describes how the over current status for the Root Hub ports reported" "0: Over current status is reported,1: Over current status is not reported"
|
|
bitfld.long 0x00 11. "OCPM,over Current Protection Mode\nThis bit describes how the over current status for the Root Hub ports reported" "0: Global Over current,1: Individual Over current"
|
|
newline
|
|
bitfld.long 0x00 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled" "0: Global Switching,1: Individual Switching"
|
|
hexmask.long.byte 0x00 0.--7. 1. "NDP,Number Downstream Ports\nUSB host control supports two downstream ports and only one port is available in this series of chip"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "HcRhDescriptorB,Host Controller Root Hub Descriptor B Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "HcRhStatus,Host Controller Root Hub Status Register"
|
|
bitfld.long 0x00 31. "CRWE,Clear Remote Wake-up Enable Bit\nThis bit is use to clear DRWE (HcRhStatus[15]).\nThis bit always read as zero.\nWrite Operation" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
|
|
bitfld.long 0x00 17. "OCIC,over Current Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero" "0: OCI (HcRhStatus[1]) didn't change,1: OCI (HcRhStatus[1]) change"
|
|
newline
|
|
bitfld.long 0x00 16. "LPSC,Set Global Power" "0: No effect,1: Set global power"
|
|
bitfld.long 0x00 15. "DRWE,Device Remote Wakeup Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation" "0: No effect.\nConnect Status Change as a remote..,1: Connect Status Change as a remote wake-up.."
|
|
newline
|
|
bitfld.long 0x00 1. "OCI,over Current Indicator\nThis bit reflects the state of the over current status pin" "0: No over current condition,1: Over current condition"
|
|
bitfld.long 0x00 0. "LPS,Clear Global Power" "0: No effect,1: Clear global power"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "HcRhPortStatus1,Host Controller Root Hub Port Status [1]"
|
|
bitfld.long 0x00 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero" "0: Port reset is not complete,1: Port reset is complete"
|
|
bitfld.long 0x00 19. "OCIC,Port over Current Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero" "0: POCI (HcRhPortStatus1[3]) didn't change,1: POCI (HcRhPortStatus1[3]) changes"
|
|
newline
|
|
bitfld.long 0x00 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero" "0: Port resume is not completed,1: Port resume completed"
|
|
bitfld.long 0x00 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero" "0: PES (HcRhPortStatus1[1]) didn't change,1: PES (HcRhPortStatus1[1]) changed"
|
|
newline
|
|
bitfld.long 0x00 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero" "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect.."
|
|
bitfld.long 0x00 9. "LSDA,Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed.."
|
|
newline
|
|
bitfld.long 0x00 8. "PPS,Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation" "0: No effect.\nPort power is Disabled,1: Port Power Enabled.\nPort power is Enabled"
|
|
bitfld.long 0x00 4. "PRS,Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
|
|
newline
|
|
bitfld.long 0x00 3. "POCI,Port over Current Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the over current status pin dedicated to this port" "0: No effect.\nNo over current condition,1: Clear port suspend.\nOver current condition"
|
|
bitfld.long 0x00 2. "PSS,Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively.."
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newline
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bitfld.long 0x00 1. "PES,Port Enable Status\nWrite Operation" "0: No effect.\nPort Disabled,1: Set port enable.\nPort Enabled"
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bitfld.long 0x00 0. "CCS,CurrentConnectStatus (Read) or ClearPortEnable Bit (Write)\nWrite Operation" "0: No effect.\nNo device connected,1: Clear port enable.\nDevice connected"
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group.long 0x200++0x03
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line.long 0x00 "HcPhyControl,Host Controller PHY Control Register"
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bitfld.long 0x00 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption" "0: The USB transceiver would never enter the..,1: The USB transceiver will enter standby mode.."
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group.long 0x204++0x03
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line.long 0x00 "HcMiscControl,Host Controller Miscellaneous Control Register"
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bitfld.long 0x00 16. "DPRT1,Disable Port 1\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
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bitfld.long 0x00 4. "PPCAL,Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC" "0: Port power control is high active,1: Port power control is low active"
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newline
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bitfld.long 0x00 3. "OCAL,Over Current Active Low\nThis bit controls the polarity of over current flag from external power IC" "0: Over current flag is high active,1: Over current flag is low active"
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bitfld.long 0x00 1. "ABORT,AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus" "0: No ERROR response received,1: ERROR response received"
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tree.end
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tree.end
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tree "USCII2C"
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tree "UI2C0"
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base ad:0x400D0000
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group.long 0x00++0x03
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line.long 0x00 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x08++0x03
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line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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newline
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x2C++0x03
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line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C"
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group.long 0x44++0x03
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line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
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group.long 0x48++0x03
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line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
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group.long 0x4C++0x03
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line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
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group.long 0x50++0x03
|
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line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
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group.long 0x54++0x03
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line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
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group.long 0x58++0x03
|
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line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
|
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bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
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newline
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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newline
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
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bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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newline
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
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|
bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
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newline
|
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
|
|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x60++0x03
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line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
|
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bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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newline
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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newline
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bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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newline
|
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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newline
|
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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newline
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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newline
|
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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newline
|
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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newline
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x88++0x03
|
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line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
|
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bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
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group.long 0x8C++0x03
|
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line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
|
|
tree.end
|
|
tree "UI2C0_NS"
|
|
base ad:0x500D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UI2C_CTL,USCI Control Register"
|
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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|
group.long 0x08++0x03
|
|
line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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newline
|
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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newline
|
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x2C++0x03
|
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line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
|
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
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line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
|
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C"
|
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group.long 0x44++0x03
|
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line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
|
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
|
|
group.long 0x48++0x03
|
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line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
|
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
|
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x54++0x03
|
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line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
|
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hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
|
|
newline
|
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
|
|
bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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newline
|
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
|
|
bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
|
|
newline
|
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
|
|
newline
|
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
|
|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
|
|
bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
|
|
bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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newline
|
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bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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|
newline
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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|
group.long 0x64++0x03
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|
line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
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|
bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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|
bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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|
newline
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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|
newline
|
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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|
bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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|
newline
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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|
bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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newline
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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newline
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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newline
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x88++0x03
|
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line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
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|
bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
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|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
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|
group.long 0x8C++0x03
|
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line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
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|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode"
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hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
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tree.end
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tree "UI2C1"
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base ad:0x400D1000
|
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group.long 0x00++0x03
|
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line.long 0x00 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x08++0x03
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line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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newline
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x2C++0x03
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line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C"
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group.long 0x44++0x03
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line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
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group.long 0x48++0x03
|
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line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
|
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abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
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group.long 0x4C++0x03
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line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
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group.long 0x50++0x03
|
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line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
|
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
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group.long 0x54++0x03
|
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line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
|
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bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
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newline
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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newline
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
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bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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newline
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
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bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
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newline
|
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
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|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x60++0x03
|
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line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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newline
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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newline
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bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
|
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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group.long 0x64++0x03
|
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line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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newline
|
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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newline
|
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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newline
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
|
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bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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newline
|
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
|
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bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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newline
|
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
|
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bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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newline
|
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
|
|
bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode"
|
|
hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
|
|
tree.end
|
|
tree "UI2C1_NS"
|
|
base ad:0x500D1000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UI2C_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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|
group.long 0x08++0x03
|
|
line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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newline
|
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
|
|
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
|
|
abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
|
|
abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
|
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bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled"
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bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
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bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
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bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
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|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x60++0x03
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line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected"
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bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode and user must write 1 into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
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bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x88++0x03
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line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
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bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
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bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode"
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hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode"
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tree.end
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tree.end
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tree "USCISPI"
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tree "USPI0"
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base ad:0x400D0000
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group.long 0x00++0x03
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line.long 0x00 "USPI_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
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group.long 0x38++0x03
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line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
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bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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group.long 0x3C++0x03
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line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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newline
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under run..,1: The output data level is 1 if TX under run.."
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
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bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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group.long 0x60++0x03
|
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line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]).." "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
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bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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group.long 0x64++0x03
|
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line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
|
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rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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newline
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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newline
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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newline
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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newline
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
|
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
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newline
|
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
|
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tree.end
|
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tree "USPI0_NS"
|
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base ad:0x500D0000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "USPI_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
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group.long 0x38++0x03
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line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
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bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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group.long 0x3C++0x03
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line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under run..,1: The output data level is 1 if TX under run.."
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
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bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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group.long 0x60++0x03
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line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]).." "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
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bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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group.long 0x64++0x03
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line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
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newline
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
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tree "USPI1"
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base ad:0x400D1000
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group.long 0x00++0x03
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line.long 0x00 "USPI_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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newline
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
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bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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newline
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
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group.long 0x38++0x03
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line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
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bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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group.long 0x3C++0x03
|
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line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
|
|
bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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|
bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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|
newline
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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|
bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
|
|
bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under run..,1: The output data level is 1 if TX under run.."
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|
newline
|
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
|
|
bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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|
newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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|
bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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|
newline
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
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|
bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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|
group.long 0x60++0x03
|
|
line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]).." "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
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|
bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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|
newline
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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|
bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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|
group.long 0x64++0x03
|
|
line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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|
rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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|
newline
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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|
bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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|
newline
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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|
bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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|
newline
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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|
bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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|
newline
|
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
|
|
bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
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|
newline
|
|
bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
|
|
tree "USPI1_NS"
|
|
base ad:0x500D1000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USPI_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
|
|
line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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|
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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|
newline
|
|
bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
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|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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newline
|
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
|
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line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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newline
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
|
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line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
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group.long 0x38++0x03
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line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.."
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newline
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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newline
|
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
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bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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group.long 0x3C++0x03
|
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line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
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bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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newline
|
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
|
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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newline
|
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
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group.long 0x40++0x03
|
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line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register"
|
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
|
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
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newline
|
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
|
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bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
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bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under run..,1: The output data level is 1 if TX under run.."
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newline
|
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
|
|
bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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newline
|
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
|
|
bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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newline
|
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]).." "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
|
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bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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newline
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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group.long 0x64++0x03
|
|
line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
|
|
rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
|
|
newline
|
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
|
|
bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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newline
|
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred"
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newline
|
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
|
|
bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred"
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newline
|
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred"
|
|
bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred"
|
|
tree.end
|
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tree.end
|
|
tree "USCIUART"
|
|
tree "UUART0"
|
|
base ad:0x400D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,2: fSAMP_CLK is selected to fSCLK,3: fSAMP_CLK is selected to fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0: The data word contains 16 bits located at bit..,1: Reserved,2: Reserved,3: Reserved,4: The data word contains 4 bits located at bit..,5: The data word contains 5 bits located at bit..,6: The data word contains 6 bits located at bit..,7: The data word contains 7 bits located at bit..,8: The data word contains 8 bits located at bit..,9: The data word contains 9 bits located at bit..,10: The data word contains 10 bits located at..,11: The data word contains 11 bits located at..,12: The data word contains 12 bits located at..,13: The data word contains 13 bits located at..,14: The data word contains 14 bits located at..,15: The data word contains 15 bits located at.."
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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group.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the nRTS signal is inactive automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree "UUART0_NS"
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base ad:0x500D0000
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group.long 0x00++0x03
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line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,2: fSAMP_CLK is selected to fSCLK,3: fSAMP_CLK is selected to fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0: The data word contains 16 bits located at bit..,1: Reserved,2: Reserved,3: Reserved,4: The data word contains 4 bits located at bit..,5: The data word contains 5 bits located at bit..,6: The data word contains 6 bits located at bit..,7: The data word contains 7 bits located at bit..,8: The data word contains 8 bits located at bit..,9: The data word contains 9 bits located at bit..,10: The data word contains 10 bits located at..,11: The data word contains 11 bits located at..,12: The data word contains 12 bits located at..,13: The data word contains 13 bits located at..,14: The data word contains 14 bits located at..,15: The data word contains 15 bits located at.."
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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group.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the nRTS signal is inactive automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree "UUART1"
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base ad:0x400D1000
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group.long 0x00++0x03
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line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,2: fSAMP_CLK is selected to fSCLK,3: fSAMP_CLK is selected to fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0: The data word contains 16 bits located at bit..,1: Reserved,2: Reserved,3: Reserved,4: The data word contains 4 bits located at bit..,5: The data word contains 5 bits located at bit..,6: The data word contains 6 bits located at bit..,7: The data word contains 7 bits located at bit..,8: The data word contains 8 bits located at bit..,9: The data word contains 9 bits located at bit..,10: The data word contains 10 bits located at..,11: The data word contains 11 bits located at..,12: The data word contains 12 bits located at..,13: The data word contains 13 bits located at..,14: The data word contains 14 bits located at..,15: The data word contains 15 bits located at.."
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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group.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the nRTS signal is inactive automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree "UUART1_NS"
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base ad:0x500D1000
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group.long 0x00++0x03
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line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK is selected to fDIV_CLK,1: fSAMP_CLK is selected to fPROT_CLK,2: fSAMP_CLK is selected to fSCLK,3: fSAMP_CLK is selected to fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 0x2" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0: The data word contains 16 bits located at bit..,1: Reserved,2: Reserved,3: Reserved,4: The data word contains 4 bits located at bit..,5: The data word contains 5 bits located at bit..,6: The data word contains 6 bits located at bit..,7: The data word contains 7 bits located at bit..,8: The data word contains 8 bits located at bit..,9: The data word contains 9 bits located at bit..,10: The data word contains 10 bits located at..,11: The data word contains 11 bits located at..,12: The data word contains 12 bits located at..,13: The data word contains 13 bits located at..,14: The data word contains 14 bits located at..,15: The data word contains 15 bits located at.."
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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group.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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rbitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator (Read Only)" "0: Transmit buffer is not full,1: Transmit buffer is full"
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rbitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator (Read Only)" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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rbitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator (Read Only)" "0: Receive buffer is not full,1: Receive buffer is full"
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rbitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator (Read Only)" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x40++0x03
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line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register"
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bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled"
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bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the nRTS signal is inactive automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree.end
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tree "WDT"
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base ad:0x40040000
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group.long 0x00++0x03
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line.long 0x00 "WDT_CTL,WDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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bitfld.long 0x00 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK"
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bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: WDT Disabled (This action will reset the..,1: WDT Enabled"
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bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag \nThis bit indicates the interrupt wake-up flag status of WDT\nNote: This bit is cleared by writing 1 to it" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.."
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bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred"
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bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred"
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bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by programming 0x5AA5 to RSTCNT to prevent WDT time-out reset happened" "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
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wgroup.long 0x08++0x03
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line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active.\nRSTCNT (WDT_RSTCNT[31:0]) bits are not.."
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tree.end
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tree "WWDT"
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base ad:0x40040100
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wgroup.long 0x00++0x03
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line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.."
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group.long 0x04++0x03
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line.long 0x00 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
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bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting"
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group.long 0x08++0x03
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line.long 0x00 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
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bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT"
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rgroup.long 0x0C++0x03
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line.long 0x00 "WWDT_CNT,WWDT Counter Value Register"
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bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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autoindent.off
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newline
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