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Gen4_R-Car_Trace32/2_Trunk/perm058san.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: M058SAN On-Chip Peripherals
; @Props: Released
; @Author: DAB
; @Changelog: 2022-02-24 DAB
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: SVD generated based on: M058SAN_v1 (Ver 1.0)
; @Core: Cortex-M0
; @Chip: M058SFAN, M058SZAN, M058SLAN, M058SSAN
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perm058san.per 14384 2022-02-25 08:43:23Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ADC (ADC Register Map)"
base ad:0x400E0000
rgroup.long 0x00++0x03
line.long 0x00 "ADDR0,A/D Data Register 0"
bitfld.long 0x00 17. "VALID,Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
bitfld.long 0x00 16. "OVERRUN,Over Run Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1" "0: Data in RSLT is recent conversion result,1: Data in RSLT is over"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC"
repeat 7. (strings "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 )
group.long ($2+0x04)++0x03
line.long 0x00 "ADDR$1,A/D Data Register $1"
rbitfld.long 0x00 17. "VALID,Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
rbitfld.long 0x00 16. "OVERRUN,Over Run Flag (Read Only)\nIf converted data in RSLT has not been read before new conversion result is loaded to this register OVERRUN is set to 1" "0: Data in RSLT is recent conversion result,1: Data in RSLT is over"
newline
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result\nThis field contains conversion result of ADC"
repeat.end
group.long 0x20++0x03
line.long 0x00 "ADCR,A/D Control Register"
bitfld.long 0x00 31. "DMOF,A/D differential input Mode Output Format\n" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.."
bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC" "0: Conversion stopped and A/D converter enter..,1: Conversion start"
newline
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Enable\n" "0: single-end analog input mode,1: differential analog input mode"
bitfld.long 0x00 8. "TRGEN,External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in single-cycle scan mode" "0: Disable,1: Enable"
newline
bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS" "0: A/D conversion is started by external STADC pin,?,?,3: A/D conversion is started by PWM trigger"
newline
bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode\nWhen changing the operation mode software should disable ADST bit firstly.\nNote: In Burst Mode the A/D result data always at Data Register 0" "0: Single conversion,1: Burst conversion,2: Single-cycle scan,3: Continuous scan"
bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1" "0: Disable A/D interrupt function,1: Enable A/D interrupt function"
newline
bitfld.long 0x00 0. "ADEN,A/D Converter Enable\nBefore starting A/D conversion function this bit should be set to 1" "0: Disable,1: Enable"
group.long 0x24++0x03
line.long 0x00 "ADCHER,A/D Channel Enable Register"
bitfld.long 0x00 8.--9. "PRESEL,Analog Input Channel 7 select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7 ADC clock rate needs to be limited to lower than 300 KHz" "0: External Analog Input,1: Internal Bandgap voltage,2: Internal temperature sensor,3: Reserved"
bitfld.long 0x00 7. "CHEN7,Analog Input Channel 7 Enable\n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 6. "CHEN6,Analog Input Channel 6 Enable\n" "0: Disable,1: Enable"
bitfld.long 0x00 5. "CHEN5,Analog Input Channel 5 Enable\n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 4. "CHEN4,Analog Input Channel 4 Enable\n" "0: Disable,1: Enable"
bitfld.long 0x00 3. "CHEN3,Analog Input Channel 3 Enable\n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 2. "CHEN2,Analog Input Channel 2 Enable\n" "0: Disable,1: Enable"
bitfld.long 0x00 1. "CHEN1,Analog Input Channel 1 Enable\n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 0. "CHEN0,Analog Input Channel 0 Enable\n" "0: Disable,1: Enable"
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
group.long ($2+0x28)++0x03
line.long 0x00 "ADCMPR$1,A/D Compare Register $1"
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel"
bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2] the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3.--5. "CMPCH,Compare Channel Selection\n" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be.."
bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
newline
bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE is set to 1 a compare interrupt request is generated" "0: Disable compare function interrupt,1: Enable compare function interrupt"
bitfld.long 0x00 0. "CMPEN,Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register" "0: Disable compare function,1: Enable compare function"
repeat.end
group.long 0x30++0x03
line.long 0x00 "ADSR,A/D Status Register"
hexmask.long.byte 0x00 16.--23. 1. "OVERRUN,Over Run flag (Read Only)\nIt is a mirror to OVERRUN bit in ADDRx\nWhen ADC in Burst Mode and the FIFO is overrun OVERRUN[7:0] will all set to 1"
hexmask.long.byte 0x00 8.--15. 1. "VALID,Data Valid flag (Read Only)\nIt is a mirror of VALID bit in ADDRx\nWhen ADC in Burst Mode and the FIFO is valid VALID[7:0] will all set to 1"
newline
bitfld.long 0x00 4.--6. "CHANNEL,Current Conversion Channel\nIt is read only" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "BUSY,BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
newline
bitfld.long 0x00 2. "CMPF1,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting"
bitfld.long 0x00 1. "CMPF0,Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0setting"
newline
bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these three conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nWhen more than 4.." "0,1"
group.long 0x44++0x03
line.long 0x00 "ADTDCR,A/D Trigger Delay Control Register"
hexmask.long.byte 0x00 0.--7. 1. "PTDT,PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock"
tree.end
tree "CLK (CLK Register Map)"
base ad:0x50000200
group.long 0x00++0x03
line.long 0x00 "PWRCON,System Power Down Control Register"
bitfld.long 0x00 8. "PD_WAIT_CPU,This bit control the power down entry condition (write-protected)\n" "0: Chip entry power down mode when the..,1: Chip enter power down mode when the both.."
bitfld.long 0x00 7. "PWR_DOWN_EN,System power down enable bit (write-protected)\nWhen CPU sets this bit 1 the chip power down mode is enabled and chip power-down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0 then the chip enters power down mode.." "0: Chip operate in normal mode or CPU in idle..,1: Chip enter the power down mode instant or.."
newline
bitfld.long 0x00 6. "PD_WU_STS,Power down mode wake up interrupt status\nSet by power down wake up event it indicates that resume from power down mode \nThe flag is set if the GPIO UART WDT ACMP ACMP1 I2C TIMER or BOD wakeup occurred\nWrite 1 to clear the bit to.." "0,1"
bitfld.long 0x00 5. "PD_WU_INT_EN,Power down mode wake Up Interrupt Enable (write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high" "0: Disable,1: Enable"
newline
bitfld.long 0x00 4. "PD_WU_DLY,Enable the wake up delay counter" "0: Disable clock cycles delay,1: Enable clock cycles delay"
bitfld.long 0x00 3. "OSC10K_EN,Internal 10 kHz Oscillator enable (write-protected)\n" "0: 10 kHz Oscillation disable,1: 10 kHz Oscillation enable"
newline
bitfld.long 0x00 2. "OSC22M_EN,Internal 22.1184 MHz Oscillator enable (write-protected)\n" "0: 22.1184 MHz Oscillation disable,1: 22.1184 MHz Oscillation enable"
bitfld.long 0x00 0. "XTL12M_EN,External Crystal Oscillator enable (write-protected)\nThe bit default value is set by flash controller user configuration register config0 [26:24]" "0: Crystal oscillation disable,1: Crystal oscillation enable"
group.long 0x04++0x03
line.long 0x00 "AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x00 2. "ISP_EN,Flash ISP Controller Clock Enable Control.\n" "0: To disable the Flash ISP controller clock,1: To enable the Flash ISP controller clock"
group.long 0x08++0x03
line.long 0x00 "APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x00 28. "ADC_EN,Analog-Digital-Converter (ADC) Clock Enable\n" "0: Disable ADC clock,1: Enable ADC clock"
bitfld.long 0x00 21. "PWM23_EN,PWM_23 Clock Enable\n" "0: Disable PWM23 clock,1: Enable PWM23 clock"
newline
bitfld.long 0x00 20. "PWM01_EN,PWM_01 Clock Enable\n" "0: Disable PWM01 clock,1: Enable PWM01 clock"
bitfld.long 0x00 16. "UART0_EN,UART Clock Enable\n" "0: Disable UART clock,1: Enable UART clock"
newline
bitfld.long 0x00 12. "SPI0_EN,SPI0 Clock Enable\n" "0: Disable SPI0 Clock,1: Enable SPI0 Clock"
bitfld.long 0x00 9. "I2C1_EN,I2C1 Clock Enable \n" "0: Disable I2C1 Clock,1: Enable I2C1 Clock"
newline
bitfld.long 0x00 8. "I2C_EN,I2C0 Clock Enable \n" "0: Disable I2C0 Clock,1: Enable I2C0 Clock"
bitfld.long 0x00 6. "FDIV_EN,Clock Divider Clock Enable\n" "0: Disable FDIV Clock,1: Enable FDIV Clock"
newline
bitfld.long 0x00 5. "TMR3_EN,Timer3 Clock Enable\n" "0: Disable Timer3 Clock,1: Enable Timer3 Clock"
bitfld.long 0x00 4. "TMR2_EN,Timer2 Clock Enable\n" "0: Disable Timer2 Clock,1: Enable Timer2 Clock"
newline
bitfld.long 0x00 3. "TMR1_EN,Timer1 Clock Enable\n" "0: Disable Timer1 Clock,1: Enable Timer1 Clock"
bitfld.long 0x00 2. "TMR0_EN,Timer0 Clock Enable\n" "0: Disable Timer0 Clock,1: Enable Timer0 Clock"
newline
bitfld.long 0x00 0. "WDT_EN,Watchdog Timer Clock Enable (write-protected)\n" "0: Disable Watchdog Timer Clock,1: Enable Watchdog Timer Clock"
group.long 0x0C++0x03
line.long 0x00 "CLKSTATUS,Clock status monitor Register"
bitfld.long 0x00 7. "CLK_SW_FAIL,Clock switch fail flag\nThis bit will be set when target switch clock source is not stable" "0: Clock switch if success,1: Clock switch if fail"
rbitfld.long 0x00 4. "OSC22M_STB,OSC22M (Internal 22.1184 MHz) clock source stable flag (Read Only)\n" "0: OSC22M clock is not stable or disable,1: OSC22M clock is stable"
newline
rbitfld.long 0x00 3. "OSC10K_STB,OSC10K clock source stable flag (Read Only)\n" "0: OSC10K clock is not stable or disable,1: OSC10K clock is stable"
rbitfld.long 0x00 2. "PLL_STB,PLL clock source stable flag (Read Only)\n" "0: PLL clock is not stable or disable,1: PLL clock is stable"
newline
rbitfld.long 0x00 0. "XTL12M_STB,External Crystal clock source stable flag (Read Only)\n" "0: External Crystal clock is not stable or disable,1: External Crystal clock is stable"
group.long 0x10++0x03
line.long 0x00 "CLKSEL0,Clock Source Select Control Register 0"
bitfld.long 0x00 3.--5. "STCLK_S,MCU Cortex_M0 SysTick clock source select (write-protected)\n" "0: Clock source from external crystal clock (4 ~..,1: Reserved,2: Clock source from external crystal clock/2 (4..,3: Clock source from HCLK/2,?,?,?,7: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 0.--2. "HCLK_S,HCLK clock source select (write-protected)\nNote:\nBefore clock switching the related clock sources (both pre-select and new-select) must be turn on\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user.." "0: Clock source from external crystal clock (4 ~..,1: Reserved,2: Clock source from PLL clock,3: Clock source from internal 10 kHz oscillator..,?,?,?,7: Clock source from internal 22.1184 MHz.."
group.long 0x14++0x03
line.long 0x00 "CLKSEL1,Clock Source Select Control Register 1"
bitfld.long 0x00 30.--31. "PWM23_S,PWM2 and PWM3 clock source select.\nPWM2 and PWM3 uses the same Engine clock source both of them use the same pre-scalar\n" "0: Clock source from external crystal clock (4 ~..,1: Reserved,2: Clock source from HCLK,3: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 28.--29. "PWM01_S,PWM0 and PWM1 clock source select.\nPWM0 and PWM1 uses the same Engine clock source both of them use the same pre-scalar\n" "0: Clock source from external crystal clock ( 4..,1: Reserved,2: Clock source from HCLK,3: Clock source from internal 22.1184 MHz.."
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bitfld.long 0x00 24.--25. "UART_S,UART clock source select.\n" "0: Clock source from external crystal clock (4 ~..,1: Clock source from PLL clock,2: Reserved,3: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 20.--22. "TMR3_S,TIMER3 clock source select.\n" "0: Clock source from external crystal clock (4 ~..,?,2: Clock source from HCLK,3: Clock source from external trigger T3,?,5: Clock source from internal 10 kHz low speed..,?,7: Clock source from internal 22.1184 MHz.."
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bitfld.long 0x00 16.--18. "TMR2_S,TIMER2 clock source select.\n" "0: Clock source from external crystal clock (4 ~..,?,2: Clock source from HCLK,3: Clock source from external trigger T2,?,5: Clock source from internal 10 kHz low speed..,?,7: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 12.--14. "TMR1_S,TIMER1 clock source select.\n" "0: Clock source from external crystal clock (4 ~..,?,2: Clock source from HCLK,3: Clock source from external trigger T1,?,5: Clock source from internal 10 kHz low speed..,?,7: Clock source from internal 22.1184 MHz.."
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bitfld.long 0x00 8.--10. "TMR0_S,TIMER0 clock source select.\n" "0: Clock source from external crystal clock (4 ~..,?,2: Clock source from HCLK,3: Clock source from external trigger T0,?,5: Clock source from internal 10 kHz low speed..,?,7: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 4. "SPI0_S,SPI0 clock source select\n" "0: Clock source from PLL clock,1: Clock source from HCLK"
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bitfld.long 0x00 2.--3. "ADC_S,ADC clock source select\n" "0: Clock source from external crystal clock (4 ~..,1: Clock source from PLL clock,2: Clock source from HCLK,3: Clock source from internal 22.1184 MHz.."
bitfld.long 0x00 0.--1. "WDT_S,WDT clock source select (write-protected)\n" "0: Reserved,1: Reserved,2: Clock source from HCLK/2048 clock,3: Clock source from internal 10 kHz oscillator.."
group.long 0x18++0x03
line.long 0x00 "CLKDIV,Clock Divider Number Register"
hexmask.long.byte 0x00 16.--23. 1. "ADC_N,ADC clock divide number from ADC clock source\n"
bitfld.long 0x00 8.--11. "UART_N,UART clock divide number from UART clock source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "HCLK_N,HCLK clock divide number from HCLK clock source\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "CLKSEL2,Clock Source Select Control Register 2"
bitfld.long 0x00 16.--17. "WWDT_S,Window Watchdog Timer clock source select\n" "?,?,2: Clock source from HCLK/2048 clock,3: Clock source from internal 10 kHz low speed.."
bitfld.long 0x00 2.--3. "FRQDIV_S,Clock Divider Clock Source Select\n" "0: Clock source from external crystal clock (4 ~..,1: Reserved,2: Clock source from HCLK,3: Clock source from internal 22.1184 MHz.."
group.long 0x20++0x03
line.long 0x00 "PLLCON,PLL Control Register"
bitfld.long 0x00 19. "PLL_SRC,PLL Source Clock Select\n" "0: PLL source clock from external crystal (4 ~..,1: PLL source clock from 22.1184 MHz oscillator"
bitfld.long 0x00 18. "OE,PLL OE (FOUT enable) pin Control\n" "0: PLL FOUT enable,1: PLL FOUT is fixed low"
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bitfld.long 0x00 17. "BP,PLL Bypass Control\n" "0: PLL is in normal mode (default),1: PLL clock output is same as clock input.."
bitfld.long 0x00 16. "PD,Power Down Mode" "0: PLL is in normal mode,1: PLL is in power-down mode (default)"
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bitfld.long 0x00 14.--15. "OUT_DV,PLL Output Divider Control" "0,1,2,3"
bitfld.long 0x00 9.--13. "IN_DV,PLL Input Divider Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x00 0.--8. 1. "FB_DV,PLL Feedback Divider Control"
group.long 0x24++0x03
line.long 0x00 "FRQDIV,Frequency Divider Control Register"
bitfld.long 0x00 4. "DIVIDER_EN,Frequency Divider Enable Bit\n" "0: Disable Frequency Divider,1: Enable Frequency Divider"
bitfld.long 0x00 0.--3. "FSEL,Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency\nFout is the frequency of divider output clock\nN is the 4-bit value of FSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "FMC (FMC Register Map)"
base ad:0x5000C000
group.long 0x00++0x03
line.long 0x00 "ISPCON,ISP Control Register"
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (write-protection bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is.." "0,1"
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable (write-protection bit)\nLDROM update enable bit.\n" "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x00 4. "CFGUEN,Config Update Enable (write-protected)\nWriting this bit to 1 enables s/w to update Configure value by ISP procedure regardless of program code is running in APROM or LDROM.\n" "0: Config update disable,1: Config update enable"
bitfld.long 0x00 3. "APUEN,APROM Update Enable (write-protected)\n" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
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bitfld.long 0x00 1. "BS,Boot Select (write-protected)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: boot from APROM,1: boot from LDROM"
bitfld.long 0x00 0. "ISPEN,ISP Enable (write-protected)\nISP function enable bit" "0: Disable ISP function,1: Enable ISP function"
group.long 0x04++0x03
line.long 0x00 "ISPADR,ISP Address Register"
hexmask.long 0x00 0.--31. 1. "ISPADR,ISP Address \nM058SLAN equips with a 8k x 32 embedded flash it supports word program only"
group.long 0x08++0x03
line.long 0x00 "ISPDAT,ISP Data Register"
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data \nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation"
group.long 0x0C++0x03
line.long 0x00 "ISPCMD,ISP Command Register"
bitfld.long 0x00 5. "FOEN,ISP Command" "0,1"
bitfld.long 0x00 4. "FCEN,ISP Command" "0,1"
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bitfld.long 0x00 0.--3. "FCTRL,ISP Command \n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "ISPTRG,ISP Trigger Register"
bitfld.long 0x00 0. "ISPGO,ISP start trigger(write-protected)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finish.\n" "0: ISP done,1: ISP is on going"
rgroup.long 0x14++0x03
line.long 0x00 "DFBADR,Data Flash Base Address"
hexmask.long 0x00 0.--31. 1. "DFBADR,Data Flash Base Address\nThis register indicates data flash start address"
group.long 0x18++0x03
line.long 0x00 "FATCON,Flash Access Time Control Register"
bitfld.long 0x00 4. "LFOM,Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz chip can work more efficiently by setting this bit to 1\n" "0: Low frequency optimization mode Disabled,1: Low frequency optimization mode Enabled"
tree.end
tree "GCR (GCR Register Map)"
base ad:0x50000000
rgroup.long 0x00++0x03
line.long 0x00 "PDID,Part Device Identification number Register"
hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number\nThis register reflects device part number code"
group.long 0x04++0x03
line.long 0x00 "RSTSRC,System Reset Source Register"
bitfld.long 0x00 7. "RSTS_CPU,The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero" "0: No reset from CPU,1: The Cortex-M0 CPU kernel and FMC are reset by.."
bitfld.long 0x00 5. "RSTS_MCU,The RSTS_MCU flag is set by the reset signal from the MCU Cortex_M0 kernel to indicate the previous reset source.\nThis bit is cleared by writing 1 to itself" "0: No reset from MCU,1: The MCU Cortex_M0 had issued the reset signal.."
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bitfld.long 0x00 4. "RSTS_BOD,The RSTS_BOD flag is set by the reset signal from the Brown-Out Detector to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero" "0: No reset from BOD,1: The Brown-Out Detector module had issued the.."
bitfld.long 0x00 3. "RSTS_LVR,The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero" "0: No reset from LVR,1: The LVR module had issued the reset signal to.."
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bitfld.long 0x00 2. "RSTS_WDT,The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero" "0: No reset from Watchdog timer,1: The Watchdog timer had issued the reset.."
bitfld.long 0x00 1. "RSTS_RESET,The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero" "0: No reset from Pin /RESET,1: The Pin /RESET had issued the reset signal to.."
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bitfld.long 0x00 0. "RSTS_POR,The RSTS_POR flag is set by the reset signal which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set to indicate the previous reset source.\nSoftware can write 1 to clear this bit to zero" "0: No reset from POR or CHIP_RST,1: The Power-On-Reset (POR) or CHIP_RST had.."
group.long 0x08++0x03
line.long 0x00 "IPRSTC1,Peripheral Reset Control Register 1"
bitfld.long 0x00 1. "CPU_RST,CPU kernel one shot reset (write-protected)\nSet this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC)" "0: Normal,1: Reset CPU"
bitfld.long 0x00 0. "CHIP_RST,CHIP one shot reset (write-protected)\nSet this bit will reset the CHIP including CPU kernel and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is same as the POR reset all the chip module is.." "0: Normal,1: Reset CHIP"
group.long 0x0C++0x03
line.long 0x00 "IPRSTC2,Peripheral Reset Control Register 2"
bitfld.long 0x00 28. "ADC_RST,ADC Controller Reset\n" "0: ADC controller normal operation,1: ADC controller reset"
bitfld.long 0x00 20. "PWM03_RST,PWM0~3 controller Reset\n" "0: PWM0~3 controller normal operation,1: PWM0~3 controller reset"
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bitfld.long 0x00 16. "UART0_RST,UART controller Reset\n" "0: UART controller normal operation,1: UART controller reset"
bitfld.long 0x00 12. "SPI0_RST,SPI0 controller Reset\n" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x00 9. "I2C1_RST,I2C1 controller Reset\n" "0: I2C1 controller normal operation,1: I2C1 controller reset"
bitfld.long 0x00 8. "I2C_RST,I2C0 controller Reset\n" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 5. "TMR3_RST,Timer3 controller Reset\n" "0: Timer3 controller normal operation,1: Timer3 controller reset"
bitfld.long 0x00 4. "TMR2_RST,Timer2 controller Reset\n" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1_RST,Timer1 controller Reset\n" "0: Timer1 controller normal operation,1: Timer1 controller reset"
bitfld.long 0x00 2. "TMR0_RST,Timer0 controller Reset\n" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIO_RST,GPIO (P0~P7) controller Reset\n" "0: GPIO controller normal operation,1: GPIO controller reset"
group.long 0x18++0x03
line.long 0x00 "BODCR,Brown-Out Detector Control Register"
bitfld.long 0x00 7. "LVR_EN,Low Voltage Reset Enable (write-protected)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting" "0: Disabled Low Voltage Reset function,1: Enabled Low Voltage Reset function - After.."
bitfld.long 0x00 6. "BOD_OUT,Brown-Out Detector output status\n" "0: Brown-Out Detector output status is 0,1: Brown-Out Detector output status is 1"
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bitfld.long 0x00 5. "BOD_LPM,Brown-Out Detector Low power Mode (write-protected)\nThe BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response" "0: BOD operate in normal mode (default),1: Enable the BOD low power mode"
bitfld.long 0x00 4. "BOD_INTF,Brown-Out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero" "0: Brown-Out Detector does not detect any..,1: When Brown-Out Detector detects the VDD is.."
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bitfld.long 0x00 3. "BOD_RSTEN,Brown-Out Reset Enable (write-protected)\nWhile the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low) BOD will assert an interrupt if BOD_OUT is high" "0: Enable the Brown-Out INTERRUPT function,1: Enable the Brown-Out RESET function"
bitfld.long 0x00 1.--2. "BOD_VL,Brown-Out Detector Threshold Voltage Selection (write-protected)\n" "0,1,2,3"
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bitfld.long 0x00 0. "BOD_EN,Brown-Out Detector Enable (write-protected)\nThe default value is set by flash controller user configuration register config0 bit[23]\n" "0: Brown-Out Detector function is disabled,1: Brown-Out Detector function is enabled"
group.long 0x1C++0x03
line.long 0x00 "TEMPCR,Temperature Sensor Control Register"
bitfld.long 0x00 0. "VTEMP_EN,Temperature sensor Enable\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1 the value of temperature can get from ADC conversion result by ADC channel selecting channel 7 and alternative multiplexer.." "0: Disabled temperature sensor function (default),1: Enabled temperature sensor function"
group.long 0x24++0x03
line.long 0x00 "PORCR,Power-On-Reset Controller Register"
hexmask.long.word 0x00 0.--15. 1. "POR_DIS_CODE,Power-On-Reset enable control (write-protected)\nWhen power on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
group.long 0x30++0x03
line.long 0x00 "P0_MFP,P0 multiple function and input type control register"
bitfld.long 0x00 25. "P0_ALT11,P0.1 alternate function Selection1\nThe pin function of P0.1 depends on P0_MFP[1] P0_ALT[1] and P0_ALT1[1].\nRefer to P0_ALT[1] for details descriptions" "0,1"
bitfld.long 0x00 24. "P0_ALT10,P0.0 alternate function Selection1\nThe pin function of P0.0 depends on P0_MFP[0] P0_ALT[0] and P0_ALT1[0].\nRefer to P0_ALT[0] for details descriptions" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "P0_TYPEn,P0[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 15. "P0_ALT7,P0.7 alternate function Selection\n" "0,1"
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bitfld.long 0x00 14. "P0_ALT6,P0.6 alternate function Selection\n" "0,1"
bitfld.long 0x00 13. "P0_ALT5,P0.5 alternate function Selection\n" "0,1"
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bitfld.long 0x00 12. "P0_ALT4,P0.4 alternate function Selection\n" "0,1"
bitfld.long 0x00 11. "P0_ALT3,P0.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P0_ALT2,P0.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P0_ALT1,P0.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P0_ALT0,P0.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P0_MFP,P0 multiple function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT for details descriptions"
group.long 0x34++0x03
line.long 0x00 "P1_MFP,P1 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P1_TYPEn,P1[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 15. "P1_ALT7,P1.7 alternate function Selection\n" "0,1"
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bitfld.long 0x00 14. "P1_ALT6,P1.6 alternate function Selection\n" "0,1"
bitfld.long 0x00 13. "P1_ALT5,P1.5 alternate function Selection\n" "0,1"
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bitfld.long 0x00 12. "P1_ALT4,P1.4 alternate function Selection\n" "0,1"
bitfld.long 0x00 11. "P1_ALT3,P1.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P1_ALT2,P1.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P1_ALT1,P1.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P1_ALT0,P1.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P1_MFP,P1 multiple function Selection\nThe pin function of P1 is depending on P1_MFP and P1_ALT.\nRefer to P1_ALT for details descriptions"
group.long 0x38++0x03
line.long 0x00 "P2_MFP,P2 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P2_TYPEn,P2[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 15. "P2_ALT7,P2.7 alternate function Selection\n" "0,1"
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bitfld.long 0x00 14. "P2_ALT6,P2.6 alternate function Selection\n" "0,1"
bitfld.long 0x00 13. "P2_ALT5,P2.5 alternate function Selection\n" "0,1"
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bitfld.long 0x00 12. "P2_ALT4,P2.4 alternate function Selection\n" "0,1"
bitfld.long 0x00 11. "P2_ALT3,P2.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P2_ALT2,P2.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P2_ALT1,P2.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P2_ALT0,P2.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P2_MFP,P2 multiple function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT for details descriptions"
group.long 0x3C++0x03
line.long 0x00 "P3_MFP,P3 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P3_TYPEn,P3[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 15. "P3_ALT7,P3.7 alternate function Selection\n" "0,1"
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bitfld.long 0x00 14. "P3_ALT6,P3.6 alternate function Selection\n" "0,1"
bitfld.long 0x00 13. "P3_ALT5,P3.5 alternate function Selection\n" "0,1"
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bitfld.long 0x00 12. "P3_ALT4,P3.4 alternate function Selection\n" "0,1"
bitfld.long 0x00 11. "P3_ALT3,P3.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P3_ALT2,P3.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P3_ALT1,P3.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P3_ALT0,P3.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P3_MFP,P3 multiple function Selection\nThe pin function of P3 is depending on P3_MFP and P3_ALT.\nRefer to P3_ALT for details descriptions"
group.long 0x40++0x03
line.long 0x00 "P4_MFP,P4 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P4_TYPEn,P4[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 15. "P4_ALT7,P4.7 alternate function Selection\n" "0,1"
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bitfld.long 0x00 14. "P4_ALT6,P4.6 alternate function Selection\n" "0,1"
bitfld.long 0x00 13. "P4_ALT5,P4.5 alternate function Selection\n" "0,1"
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bitfld.long 0x00 12. "P4_ALT4,P4.4 alternate function Selection\n" "0,1"
bitfld.long 0x00 11. "P4_ALT3,P4.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P4_ALT2,P4.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P4_ALT1,P4.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P4_ALT0,P4.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P4_MFP,P4 multiple function Selection\nThe pin function of P4 is depending on P4_MFP and P4_ALT.\nRefer to P4_ALT for details descriptions"
group.long 0x44++0x03
line.long 0x00 "P5_MFP,P5 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P5_TYPEn,P5[7:0] input Schmitt Trigger function Enable\n"
bitfld.long 0x00 11. "P5_ALT3,P5.3 alternate function Selection\n" "0,1"
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bitfld.long 0x00 10. "P5_ALT2,P5.2 alternate function Selection\n" "0,1"
bitfld.long 0x00 9. "P5_ALT1,P5.1 alternate function Selection\n" "0,1"
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bitfld.long 0x00 8. "P5_ALT0,P5.0 alternate function Selection\n" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "P5_MFP,P5 multiple function Selection\nThe pin function of P5 is depending on P5_MFP and P5_ALT.\nRefer to P5_ALT for details descriptions"
group.long 0x48++0x03
line.long 0x00 "P6_MFP,P6 multiple function and input type control register"
hexmask.long.byte 0x00 16.--23. 1. "P6_TYPEn,P6[7:0] input Schmitt Trigger function Enable\n"
group.long 0x100++0x03
line.long 0x00 "REGWRPROT,Register Write-Protection Control Register"
hexmask.long.byte 0x00 0.--7. 1. "REGWRPROT,Register Write-Protected Code (Write Only)\nProgramming a write-protected register must remove write-protected function by programming a sequence of value 59h 16h 88h to this field"
rbitfld.long 0x00 0. "REGPROTDIS,Register Write-Protected Disable index (Read only)\n" "0: Protection is enabled for writing protected..,1: Protection is disabled for writing protected.."
tree.end
tree "GP (GP Register Map)"
base ad:0x50004000
group.long 0x00++0x03
line.long 0x00 "P0_PMD,P0 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x04++0x03
line.long 0x00 "P0_OFFD,P0 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x08++0x03
line.long 0x00 "P0_DOUT,P0 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x0C++0x03
line.long 0x00 "P0_DMASK,P0 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
rgroup.long 0x10++0x03
line.long 0x00 "P0_PIN,P0 Pin Value"
bitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
bitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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bitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
bitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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bitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
bitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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bitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
bitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x14++0x03
line.long 0x00 "P0_DBEN,P0 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x18++0x03
line.long 0x00 "P0_IMD,P0 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x1C++0x03
line.long 0x00 "P0_IEN,P0 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x20++0x03
line.long 0x00 "P0_ISRC,P0 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x40++0x03
line.long 0x00 "P1_PMD,P1 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x44++0x03
line.long 0x00 "P1_OFFD,P1 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x48++0x03
line.long 0x00 "P1_DOUT,P1 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x4C++0x03
line.long 0x00 "P1_DMASK,P1 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x50++0x03
line.long 0x00 "P1_PIN,P1 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x54++0x03
line.long 0x00 "P1_DBEN,P1 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x58++0x03
line.long 0x00 "P1_IMD,P1 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x5C++0x03
line.long 0x00 "P1_IEN,P1 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x60++0x03
line.long 0x00 "P1_ISRC,P1 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x80++0x03
line.long 0x00 "P2_PMD,P2 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x84++0x03
line.long 0x00 "P2_OFFD,P2 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x88++0x03
line.long 0x00 "P2_DOUT,P2 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x8C++0x03
line.long 0x00 "P2_DMASK,P2 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x90++0x03
line.long 0x00 "P2_PIN,P2 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x94++0x03
line.long 0x00 "P2_DBEN,P2 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x98++0x03
line.long 0x00 "P2_IMD,P2 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x9C++0x03
line.long 0x00 "P2_IEN,P2 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0xA0++0x03
line.long 0x00 "P2_ISRC,P2 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0xC0++0x03
line.long 0x00 "P3_PMD,P3 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0xC4++0x03
line.long 0x00 "P3_OFFD,P3 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0xC8++0x03
line.long 0x00 "P3_DOUT,P3 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0xCC++0x03
line.long 0x00 "P3_DMASK,P3 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0xD0++0x03
line.long 0x00 "P3_PIN,P3 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0xD4++0x03
line.long 0x00 "P3_DBEN,P3 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0xD8++0x03
line.long 0x00 "P3_IMD,P3 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0xDC++0x03
line.long 0x00 "P3_IEN,P3 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0xE0++0x03
line.long 0x00 "P3_ISRC,P3 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x100++0x03
line.long 0x00 "P4_PMD,P4 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x104++0x03
line.long 0x00 "P4_OFFD,P4 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x108++0x03
line.long 0x00 "P4_DOUT,P4 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x10C++0x03
line.long 0x00 "P4_DMASK,P4 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x110++0x03
line.long 0x00 "P4_PIN,P4 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x114++0x03
line.long 0x00 "P4_DBEN,P4 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x118++0x03
line.long 0x00 "P4_IMD,P4 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x11C++0x03
line.long 0x00 "P4_IEN,P4 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x120++0x03
line.long 0x00 "P4_ISRC,P4 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x180++0x03
line.long 0x00 "DBNCECON,De-bounce Cycle Control"
bitfld.long 0x00 5. "ICLK_ON,Interru\nIt is recommended to turn off this bit to save system power if on special application concern" "0: Edge detection circuit is active only if IO..,1: All IO pins edge detection circuit is always.."
bitfld.long 0x00 4. "DBCLKSRC,De-bounce counter clock source select\n" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce sampling cycle selection\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x200++0x03
line.long 0x00 "P00_DOUT,P0.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x204++0x03
line.long 0x00 "P01_DOUT,P0.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x208++0x03
line.long 0x00 "P02_DOUT,P0.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x20C++0x03
line.long 0x00 "P03_DOUT,P0.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x210++0x03
line.long 0x00 "P04_DOUT,P0.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x214++0x03
line.long 0x00 "P05_DOUT,P0.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x218++0x03
line.long 0x00 "P06_DOUT,P0.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x21C++0x03
line.long 0x00 "P07_DOUT,P0.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x220++0x03
line.long 0x00 "P10_DOUT,P1.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x224++0x03
line.long 0x00 "P11_DOUT,P1.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x228++0x03
line.long 0x00 "P12_DOUT,P1.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x22C++0x03
line.long 0x00 "P13_DOUT,P1.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x230++0x03
line.long 0x00 "P14_DOUT,P1.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x234++0x03
line.long 0x00 "P15_DOUT,P1.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x238++0x03
line.long 0x00 "P16_DOUT,P1.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x23C++0x03
line.long 0x00 "P17_DOUT,P1.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x240++0x03
line.long 0x00 "P20_DOUT,P2.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x244++0x03
line.long 0x00 "P21_DOUT,P2.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x248++0x03
line.long 0x00 "P22_DOUT,P2.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x24C++0x03
line.long 0x00 "P23_DOUT,P2.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x250++0x03
line.long 0x00 "P24_DOUT,P2.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x254++0x03
line.long 0x00 "P25_DOUT,P2.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x258++0x03
line.long 0x00 "P26_DOUT,P2.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x25C++0x03
line.long 0x00 "P27_DOUT,P2.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x260++0x03
line.long 0x00 "P30_DOUT,P3.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x264++0x03
line.long 0x00 "P31_DOUT,P3.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x268++0x03
line.long 0x00 "P32_DOUT,P3.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x26C++0x03
line.long 0x00 "P33_DOUT,P3.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x270++0x03
line.long 0x00 "P34_DOUT,P3.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x274++0x03
line.long 0x00 "P35_DOUT,P3.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x278++0x03
line.long 0x00 "P36_DOUT,P3.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x27C++0x03
line.long 0x00 "P37_DOUT,P3.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x280++0x03
line.long 0x00 "P40_DOUT,P4.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x284++0x03
line.long 0x00 "P41_DOUT,P4.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x288++0x03
line.long 0x00 "P42_DOUT,P4.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x28C++0x03
line.long 0x00 "P43_DOUT,P4.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x290++0x03
line.long 0x00 "P44_DOUT,P4.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x294++0x03
line.long 0x00 "P45_DOUT,P4.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x298++0x03
line.long 0x00 "P46_DOUT,P4.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x29C++0x03
line.long 0x00 "P47_DOUT,P4.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x2C0++0x03
line.long 0x00 "P5_PMD,P5 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x2C4++0x03
line.long 0x00 "P5_OFFD,P5 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x2C8++0x03
line.long 0x00 "P5_DOUT,P5 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x2CC++0x03
line.long 0x00 "P5_DMASK,P5 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x2D0++0x03
line.long 0x00 "P5_PIN,P5 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x2D4++0x03
line.long 0x00 "P5_DBEN,P5 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x2D8++0x03
line.long 0x00 "P5_IMD,P5 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x2DC++0x03
line.long 0x00 "P5_IEN,P5 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x2E0++0x03
line.long 0x00 "P5_ISRC,P5 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x300++0x03
line.long 0x00 "P6_PMD,P6 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x304++0x03
line.long 0x00 "P6_OFFD,P6 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x308++0x03
line.long 0x00 "P6_DOUT,P6 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x30C++0x03
line.long 0x00 "P6_DMASK,P6 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x310++0x03
line.long 0x00 "P6_PIN,P6 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x314++0x03
line.long 0x00 "P6_DBEN,P6 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x318++0x03
line.long 0x00 "P6_IMD,P6 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x31C++0x03
line.long 0x00 "P6_IEN,P6 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x320++0x03
line.long 0x00 "P6_ISRC,P6 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x340++0x03
line.long 0x00 "P7_PMD,P7 Pin I/O Mode Control"
bitfld.long 0x00 14.--15. "PMD7,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 12.--13. "PMD6,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "PMD5,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 8.--9. "PMD4,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "PMD3,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 4.--5. "PMD2,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "PMD1,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
bitfld.long 0x00 0.--1. "PMD0,Px I/O Pin[n] Mode Control \nDetermine each I/O type of Px pins\n" "0: Px [n] pin is in INPUT mode,1: Px [n] pin is in OUTPUT mode,2: Px [n] pin is in Open-Drain mode,3: Px [n] pin is in Quasi-bidirectional mode"
group.long 0x344++0x03
line.long 0x00 "P7_OFFD,P7 Digital Input Path Disable Control"
hexmask.long.byte 0x00 16.--23. 1. "OFFD,OFFD: Px Pin[n] Digital Input Path Disable Control\n"
group.long 0x348++0x03
line.long 0x00 "P7_DOUT,P7 Data Output Value"
bitfld.long 0x00 7. "DOUT7,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 6. "DOUT6,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 5. "DOUT5,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 4. "DOUT4,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 3. "DOUT3,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 2. "DOUT2,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
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bitfld.long 0x00 1. "DOUT1,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
bitfld.long 0x00 0. "DOUT0,Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output open-drain and quasi-mode.\n" "0: Px Pin[n] will drive Low if the corresponding..,1: Px Pin[n] will drive High if the.."
group.long 0x34C++0x03
line.long 0x00 "P7_DMASK,P7 Data Output Write Mask"
bitfld.long 0x00 7. "DMASK7,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 6. "DMASK6,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 5. "DMASK5,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 4. "DMASK4,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 3. "DMASK3,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 2. "DMASK2,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
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bitfld.long 0x00 1. "DMASK1,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
bitfld.long 0x00 0. "DMASK0,Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]" "0: The corresponding Px_DOUT[n] bit can be updated,1: The corresponding Px_DOUT[n] bit is protected"
group.long 0x350++0x03
line.long 0x00 "P7_PIN,P7 Pin Value"
rbitfld.long 0x00 7. "PIN7,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 6. "PIN6,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 5. "PIN5,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 4. "PIN4,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 3. "PIN3,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 2. "PIN2,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
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rbitfld.long 0x00 1. "PIN1,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
rbitfld.long 0x00 0. "PIN0,Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n" "0,1"
group.long 0x354++0x03
line.long 0x00 "P7_DBEN,P7 De-bounce Enable"
bitfld.long 0x00 7. "DBEN7,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 6. "DBEN6,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 5. "DBEN5,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 4. "DBEN4,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 3. "DBEN3,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 2. "DBEN2,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
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bitfld.long 0x00 1. "DBEN1,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
bitfld.long 0x00 0. "DBEN0,Px Input Signal De-bounce Enable\nDBEN[n]used to enable the de-bounce function for each corresponding bit" "0: The bit[n] de-bounce function is disabled,1: The bit[n] de-bounce function is enabled"
group.long 0x358++0x03
line.long 0x00 "P7_IMD,P7 Interrupt Mode Control"
bitfld.long 0x00 7. "IMD7,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 6. "IMD6,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "IMD5,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 4. "IMD4,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "IMD3,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 2. "IMD2,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "IMD1,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
bitfld.long 0x00 0. "IMD0,Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
group.long 0x35C++0x03
line.long 0x00 "P7_IEN,P7 Interrupt Enable"
bitfld.long 0x00 23. "IR_EN7,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 22. "IR_EN6,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 21. "IR_EN5,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 20. "IR_EN4,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 19. "IR_EN3,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 18. "IR_EN2,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 17. "IR_EN1,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
bitfld.long 0x00 16. "IR_EN0,Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High\nIR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] level-high or low-to-high..,1: Enable the Px[n] level-high or low-to-high.."
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bitfld.long 0x00 7. "IF_EN7,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 6. "IF_EN6,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 5. "IF_EN5,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 4. "IF_EN4,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 3. "IF_EN3,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 2. "IF_EN2,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
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bitfld.long 0x00 1. "IF_EN1,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
bitfld.long 0x00 0. "IF_EN0,Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low\nIF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]" "0: Disable the Px[n] state low-level or..,1: Enable the Px[n] state low-level or.."
group.long 0x360++0x03
line.long 0x00 "P7_ISRC,P7 Interrupt Source Flag"
bitfld.long 0x00 7. "ISRC7,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 6. "ISRC6,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 5. "ISRC5,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 4. "ISRC4,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 3. "ISRC3,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 2. "ISRC2,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
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bitfld.long 0x00 1. "ISRC1,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
bitfld.long 0x00 0. "ISRC0,Port 0-7 Interrupt Source Flag \nRead :\n" "0: No interrupt at Px[n]\nNo action,1: Indicates Px[n] generate an interrupt\nClear.."
group.long 0x380++0x03
line.long 0x00 "P50_DOUT,P5.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x384++0x03
line.long 0x00 "P51_DOUT,P5.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x388++0x03
line.long 0x00 "P52_DOUT,P5.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x38C++0x03
line.long 0x00 "P53_DOUT,P5.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x390++0x03
line.long 0x00 "P54_DOUT,P5.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x394++0x03
line.long 0x00 "P55_DOUT,P5.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x398++0x03
line.long 0x00 "P56_DOUT,P5.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x39C++0x03
line.long 0x00 "P57_DOUT,P5.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3A0++0x03
line.long 0x00 "P60_DOUT,P6.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3A4++0x03
line.long 0x00 "P61_DOUT,P6.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3A8++0x03
line.long 0x00 "P62_DOUT,P6.2 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3AC++0x03
line.long 0x00 "P63_DOUT,P6.3 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3B0++0x03
line.long 0x00 "P64_DOUT,P6.4 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3B4++0x03
line.long 0x00 "P65_DOUT,P6.5 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3B8++0x03
line.long 0x00 "P66_DOUT,P6.6 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3BC++0x03
line.long 0x00 "P67_DOUT,P6.7 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3C0++0x03
line.long 0x00 "P70_DOUT,P7.0 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
group.long 0x3C4++0x03
line.long 0x00 "P71_DOUT,P7.1 Data Output Value"
bitfld.long 0x00 0. "Pxn_PDIO,GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0] read P00_PDIO will return the value.." "0: Set corresponding GPIO pin to low,1: Set corresponding GPIO pin to high"
tree.end
tree "I2C (Inter-Integrated Circuit)"
repeat 2. (list 0. 1.) (list ad:0x40020000 ad:0x40120000)
tree "I2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "I2CON,I2C Control Register"
bitfld.long 0x00 7. "EI,Enable Interrupt\n" "0: Disable I2C interrupt,1: Enable I2C interrupt"
bitfld.long 0x00 6. "ENS1,I2C Controller Enable Bit\n" "0: Disable,1: Enable"
newline
bitfld.long 0x00 5. "STA,I2C START Control Bit\nSetting STA to logic 1 to enter master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 4. "STO,I2C STOP Control Bit\nIn master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
newline
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register the SI flag is set by hardware and if bit EI (I2CON [7]) is set the I2C interrupt is requested" "0,1"
bitfld.long 0x00 2. "AA,Assert Acknowledge Control Bit\n" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2CADDR0,I2C slave Address Register0"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
group.long 0x08++0x03
line.long 0x00 "I2CDAT,I2C DATA Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CDAT,I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port"
rgroup.long 0x0C++0x03
line.long 0x00 "I2CSTATUS,I2C Status Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CSTATUS,I2C Status Register\nThe status register of I2C:\n"
group.long 0x10++0x03
line.long 0x00 "I2CLK,I2C clock divided Register"
hexmask.long.byte 0x00 0.--7. 1. "I2CLK,I2C clock divided Register\nNote: The minimum value of I2CLK is 4"
group.long 0x14++0x03
line.long 0x00 "I2CTOC,I2C Time out control Register"
bitfld.long 0x00 2. "ENTI,Time-out counter is enabled/disable\nWhen Enable the 14 bit time-out counter will start counting when SI is clear" "0: Disable,1: Enable"
bitfld.long 0x00 1. "DIV4,Time-Out counter input clock is divided by 4 \nWhen Enable The time-Out period is extend 4 times" "0: Disable,1: Enable"
newline
bitfld.long 0x00 0. "TIF,Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nS/W can write 1 to clear this bit" "0,1"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "I2CADDR$1,I2C slave Address Register $1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADDR,I2C Address Register\nThe content of this register is irrelevant when I2C is in master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: Disable General Call Function,1: Enable General Call Function"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x24)++0x03
line.long 0x00 "I2CADM$1,I2C slave Address Mask Register $1"
hexmask.long.byte 0x00 1.--7. 1. "I2CADMx,I2C Address Mask register\nI2C bus controllers support multiple address recognition with four address mask register"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "I2CWKUPCON,I2C Wake Up Control Register"
bitfld.long 0x00 0. "WKUPEN,I2C Wakeup Function Enable\n" "0: Disable I2C wake up function,1: Enable I2C wake up function"
rgroup.long 0x40++0x03
line.long 0x00 "I2CWKUPSTS,I2C Wake Up Status Register"
bitfld.long 0x00 0. "WKUPIF,I2C Wake Up Interrupt Flag\nWhen chip is waked up from power down mode by I2C this bit is set to 1" "0,1"
tree.end
repeat.end
tree.end
tree "INT (Interrupt Router)"
base ad:0x50000300
rgroup.long 0x00++0x03
line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) interrupt source identity"
bitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x04++0x03
line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x08++0x03
line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x0C++0x03
line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "IRQ4_SRC,IRQ4 (P0/1) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "IRQ5_SRC,IRQ5 (P2/3/4) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x03
line.long 0x00 "IRQ6_SRC,IRQ6 (PWM) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x03
line.long 0x00 "IRQ7_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x28++0x03
line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2C++0x03
line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "IRQ12_SRC,IRQ12 (URT) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x34++0x03
line.long 0x00 "IRQ13_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x03
line.long 0x00 "IRQ14_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C++0x03
line.long 0x00 "IRQ15_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x40++0x03
line.long 0x00 "IRQ16_SRC,IRQ16 (P5) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x44++0x03
line.long 0x00 "IRQ17_SRC,IRQ17 (P6/7) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x48++0x03
line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x4C++0x03
line.long 0x00 "IRQ19_SRC,IRQ19 (I2C1) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x50++0x03
line.long 0x00 "IRQ20_SRC,IRQ20 (PWMCAP0) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x54++0x03
line.long 0x00 "IRQ21_SRC,IRQ21(PWMCAP1) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x58++0x03
line.long 0x00 "IRQ22_SRC,IRQ22 (PWMCAP2) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x5C++0x03
line.long 0x00 "IRQ23_SRC,IRQ23 (PWMCAP3) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "IRQ24_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x03
line.long 0x00 "IRQ25_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x68++0x03
line.long 0x00 "IRQ26_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x6C++0x03
line.long 0x00 "IRQ27_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x70++0x03
line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) interrupt source identity"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x74++0x03
line.long 0x00 "IRQ29_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x78++0x03
line.long 0x00 "IRQ30_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x7C++0x03
line.long 0x00 "IRQ31_SRC,Reserved"
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "NMI_SEL,NMI source interrupt select control register"
bitfld.long 0x00 8. "NMI_EN,NMI interrupt enable (write-protection bit)\nThis bit is the protected bit" "0: Disable NMI interrupt,1: Enable NMI interrupt"
bitfld.long 0x00 0.--4. "NMI_SEL,NMI interrupt source selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the interrupt[31:0]\nThe NMI_SEL bit[4:0] used to select the NMI interrupt source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x84++0x03
line.long 0x00 "MCU_IRQ,MCU Interrupt Request Source Register"
hexmask.long 0x00 0.--31. 1. "MCU_IRQ,MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0 core"
tree.end
tree "PWM (Pulse-Width Modulator)"
base ad:0x40040000
group.long 0x00++0x03
line.long 0x00 "PPR,PWM Prescaler Register"
hexmask.long.byte 0x00 24.--31. 1. "DZI23,Dead zone interval register for pair of channel2 and channel3\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits"
hexmask.long.byte 0x00 16.--23. 1. "DZI01,Dead zone interval register for pair of channel 0 and channel 1 \nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits"
newline
hexmask.long.byte 0x00 8.--15. 1. "CP23,Clock prescaler 2 \nClock input is divided by (CP23 + 1) before it is fed to PWM counter 2 3.\n"
hexmask.long.byte 0x00 0.--7. 1. "CP01,Clock prescaler 0\nClock input is divided by (CP01 + 1) before it is fed to PWM counter 0 1.\n"
group.long 0x04++0x03
line.long 0x00 "CSR,PWM Clock Select Register"
bitfld.long 0x00 12.--14. "CSR3,Timer 3 Clock Source Selection \n" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "CSR2,Timer 2 Clock Source Selection \nSelect clock input for PWM timer.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "CSR1,Timer 1 Clock Source Selection \nSelect clock input for PWM timer.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "CSR0,Timer 0 Clock Source Selection \nSelect clock input for PWM timer.\n(Table is the same as CSR3)" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "PCR,PWM Control Register"
bitfld.long 0x00 31. "PWM23TYPE,PWM23 Aligned Type Selection Bit\n" "0: Edge-aligned type,1: Center-aligned type"
bitfld.long 0x00 30. "PWM01TYPE,PWM01 Aligned Type Selection Bit\n" "0: Edge-aligned type,1: Center-aligned type"
newline
bitfld.long 0x00 27. "CH3MOD,PWM-Timer 3 Auto-reload/One-Shot Mode \nNote: If there is a transition at this bit it will cause CNR3 and CMR3 be clear" "0: One-Shot Mode,1: Auto-reload Mode"
bitfld.long 0x00 26. "CH3INV,PWM-Timer 3 Output Inverter ON/OFF \n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 25. "CH3PINV,PWM-Timer 3 Output Polar Inverse Enable\n" "0: PWM3 output polar inverse Disabled,1: PWM3 output polar inverse Enabled"
bitfld.long 0x00 24. "CH3EN,PWM-Timer 3 Enable/Disable Start Run \n" "0: Stop corresponding PWM-Timer Running,1: Enable corresponding PWM-Timer Start Run"
newline
bitfld.long 0x00 19. "CH2MOD,PWM-Timer 2 Auto-reload/One-Shot Mode \nNote: If there is a transition at this bit it will cause CNR2 and CMR2 be clear" "0: One-Shot Mode,1: Auto-reload Mode"
bitfld.long 0x00 18. "CH2INV,PWM-Timer 2 Output Inverter ON/OFF \n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 17. "CH2PINV,PWM-Timer 2 Output Polar Inverse Enable\n" "0: PWM2 output polar inverse Disabled,1: PWM2 output polar inverse Enabled"
bitfld.long 0x00 16. "CH2EN,PWM-Timer 2 Enable/Disable Start Run \n" "0: Stop corresponding PWM-Timer Running,1: Enable corresponding PWM-Timer Start Run"
newline
bitfld.long 0x00 11. "CH1MOD,PWM-Timer 1 Auto-reload/One-Shot Mode \nNote: If there is a transition at this bit it will cause CNR1 and CMR1 be clear" "0: One-Shot Mode,1: Auto-load Mode"
bitfld.long 0x00 10. "CH1INV,PWM-Timer 1 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 9. "CH1PINV,PWM-Timer 1 Output Polar Inverse Enable\n" "0: PWM1 output polar inverse Disabled,1: PWM1 output polar inverse Enabled"
bitfld.long 0x00 8. "CH1EN,PWM-Timer 1 Enable/Disable Start Run\n" "0: Stop corresponding PWM-Timer Running,1: Enable corresponding PWM-Timer Start Run"
newline
bitfld.long 0x00 5. "DZEN23,Dead-Zone 2 Generator Enable/Disable\nNote: When Dead-Zone Generator is enabled the pair of PWM2 and PWM3 becomes a complementary pair" "0: Disable,1: Enable"
bitfld.long 0x00 4. "DZEN01,Dead-Zone 0 Generator Enable/Disable \nNote: When Dead-Zone Generator is enabled the pair of PWM0 and PWM1 becomes a complementary pair" "0: Disable,1: Enable"
newline
bitfld.long 0x00 3. "CH0MOD,PWM-Timer 0 Auto-reload/One-Shot Mode\nNote: If there is a transition at this bit it will cause CNR0 and CMR0 be clear" "0: One-Shot Mode,1: Auto-reload Mode"
bitfld.long 0x00 2. "CH0INV,PWM-Timer 0 Output Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 1. "CH0PINV,PWM-Timer 0 Output Polar Inverse Enable\n" "0: PWM0 output polar inverse Disabled,1: PWM0 output polar inverse Enabled"
bitfld.long 0x00 0. "CH0EN,PWM-Timer 0 Enable/Disable Start Run\n" "0: Stop corresponding PWM-Timer Running,1: Enable corresponding PWM-Timer Start Run"
group.long 0x0C++0x03
line.long 0x00 "CNR0,PWM Counter Register 0"
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x10++0x03
line.long 0x00 "CMR0,PWM Comparator Register 0"
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
rgroup.long 0x14++0x03
line.long 0x00 "PDR0,PWM Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter"
group.long 0x18++0x03
line.long 0x00 "CNR1,PWM Counter Register 1"
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x1C++0x03
line.long 0x00 "CMR1,PWM Comparator Register 1"
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x20++0x03
line.long 0x00 "PDR1,PWM Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter"
group.long 0x24++0x03
line.long 0x00 "CNR2,PWM Counter Register 2"
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x28++0x03
line.long 0x00 "CMR2,PWM Comparator Register 2"
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x2C++0x03
line.long 0x00 "PDR2,PWM Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter"
group.long 0x30++0x03
line.long 0x00 "CNR3,PWM Counter Register 3"
hexmask.long.word 0x00 0.--15. 1. "CNRx,PWM Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x34++0x03
line.long 0x00 "CMR3,PWM Comparator Register 3"
hexmask.long.word 0x00 0.--15. 1. "CMRx,PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CNR will take effect in next PWM cycle"
group.long 0x38++0x03
line.long 0x00 "PDR3,PWM Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "PDRx,PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter"
group.long 0x40++0x03
line.long 0x00 "PIER,PWM Interrupt Enable Register"
bitfld.long 0x00 25. "INT23DTYPE,PWM23 Duty Interrupt Type Selection Bit \nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.."
bitfld.long 0x00 24. "INT01DTYPE,PWM01 Duty Interrupt Type Selection Bit \nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type" "0: PWMDIFn will be set if PWM counter down count..,1: PWMDIFn will be set when PWM counter up count.."
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bitfld.long 0x00 17. "INT23TYPE,PWM23 Interrupt Period Type Selection Bit\nNote: Set INT23TYPE to 1 only work when PWM operating in center aligned type" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
bitfld.long 0x00 16. "INT01TYPE,PWM01 Interrupt Period Type Selection Bit\nNote: Set INT01TYPE to 1 only work when PWM operating in center aligned type" "0: PWMIFn will be set if PWM counter underflow,1: PWMIFn will be set if PWM counter matches.."
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bitfld.long 0x00 11. "PWMDIE3,PWM channel 3 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x00 10. "PWMDIE2,PWM channel 2 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 9. "PWMDIE1,PWM channel 1 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
bitfld.long 0x00 8. "PWMDIE0,PWM channel 0 Duty Interrupt Enable\n" "0: Disabled,1: Enabled"
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bitfld.long 0x00 3. "PWMIE3,PWM channel 3 Period Interrupt Enable\n" "0: Disable,1: Enable"
bitfld.long 0x00 2. "PWMIE2,PWM channel 2 Period Interrupt Enable\n" "0: Disable,1: Enable"
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bitfld.long 0x00 1. "PWMIE1,PWM channel 1 Period Interrupt Enable\n" "0: Disable,1: Enable"
bitfld.long 0x00 0. "PWMIE0,PWM channel 0 Period Interrupt Enable\n" "0: Disable,1: Enable"
group.long 0x44++0x03
line.long 0x00 "PIIR,PWM Interrupt Indication Register"
bitfld.long 0x00 3. "PWMIF3,PWM channel 3 Period Interrupt Status\nThis bit is set by hardware when PWM3 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) if PWM3 interrupt enable bit (PWMIE3) is 1 software can write 1 to clear this bit.." "0,1"
bitfld.long 0x00 2. "PWMIF2,PWM channel 2 Period Interrupt Status\nThis bit is set by hardware when PWM2 counter reaches the requirement of interrupt (depend on INT23TYPE bit of PIER register) if PWM2 interrupt enable bit (PWMIE2) is 1 software can write 1 to clear this bit.." "0,1"
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bitfld.long 0x00 1. "PWMIF1,PWM channel 1 Period Interrupt Status\nThis bit is set by hardware when PWM1 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) if PWM1 interrupt enable bit (PWMIE1) is 1 software can write 1 to clear this bit.." "0,1"
bitfld.long 0x00 0. "PWMIF0,PWM channel 0 Period Interrupt Status\nThis bit is set by hardware when PWM0 counter reaches the requirement of interrupt (depend on INT01TYPE bit of PIER register) if PWM0 interrupt enable bit (PWMIE0) is 1 software can write 1 to clear this bit.." "0,1"
group.long 0x50++0x03
line.long 0x00 "CCR0,PWM Capture Control Register 0"
bitfld.long 0x00 23. "CFLRI1,CFLR1 Latched Indicator Bit\nWhen PWM input channel 1 has a falling transition CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it" "0,1"
bitfld.long 0x00 22. "CRLRI1,CRLR1 Latched Indicator Bit\nWhen PWM input channel 1 has a rising transition CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it" "0,1"
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bitfld.long 0x00 20. "CAPIF1,Capture1 Interrupt Indication Flag\n" "0,1"
bitfld.long 0x00 19. "CAPCH1EN,Capture PWM Channel 1 transition Enable/Disable\nWhen Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable Capture does not update CRLR and CFLR and disable PWM channel 1 Interrupt" "0: Disable capture function on PWM channel 1,1: Enable capture function on PWM channel 1"
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bitfld.long 0x00 18. "CFL_IE1,PWM Channel 1 Falling Latch Interrupt Enable\nWhen Enable if Capture detects PWM channel 1 has falling transition Capture issues an Interrupt" "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
bitfld.long 0x00 17. "CRL_IE1,PWM Channel 1 Rising Latch Interrupt Enable\nWhen Enable if Capture detects PWM channel 1 has rising transition Capture issues an Interrupt" "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
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bitfld.long 0x00 16. "INV1,PWM Channel 1 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x00 7. "CFLRI0,CFLR0 Latched Indicator Bit\nWhen PWM input channel 0 has a falling transition CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it" "0,1"
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bitfld.long 0x00 6. "CRLRI0,CRLR0 Latched Indicator Bit\nWhen PWM input channel 0 has a rising transition CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware" "0,1"
bitfld.long 0x00 4. "CAPIF0,Capture0 Interrupt Indication Flag\n" "0,1"
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bitfld.long 0x00 3. "CAPCH0EN,Capture Channel 0 transition Enable/Disable\nWhen Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable Capture does not update CRLR and CFLR and disable PWM channel 0 Interrupt" "0: Disable capture function on PWM channel 0,1: Enable capture function on PWM channel 0"
bitfld.long 0x00 2. "CFL_IE0,PWM Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enable if Capture detects PWM channel 0 has falling transition Capture issues an Interrupt" "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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bitfld.long 0x00 1. "CRL_IE0,PWM Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enable if Capture detects PWM channel 0 has rising transition Capture issues an Interrupt" "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
bitfld.long 0x00 0. "INV0,PWM Channel 0 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
group.long 0x54++0x03
line.long 0x00 "CCR2,PWM Capture Control Register 2"
bitfld.long 0x00 23. "CFLRI3,CFLR3 Latched Indicator Bit\nWhen PWM input channel 3 has a falling transition CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 22. "CRLRI3,CRLR3 Latched Indicator Bit\nWhen PWM input channel 3 has a rising transition CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 20. "CAPIF3,Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 19. "CAPCH3EN,Capture Channel 3 transition Enable/Disable\nWhen Enable Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable Capture does not update CRLR and CFLR and disable PWM channel 3 Interrupt" "0: Disable capture function on PWM channel 3,1: Enable capture function on PWM channel 3"
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bitfld.long 0x00 18. "CFL_IE3,PWM Channel 3 Falling Latch Interrupt Enable\nWhen Enable if Capture detects PWM channel 3 has falling transition Capture issues an Interrupt" "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
bitfld.long 0x00 17. "CRL_IE3,PWM Channel 3 Rising Latch Interrupt Enable\nWhen Enable if Capture detects PWM channel 3 has rising transition Capture issues an Interrupt" "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
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bitfld.long 0x00 16. "INV3,PWM Channel 3 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x00 7. "CFLRI2,CFLR2 Latched Indicator Bit\nWhen PWM input channel 2 has a falling transition CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 6. "CRLRI2,CRLR2 Latched Indicator Bit\nWhen PWM input channel 2 has a rising transition CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero" "0,1"
bitfld.long 0x00 4. "CAPIF2,Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 3. "CAPCH2EN,Capture Channel 2 transition Enable/Disable\nWhen Enable Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable Capture does not update CRLR and CFLR and disable PWM channel 2 Interrupt" "0: Disable capture function on PWM channel 2,1: Enable capture function on PWM channel 2"
bitfld.long 0x00 2. "CFL_IE2,PWM Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enable if Capture detects PWM channel 2 has falling transition Capture issues an Interrupt" "0: Disable falling latch interrupt,1: Enable falling latch interrupt"
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bitfld.long 0x00 1. "CRL_IE2,PWM Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enable if Capture detects PWM channel 2 has rising transition Capture issues an Interrupt" "0: Disable rising latch interrupt,1: Enable rising latch interrupt"
bitfld.long 0x00 0. "INV2,PWM Channel 2 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
rgroup.long 0x58++0x03
line.long 0x00 "CRLR0,PWM Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
rgroup.long 0x5C++0x03
line.long 0x00 "CFLR0,PWM Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x60++0x03
line.long 0x00 "CRLR1,PWM Capture Rising Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x64++0x03
line.long 0x00 "CFLR1,PWM Capture Falling Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x68++0x03
line.long 0x00 "CRLR2,PWM Capture Rising Latch Register (Channel 2)"
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x6C++0x03
line.long 0x00 "CFLR2,PWM Capture Falling Latch Register (Channel 2)"
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x70++0x03
line.long 0x00 "CRLR3,PWM Capture Rising Latch Register (Channel 3)"
hexmask.long.word 0x00 0.--15. 1. "CRLRx,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x74++0x03
line.long 0x00 "CFLR3,PWM Capture Falling Latch Register (Channel 3)"
hexmask.long.word 0x00 0.--15. 1. "CFLRx,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x78++0x03
line.long 0x00 "CAPENR,PWM Capture Input 0~3 Enable Register"
bitfld.long 0x00 0.--3. "CAPENR,Capture Input Enable Register\nThere are four capture inputs from pad" "0: OFF (PWMx multi-function pin input does not..,1: ON (PWMx multi-function pin input will affect..,?..."
group.long 0x7C++0x03
line.long 0x00 "POE,PWM Output Enable Register for channel 0~3"
bitfld.long 0x00 3. "PWM3,PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 3 output to pin,1: Enable PWM channel 3 output to pin"
bitfld.long 0x00 2. "PWM2,PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 2 output to pin,1: Enable PWM channel 2 output to pin"
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bitfld.long 0x00 1. "PWM1,PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 1 output to pin,1: Enable PWM channel 1 output to pin"
bitfld.long 0x00 0. "PWM0,PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function" "0: Disable PWM channel 0 output to pin,1: Enable PWM channel 0 output to pin"
group.long 0x80++0x03
line.long 0x00 "TCON,PWM Trigger Control Register for Channel 0~3"
bitfld.long 0x00 11. "PWM3DTEN,Channel 3 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function"
bitfld.long 0x00 10. "PWM2DTEN,Channel 2 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function"
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bitfld.long 0x00 9. "PWM1DTEN,Channel 1 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function"
bitfld.long 0x00 8. "PWM0DTEN,Channel 0 PWM Duty Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to match CMR.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function"
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bitfld.long 0x00 3. "PWM3TEN,Channel 3 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 3 trigger ADC function,1: Enable PWM channel 3 trigger ADC function"
bitfld.long 0x00 2. "PWM2TEN,Channel 2 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 2 trigger ADC function,1: Enable PWM channel 2 trigger ADC function"
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bitfld.long 0x00 1. "PWM1TEN,Channel 1 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 1 trigger ADC function,1: Enable PWM channel 1 trigger ADC function"
bitfld.long 0x00 0. "PWM0TEN,Channel 0 PWM Period Trigger ADC Enable Register\nAs PWM operating at edge-aligned type enable this bit can make PWM trigger ADC to start conversion when PWM counter down count to underflow.\nAs PWM operating at center-aligned type enable this.." "0: Disable PWM channel 0 trigger ADC function,1: Enable PWM channel 0 trigger ADC function"
group.long 0x84++0x03
line.long 0x00 "TSTATUS,PWM Trigger Status Register"
bitfld.long 0x00 3. "PWM3TF,PWM Channel 3 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM3 trigger ADC condition matched" "0,1"
bitfld.long 0x00 2. "PWM2TF,PWM Channel 2 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM2 trigger ADC condition matched" "0,1"
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bitfld.long 0x00 1. "PWM1TF,PWM Channel 1 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM1 trigger ADC condition matched" "0,1"
bitfld.long 0x00 0. "PWM0TF,PWM Channel 0 Trigger ADC Flag\nThis bit is set to 1 by hardware when PWM0 trigger ADC condition matched" "0,1"
group.long 0xA0++0x03
line.long 0x00 "CAPIC,PWM Capture Interrupt Control Register"
bitfld.long 0x00 0. "CIENS,PWM Capture interrupt exception Number select\nThis bit is to enable PWM0-3 capture interrupts have independent interrupt exception number" "0: Disable PWM0-3 independent capture interrupt..,1: Enable PWM0-3 independent capture interrupt.."
tree.end
tree "SCS (SCS Register Map)"
base ad:0xE000E000
group.long 0x10++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
bitfld.long 0x00 2. "CLKSRC," "0: Clock source is optional refer to STCLK_S,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT," "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x00 0. "ENABLE," "0: The counter is disabled,1: The counter will operate in a multi-shot manner"
group.long 0x14++0x03
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the Current Value register when the counter reaches 0"
group.long 0x18++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current counter value"
group.long 0x100++0x03
line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-Enable Control Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Enable one or more interrupts within a group of 32"
group.long 0x180++0x03
line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-Enable Control Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Disable one or more interrupts within a group of 32"
group.long 0x200++0x03
line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-Pending Control Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Writing 1 to a bit pends the associated interrupt under software control"
group.long 0x280++0x03
line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-Pending Control Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Writing 1 to a bit un-pends the associated interrupt under software control"
group.long 0x400++0x03
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_3,Priority of IRQ3\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_2,Priority of IRQ2\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_1,Priority of IRQ1\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_0,Priority of IRQ0\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x404++0x03
line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_7,Priority of IRQ7\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_6,Priority of IRQ6\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_5,Priority of IRQ5\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_4,Priority of IRQ4\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x408++0x03
line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_11,Priority of IRQ11\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_10,Priority of IRQ10\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_9,Priority of IRQ9\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_8,Priority of IRQ8\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x40C++0x03
line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_15,Priority of IRQ15\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of IRQ14\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_13,Priority of IRQ13\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_12,Priority of IRQ12\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x410++0x03
line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_19,Priority of IRQ19\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_18,Priority of IRQ18\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_17,Priority of IRQ17\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_16,Priority of IRQ16\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x414++0x03
line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_23,Priority of IRQ23\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_22,Priority of IRQ22\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_21,Priority of IRQ21\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_20,Priority of IRQ20\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x418++0x03
line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_27,Priority of IRQ27\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_26,Priority of IRQ26\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_25,Priority of IRQ25\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_24,Priority of IRQ24\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
group.long 0x41C++0x03
line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x00 30.--31. "PRI_31,Priority of IRQ31\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_30,Priority of IRQ30\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_29,Priority of IRQ29\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_28,Priority of IRQ28\n 0 denotes the highest priority and 3 denotes lowest priority" "0,1,2,3"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPUID Base Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,"
bitfld.long 0x00 16.--19. "PART,Reads as 0xC for ARMv6-M parts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Reads as 0xC20"
bitfld.long 0x00 0.--3. "REVISION,Reads as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: no effect\nNMI exception is not pending,1: changes NMI exception state to pending.\nNMI.."
bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending" "0: no effect\nPendSV exception is not pending,1: changes PendSV exception state to.."
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bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit.\nWrite:\nThis is a write only bit" "0: no effect,1: removes the pending state from the PendSV.."
bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit.\nWrite:\n" "0: no effect\nSysTick exception is not pending,1: changes SysTick exception state to.."
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bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit.\nWrite:\nThis is a write only bit" "0: no effect,1: removes the pending state from the SysTick.."
bitfld.long 0x00 23. "ISRPREEMPT,If set a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit" "0,1"
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bitfld.long 0x00 22. "ISRPENDING,Interrupt pending flag excluding NMI and Faults:\nThis is a read only bit" "0: interrupt not pending,1: interrupt pending"
bitfld.long 0x00 12.--17. "VECTPENDING,Indicates the exception number of the highest priority pending enabled exception:\n" "0: no pending exceptions,?..."
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bitfld.long 0x00 0.--5. "VECTACTIVE,Contains the active exception number\n" "0: Thread mode,?..."
group.long 0xD0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,When write this register this field should be 0x05FA otherwise the write action will be unpredictable"
bitfld.long 0x00 2. "SYSRESETREQ,Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence" "0,1"
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bitfld.long 0x00 1. "VECTCLRACTIVE,Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the.." "0,1"
group.long 0xD10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit:\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: only enabled interrupts or events can wake-up..,1: enabled events and all interrupts including.."
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode:\n" "0: sleep,1: deep sleep"
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bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: do not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an.."
group.long 0xD1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler" "0,1,2,3"
group.long 0xD20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler" "0,1,2,3"
tree.end
tree "SPI (SPI Register Map)"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "SPI_CNTRL,Control and Status Register"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[27].\n" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is full"
rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].\n" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is.."
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rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].\n" "0: Indicates that the receive FIOF buffer is not..,1: Indicates that the receive FIFO buffer is full"
rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty"
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bitfld.long 0x00 21. "FIFO,FIFO Mode\nNote:\nBefore enabling FIFO mode the other related settings should be set in advance.\n In master mode if the FIFO mode is enabled the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth FIFO" "0: Disable FIFO Mode,1: Enable FIFO Mode"
bitfld.long 0x00 19. "REORDER,Byte Reorder Function\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16 24 and 32 bits" "0: Disable the byte reorder function,1: Enable byte reorder function"
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bitfld.long 0x00 18. "SLAVE,Slave Mode Enable Bit\n" "0: Master mode,1: Slave mode"
bitfld.long 0x00 17. "IE,SPI Unit Transfer Interrupt Enable Bit\n" "0: Disable SPI unit transfer interrupt,1: Enable SPI unit transfer interrupt"
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bitfld.long 0x00 16. "IF,SPI Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: It indicates that the transfer does not..,1: It indicates that the SPI controller has.."
bitfld.long 0x00 12.--15. "SP_CYCLE,Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "CLKP,Clock Polarity\n" "0: SPICLK idle low,1: SPICLK idle high"
bitfld.long 0x00 10. "LSB,LSB First\n" "0: The MSB which bit of SPI_TX0/SPI_RX0 register..,1: The LSB bit 0 of the SPI_TX0 register is sent.."
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bitfld.long 0x00 3.--7. "TX_BIT_LEN,Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 2. "TX_NEG,Transmit on Negative Edge\n" "0: The transmitted data output signal is changed..,1: The transmitted data output signal is changed.."
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bitfld.long 0x00 1. "RX_NEG,Receive on Negative Edge\n" "0: The received data input signal is latched on..,1: The received data input signal is latched on.."
bitfld.long 0x00 0. "GO_BUSY,SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled during the data transfer this bit keeps the value of 1" "0: Writing 0 to this bit to stop data transfer..,1: In master mode writing 1 to this bit to start.."
group.long 0x04++0x03
line.long 0x00 "SPI_DIVIDER,Clock Divider Register"
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the SPI engine clock and its SPI clock"
group.long 0x08++0x03
line.long 0x00 "SPI_SSR,Slave Select Register"
bitfld.long 0x00 5. "LTRIG_FLAG,Level Trigger Accomplish Flag\nIn slave mode this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only" "0: The transferred bit length of one transaction..,1: The transferred bit length meets the.."
bitfld.long 0x00 4. "SS_LTRIG,Slave Select Level Trigger Enable Bit (Slave only)\n" "0: The slave select signal is edge-trigger,1: The slave select signal will be level-trigger"
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable Bit (Master only)\n" "0: If this bit is cleared slave select signal..,1: If this bit is set SPISS signal will be.."
bitfld.long 0x00 2. "SS_LVL,Slave Select Active Level\nIt defines the active status of slave select signal (SPISS).\n" "0: The slave select signal SPISS is active on..,1: The slave select signal SPISS is active on.."
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bitfld.long 0x00 0. "SSR,Slave Select Control Bits (Master only)\nIf AUTOSS bit is cleared writing 1 to this field sets the SPISS line to active state and writing 0 sets the line back to inactive state.\nIf AUTOSS bit is set writing 0 to this field will keep the SPISS line.." "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "SPI_RX0,Data Receive Register 0"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe data receive register holds the datum received from SPI data input pin"
wgroup.long 0x20++0x03
line.long 0x00 "SPI_TX0,Data Transmit Register 0"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer"
group.long 0x3C++0x03
line.long 0x00 "SPI_CNTRL2,Control and Status Register 2"
bitfld.long 0x00 31. "BCn,SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details" "0: Backward compatible clock configuration,1: The clock configuration is not backward.."
bitfld.long 0x00 16. "SS_INT_OPT,Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n" "0: As the slave select signal goes to inactive..,1: As the slave select signal goes to inactive.."
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bitfld.long 0x00 11. "SLV_START_INTSTS,Slave 3-Wire Mode Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode.\n" "0: It indicates that the SPI transfer is not..,1: It indicates that the transfer has started in.."
bitfld.long 0x00 10. "SSTA_INTEN,Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode" "0: Disable the transfer start interrupt,1: Enable the transaction start interrupt"
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bitfld.long 0x00 9. "SLV_ABORT,Slave 3-Wire Mode Abort Control Bit\nIn normal operation there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial.." "0,1"
bitfld.long 0x00 8. "NOSLVSEL,Slave 3-Wire Mode Enable Bit\nThis is used to ignore the slave select signal in slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
group.long 0x40++0x03
line.long 0x00 "SPI_FIFO_CTL,SPI FIFO Control Register"
bitfld.long 0x00 28.--29. "TX_THRESHOLD,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting the TX_INTSTS bit will be set to 1 else the TX_INTSTS bit will be cleared to 0" "0,1,2,3"
bitfld.long 0x00 24.--25. "RX_THRESHOLD,Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting the RX_INTSTS bit will be set to 1 else the RX_INTSTS bit will be cleared to 0" "0,1,2,3"
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bitfld.long 0x00 21. "TIMEOUT_INTEN,Receive FIFO Time-out Interrupt Enable\n" "0: Disable time-out interrupt,1: Enable time-out interrupt"
bitfld.long 0x00 6. "RXOV_INTEN,Receive FIFO Overrun Interrupt Enable\n" "0: Disable Receive FIFO overrun interrupt,1: Enable Receive FIFO overrun interrupt"
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bitfld.long 0x00 3. "TX_INTEN,Transmit Threshold Interrupt Enable\n" "0: Disable transmit threshold interrupt,1: Enable transmit threshold interrupt"
bitfld.long 0x00 2. "RX_INTEN,Receive Threshold Interrupt Enable\n" "0: Disable receive threshold interrupt,1: Enable receive threshold interrupt"
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bitfld.long 0x00 1. "TX_CLR,Clear Transmit FIFO Buffer\n" "0: No effect,1: Clear transmit FIFO buffer"
bitfld.long 0x00 0. "RX_CLR,Clear Receive FIFO Buffer\n" "0: No effect,1: Clear receive FIFO buffer"
group.long 0x44++0x03
line.long 0x00 "SPI_STATUS,SPI Status Register"
rbitfld.long 0x00 28.--31. "TX_FIFO_COUNT,Transmit FIFO Data Count (read only)\nIndicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "TX_FULL,Transmit FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[27].\n" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is full"
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rbitfld.long 0x00 26. "TX_EMPTY,Transmit FIFO Buffer Empty Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[26].\n" "0: Indicates that the transmit FIFO buffer is..,1: Indicates that the transmit FIFO buffer is.."
rbitfld.long 0x00 25. "RX_FULL,Receive FIFO Buffer Full Indicator (read only) \nIt's a mutual mirror bit of SPI_CNTRL[25].\n" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is full"
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rbitfld.long 0x00 24. "RX_EMPTY,Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].\n" "0: Indicates that the receive FIFO buffer is not..,1: Indicates that the receive FIFO buffer is empty"
bitfld.long 0x00 20. "TIMEOUT,Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: It indicates that the receive FIFO buffer is.."
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bitfld.long 0x00 16. "IF,SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself" "0: It indicates that the transfer does not..,1: It indicates that the SPI controller has.."
rbitfld.long 0x00 12.--15. "RX_FIFO_COUNT,Receive FIFO Data Count (read only)\nIndicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 11. "SLV_START_INTSTS,Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode" "0: It indicates that the transfer is not started,1: It indicates that the transfer has started in.."
rbitfld.long 0x00 4. "TX_INTSTS,Transmit FIFO Threshold Interrupt Status (read only)\n" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.."
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bitfld.long 0x00 2. "RX_OVERRUN,Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself" "0,1"
rbitfld.long 0x00 0. "RX_INTSTS,Receive FIFO Threshold Interrupt Status (read only)\n" "0: It indicates that the valid data count within..,1: It indicates that the valid data count within.."
tree.end
tree "TMR (TMR Register Map)"
tree "TMR01"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "TCSR0,Timer0 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR" "0: Disable timer Interrupt,1: Enable timer Interrupt"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x00 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Reset Timer's prescale counter internal.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is in active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is the counter mode enable bit" "0: Disable counter mode,1: Enable counter mode"
bitfld.long 0x00 23. "WAKE_EN,Wake up Enable\nWhen WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable"
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bitfld.long 0x00 21. "TOGGLE_PIN,Toggle Mode Output PIN\n" "0: Toggle mode output to Tx (Timer Even,1: Toggle mode output to TxEX((Timer External Pin)"
bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable\nWhen users update TCMP TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TIMERx_CH0 will be in counter mode and counting with external clock source or event" "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR0,Timer0 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP"
group.long 0x08++0x03
line.long 0x00 "TISR0,Timer0 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP)" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR0,Timer0 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP0,Timer0 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP"
group.long 0x14++0x03
line.long 0x00 "TEXCON0,Timer0 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter pin De-bounce enable bit\nIf this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
bitfld.long 0x00 6. "TEXDB,Timer External Capture pin De-bounce enable bit\nIf this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
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bitfld.long 0x00 5. "TEXIEN,Timer External interrupt Enable Bit\n" "0: Disable timer External Interrupt,1: Enable timer External Interrupt"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select\n" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.."
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bitfld.long 0x00 3. "TEXEN,Timer External Pin Enable" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,2: either 1 to 0 or 0 to 1 transition on TEX..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
group.long 0x18++0x03
line.long 0x00 "TEXISR0,Timer0 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred" "0,1"
group.long 0x20++0x03
line.long 0x00 "TCSR1,Timer1 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR" "0: Disable timer Interrupt,1: Enable timer Interrupt"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x00 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Reset Timer's prescale counter internal.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is in active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is the counter mode enable bit" "0: Disable counter mode,1: Enable counter mode"
bitfld.long 0x00 23. "WAKE_EN,Wake up Enable\nWhen WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable"
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bitfld.long 0x00 21. "TOGGLE_PIN,Toggle Mode Output PIN\n" "0: Toggle mode output to Tx (Timer Even,1: Toggle mode output to TxEX((Timer External Pin)"
bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable\nWhen users update TCMP TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TIMERx_CH0 will be in counter mode and counting with external clock source or event" "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR1,Timer1 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP"
group.long 0x28++0x03
line.long 0x00 "TISR1,Timer1 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "TDR1,Timer1 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1"
group.long 0x30++0x03
line.long 0x00 "TCAP1,Timer1 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP"
group.long 0x34++0x03
line.long 0x00 "TEXCON1,Timer1 external Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter pin De-bounce enable bit\nIf this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
bitfld.long 0x00 6. "TEXDB,Timer External Capture pin De-bounce enable bit\nIf this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
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bitfld.long 0x00 5. "TEXIEN,Timer External interrupt Enable Bit\n" "0: Disable timer External Interrupt,1: Enable timer External Interrupt"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select\n" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.."
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bitfld.long 0x00 3. "TEXEN,Timer External Pin Enable" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,2: either 1 to 0 or 0 to 1 transition on TEX..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
group.long 0x38++0x03
line.long 0x00 "TEXISR1,Timer1 external Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred" "0,1"
tree.end
tree "TMR23"
base ad:0x40110000
group.long 0x00++0x03
line.long 0x00 "TCSR2,Timer2 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR" "0: Disable timer Interrupt,1: Enable timer Interrupt"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x00 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Reset Timer's prescale counter internal.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is in active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is the counter mode enable bit" "0: Disable counter mode,1: Enable counter mode"
bitfld.long 0x00 23. "WAKE_EN,Wake up Enable\nWhen WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable"
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bitfld.long 0x00 21. "TOGGLE_PIN,Toggle Mode Output PIN\n" "0: Toggle mode output to Tx (Timer Even,1: Toggle mode output to TxEX((Timer External Pin)"
bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable\nWhen users update TCMP TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TIMERx_CH0 will be in counter mode and counting with external clock source or event" "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Counter\n"
group.long 0x04++0x03
line.long 0x00 "TCMPR2,Timer2 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP"
group.long 0x08++0x03
line.long 0x00 "TISR2,Timer2 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP)" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "TDR2,Timer2 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1"
rgroup.long 0x10++0x03
line.long 0x00 "TCAP2,Timer2 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP"
group.long 0x14++0x03
line.long 0x00 "TEXCON2,Timer2 External Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter pin De-bounce enable bit\nIf this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
bitfld.long 0x00 6. "TEXDB,Timer External Capture pin De-bounce enable bit\nIf this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
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bitfld.long 0x00 5. "TEXIEN,Timer External interrupt Enable Bit\n" "0: Disable timer External Interrupt,1: Enable timer External Interrupt"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select\n" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.."
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bitfld.long 0x00 3. "TEXEN,Timer External Pin Enable" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,2: either 1 to 0 or 0 to 1 transition on TEX..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
group.long 0x18++0x03
line.long 0x00 "TEXISR2,Timer2 External Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred" "0,1"
group.long 0x20++0x03
line.long 0x00 "TCSR3,Timer3 Control and Status Register"
bitfld.long 0x00 31. "DBGACK_TMR,ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 30. "CEN,Timer Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x00 29. "IE,Interrupt Enable Bit\nIf timer interrupt is enabled the timer asserts its interrupt signal when the associated timer is equal to TCMPR" "0: Disable timer Interrupt,1: Enable timer Interrupt"
bitfld.long 0x00 27.--28. "MODE,Timer Operating Mode\n" "0,1,2,3"
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bitfld.long 0x00 26. "CRST,Timer Reset Bit\nSet this bit will reset the 24-bit up-timer 8-bit pre-scale counter and also force CEN to 0.\n" "0: No effect,1: Reset Timer's prescale counter internal.."
rbitfld.long 0x00 25. "CACT,Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n" "0: Timer is not active,1: Timer is in active"
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bitfld.long 0x00 24. "CTB,Counter Mode Enable Bit \nThis bit is the counter mode enable bit" "0: Disable counter mode,1: Enable counter mode"
bitfld.long 0x00 23. "WAKE_EN,Wake up Enable\nWhen WAKE_EN is set and the TIF is set the timer controller will generator a wake-up trigger event to CPU.\n" "0: Wake-up trigger event disable,1: Wake-up trigger event enable"
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bitfld.long 0x00 21. "TOGGLE_PIN,Toggle Mode Output PIN\n" "0: Toggle mode output to Tx (Timer Even,1: Toggle mode output to TxEX((Timer External Pin)"
bitfld.long 0x00 20. "PERIODIC_SEL,Periodic Mode Behavior Selection Enable\nWhen users update TCMP TDR will be reset to default value" "0: The behavior selection in periodic mode is..,1: The behavior selection in periodic mode is.."
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bitfld.long 0x00 19. "INTR_TRG_EN,Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled the TIMERx_CH0 will be in counter mode and counting with external clock source or event" "0: The inter-timer trigger mode is disabled,1: The inter-timer trigger mode is enabled"
bitfld.long 0x00 16. "TDR_EN,Data Load Enable\nWhen TDR_EN is set TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n" "0: Timer Data Register update disable,1: Timer Data Register update enable"
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hexmask.long.byte 0x00 0.--7. 1. "PRESCALE,Pre-scale Counter\n"
group.long 0x24++0x03
line.long 0x00 "TCMPR3,Timer3 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCMP,Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode the 24-bit up-timer will count continuously if software writes a new value into TCMP"
group.long 0x28++0x03
line.long 0x00 "TISR3,Timer3 Interrupt Status Register"
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP)" "0,1"
group.long 0x2C++0x03
line.long 0x00 "TDR3,Timer3 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TDR,Timer Data Register\nUser can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1"
group.long 0x30++0x03
line.long 0x00 "TCAP3,Timer3 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TCAP,Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set RSTCAPSEL (TTXCON[4]) is 0 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred the internal 24-bit up-timer value will be loaded into TCAP"
group.long 0x34++0x03
line.long 0x00 "TEXCON3,Timer3 external Control Register"
bitfld.long 0x00 7. "TCDB,Timer Counter pin De-bounce enable bit\nIf this bit is enabled the edge of T0~T3 pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
bitfld.long 0x00 6. "TEXDB,Timer External Capture pin De-bounce enable bit\nIf this bit is enabled the edge of T0EX~T3EX pin is detected with de-bounce circuit" "0: Disable De-bounce,1: Enable De-bounce"
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bitfld.long 0x00 5. "TEXIEN,Timer External interrupt Enable Bit\n" "0: Disable timer External Interrupt,1: Enable timer External Interrupt"
bitfld.long 0x00 4. "RSTCAPSEL,Timer External Reset Counter / Capture mode select\n" "0: TEX transition is using as the timer capture..,1: TEX transition is using as the timer counter.."
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bitfld.long 0x00 3. "TEXEN,Timer External Pin Enable" "0: The TEX pin will be ignored,1: The transition detected on the TEX pin will.."
bitfld.long 0x00 1.--2. "TEX_EDGE,Timer External Pin Edge Detect\n" "0: a 1 to 0 transition on TEX will be detected,1: a 0 to 1 transition on TEX will be detected,2: either 1 to 0 or 0 to 1 transition on TEX..,3: Reserved"
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bitfld.long 0x00 0. "TX_PHASE,Timer External Count Phase \nThis bit indicates the external count pin phase.\n" "0: A falling edge of external count pin will be..,1: A rising edge of external count pin will be.."
group.long 0x38++0x03
line.long 0x00 "TEXISR3,Timer3 external Interrupt Status Register"
bitfld.long 0x00 0. "TEXIF,Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1 and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred" "0,1"
tree.end
tree.end
tree "UART (Universal Asynchronous Receiver/Transmitter)"
base ad:0x40050000
rgroup.long 0x00++0x03
line.long 0x00 "UA_RBR,UART Receive Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "RBR,Receive Buffer Register (Read Only)\nBy reading this register the UART will return an 8-bit data received from RX pin (LSB first)"
wgroup.long 0x00++0x03
line.long 0x00 "UA_THR,UART Transmit Holding Register"
hexmask.long.byte 0x00 0.--7. 1. "THR,Transmit Holding Register\nBy writing to this register the UART will send out an 8-bit data through the TX pin (LSB first)"
group.long 0x04++0x03
line.long 0x00 "UA_IER,UART Interrupt Enable Register"
bitfld.long 0x00 13. "AUTO_CTS_EN,CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted)" "0: Disable CTS auto flow control,1: Enable CTS auto flow control"
bitfld.long 0x00 12. "AUTO_RTS_EN,RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV] the UART will de-assert RTS signal" "0: Disable RTS auto flow control,1: Enable RTS auto flow control"
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bitfld.long 0x00 11. "TIME_OUT_EN,Time Out Counter Enable\n" "0: Disable Time-out counter,1: Enable Time-out counter"
bitfld.long 0x00 8. "LIN_RX_BRK_IEN,LIN RX Break Field Detected Interrupt Enable\nNote: This field is used for LIN function mode" "0: Mask off Lin bus RX break filed interrupt,1: Enable Lin bus RX break filed interrupt"
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bitfld.long 0x00 6. "WAKE_EN,Wake Up CPU Function Enable \n" "0: Disable UART wake up CPU function,1: Enable wake up function when the system is in.."
bitfld.long 0x00 5. "BUF_ERR_IEN,Buffer Error Interrupt Enable\n" "0: Mask off INT_BUF_ERR,1: Enable INT_BUF_ERR"
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bitfld.long 0x00 4. "RTO_IEN,RX Time Out Interrupt Enable\n" "0: Mask off INT_TOUT,1: Enable INT_TOUT"
bitfld.long 0x00 3. "MODEM_IEN,Modem Status Interrupt Enable\n" "0: Mask off INT_MODEM,1: Enable INT_MODEM"
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bitfld.long 0x00 2. "RLS_IEN,Receive Line Status Interrupt Enable \n" "0: Mask off INT_RLS,1: Enable INT_RLS"
bitfld.long 0x00 1. "THRE_IEN,Transmit Holding Register Empty Interrupt Enable\n" "0: Mask off INT_THRE,1: Enable INT_THRE"
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bitfld.long 0x00 0. "RDA_IEN,Receive Data Available Interrupt Enable.\n" "0: Mask off INT_RDA,1: Enable INT_RDA"
group.long 0x08++0x03
line.long 0x00 "UA_FCR,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTS_TRI_LEV,RTS Trigger Level for Auto-flow Control Use\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8. "RX_DIS,Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode" "0: Enable Receiver,1: Disable Receiver"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt (INT_RDA) Trigger Level\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 2. "TFR,TX Field Software Reset\nWhen TX_RST is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles" "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the TX.."
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bitfld.long 0x00 1. "RFR,RX Field Software Reset\nWhen RX_RST is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles" "0: Writing 0 to this bit has no effect,1: Writing 1 to this bit will reset the RX.."
group.long 0x0C++0x03
line.long 0x00 "UA_LCR,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control Bit\nWhen this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0,1"
bitfld.long 0x00 5. "SPE,Stick Parity Enable\n" "0: Disable stick parity,1: When bits PBE EPE and SPE are set the parity.."
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bitfld.long 0x00 4. "EPE,Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set" "0: Odd number of logic 1's are transmitted or..,1: Even number of logic 1's are transmitted or.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable\n" "0: Parity bit is not generated (transmit data)..,1: Parity bit is generated or checked between.."
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bitfld.long 0x00 2. "NSB,Number of STOP bit \n" "0: 1 STOP bit,1: 2 STOP bits (1.5 STOP bits if WLS[1:0]=00)"
bitfld.long 0x00 0.--1. "WLS,Word Length Select\n" "0,1,2,3"
group.long 0x10++0x03
line.long 0x00 "UA_MCR,UART Modem Control Register"
rbitfld.long 0x00 13. "RTS_ST,RTS Pin State (Read Only)\nThis bit is the output pin status of RTS" "0,1"
bitfld.long 0x00 9. "LEV_RTS,RTS Trigger Level\nThis bit can change the RTS trigger level.\n" "0: low level triggered,1: high level triggered"
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bitfld.long 0x00 1. "RTS,RTS (Request-To-Send) Signal\n" "0: Drive RTS pin to logic 1 (If the LEV_RTS set..,1: Drive RTS pin to logic 0 (If the LEV_RTS set.."
group.long 0x14++0x03
line.long 0x00 "UA_MSR,UART Modem Status Register"
bitfld.long 0x00 8. "LEV_CTS,CTS Trigger Level\nThis bit can change the CTS trigger level.\n" "0: low level triggered,1: high level triggered"
rbitfld.long 0x00 4. "CTS_ST,CTS Pin Status (Read Only)\nThis bit is the pin status of CTS when UART clock is enabled and CTS multi-function port is selected" "0,1"
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rbitfld.long 0x00 0. "DCTSF,Detect CTS State Change Flag (Read Only)\nThis bit is set whenever CTS input has change state and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nSoftware can write 1 to clear this bit to zero" "0,1"
group.long 0x18++0x03
line.long 0x00 "UA_FSR,UART FIFO Status Register"
rbitfld.long 0x00 28. "TE_FLAG,Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not.." "0,1"
rbitfld.long 0x00 24. "TX_OVER_IF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full an additional write to UA_THR will cause this bit to logic 1" "0,1"
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rbitfld.long 0x00 23. "TX_FULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to 16 otherwise is cleared by hardware" "0,1"
rbitfld.long 0x00 22. "TX_EMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0,1"
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rbitfld.long 0x00 16.--21. "TX_POINTER,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RX_FULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RX_POINTER is equal to 16 otherwise is cleared by hardware" "0,1"
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rbitfld.long 0x00 14. "RX_EMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0,1"
rbitfld.long 0x00 8.--13. "RX_POINTER,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0,1"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as a logic 0) and is reset whenever the CPU writes.." "0,1"
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rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only but can be cleared by writing '1' to.." "0,1"
rbitfld.long 0x00 3. "RS485_ADD_DETF,RS-485 Address Byte Detection Flag (Read Only)\nNote: This field is used for RS-485 function mode.\nNote: This bit is read only but can be cleared by writing '1' to it" "0,1"
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bitfld.long 0x00 0. "RX_OVER_IF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size 16 bytes this bit will be set.\nNote: This bit is cleared by writing 1 to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UA_ISR,UART Interrupt Status Register"
rbitfld.long 0x00 15. "LIN_RX_BREAK_INT,LIN Bus RX Break Field Detected Interrupt Indicator (Read Only)\nThis bit is set if LIN_RX_BRK_IEN and LIN_RX_BREAK_IF are both set to 1.\n" "0: No LIN RX Break interrupt is generated,1: The LIN RX Break interrupt is generated"
rbitfld.long 0x00 13. "BUF_ERR_INT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n" "0: No buffer error interrupt is generated,1: The buffer error interrupt is generated"
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rbitfld.long 0x00 12. "TOUT_INT,Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN and TOUT_IF are both set to 1.\n" "0: No Tout interrupt is generated,1: The Tout interrupt is generated"
rbitfld.long 0x00 11. "MODEM_INT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN and MODEM_IF are both set to 1.\n" "0: No Modem interrupt is generated,1: The Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLS_INT,Receive Line Status Interrupt Indicator (Read Only)" "0: No RLS interrupt is generated,1: The RLS interrupt is generated"
rbitfld.long 0x00 9. "THRE_INT,Transmit Holding Register Empty Interrupt Indicator (Read Only).\nThis bit is set if THRE_IEN and THRE_IF are both set to 1.\n" "0: No THRE interrupt is generated,1: The THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDA_INT,Receive Data Available Interrupt Indicator (Read Only).\nThis bit is set if RDA_IEN and RDA_IF are both set to 1.\n" "0: No RDA interrupt is generated,1: The RDA interrupt is generated"
rbitfld.long 0x00 7. "LIN_RX_BREAK_IF,LIN Bus RX Break Field Detected Flag (Read Only)\nThis bit is set when RX received LIN Break Field" "0,1"
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rbitfld.long 0x00 5. "BUF_ERR_IF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows or Break Interrupt Flag or Parity Error Flag or Frame Error Flag (TX_OVER_IF or RX_OVER_IF or BIF or PEF or FEF ) is set" "0,1"
rbitfld.long 0x00 4. "TOUT_IF,Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC" "0,1"
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rbitfld.long 0x00 3. "MODEM_IF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF" "0,1"
rbitfld.long 0x00 2. "RLS_IF,Receive Line Interrupt Flag (Read Only).\nThis bit is set when the RX receive data have parity error framing error or break error (at least one of 3 bits BIF FEF and PEF is set)" "0,1"
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rbitfld.long 0x00 1. "THRE_IF,Transmit Holding Register Empty Interrupt Flag (Read Only)" "0,1"
rbitfld.long 0x00 0. "RDA_IF,Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set" "0,1"
group.long 0x20++0x03
line.long 0x00 "UA_TOR,UART Time Out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time Out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UA_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "DIV_X_EN,Divider X Enable\nRefer to the table below for more information.\nNote: When in IrDA mode this bit must disable" "0: Disable divider X (the equation of M = 16),1: Enable divider X (the equation of M = X+1 but.."
bitfld.long 0x00 28. "DIV_X_ONE,Divider X equal 1\nRefer to the Table 6.114 below for more information" "0: Divider M = X (the equation of M = X+1 but..,1: Divider M = 1 (the equation of M = 1 but BRD.."
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bitfld.long 0x00 24.--27. "DIVIDER_X,Divider X\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicated the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UA_IRCR,UART IrDA Control Register"
bitfld.long 0x00 6. "INV_RX,INV_RX\n" "0: No inversion,1: Inverse RX input signal"
bitfld.long 0x00 5. "INV_TX,INV_TX\n" "0: No inversion,1: Inverse TX output signal"
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bitfld.long 0x00 1. "TX_SELECT,TX_SELECT\n" "0: Enable IrDA receiver,1: Enable IrDA transmitter"
group.long 0x2C++0x03
line.long 0x00 "UA_ALT_CSR,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDR_MATCH,Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 15. "RS485_ADD_EN,RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode" "0: Disable address detection mode,1: Enable address detection mode"
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bitfld.long 0x00 10. "RS485_AUD,RS-485 Auto Direction Mode (AUD)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: Disable RS-485 Auto Direction Operation Mode..,1: Enable RS-485 Auto Direction Operation Mode.."
bitfld.long 0x00 9. "RS485_AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode" "0: Disable RS-485 Auto Address Detection..,1: Enable RS-485 Auto Address Detection.."
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bitfld.long 0x00 8. "RS485_NMM,RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode" "0: Disable RS-485 Normal Multi-drop Operation..,1: Enable RS-485 Normal Multi-drop Operation.."
bitfld.long 0x00 7. "LIN_TX_EN,LIN TX Break Mode Enable\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: Disable LIN TX Break Mode,1: Enable LIN TX Break Mode"
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bitfld.long 0x00 6. "LIN_RX_EN,LIN RX Enable\n" "0: Disable LIN RX mode,1: Enable LIN RX mode"
bitfld.long 0x00 0.--3. "UA_LIN_BKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote: This break field length is UA_LIN_BKFL + 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UA_FUN_SEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUN_SEL,Function Select Enable\n" "0: UART Function,1: Enable LIN Function,2: Enable IrDA Function,3: Enable RS-485 Function"
tree.end
tree "WDT (Watchdog Timer Unit)"
base ad:0x40004000
group.long 0x00++0x03
line.long 0x00 "WTCR,Watchdog Timer Control Register"
bitfld.long 0x00 31. "DBGACK_WDT,ICE debug mode acknowledge Disable (write-protected)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not" "0: ICE debug mode acknowledgement effects..,1: ICE debug mode acknowledgement disabled"
bitfld.long 0x00 8.--10. "WTIS,Watchdog Timer Interval Select (write protection bits)\n" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 7. "WTE,Watchdog Timer Enable (write protection bits)\n" "0: Disable the Watchdog timer (This action will..,1: Enable the Watchdog timer"
bitfld.long 0x00 6. "WTIE,Watchdog Timer Interrupt Enable (write protection bits)\n" "0: Disable the Watchdog timer interrupt,1: Enable the Watchdog timer interrupt"
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bitfld.long 0x00 5. "WTWKF,Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip wakes up from power down mode this bit will be set to high" "0: Watchdog timer does not cause chip wake-up,1: Chip wake-up from idle or power down mode by.."
bitfld.long 0x00 4. "WTWKE,Watchdog Timer Wake-up Function Enable bit (write-protection bit)\nNote: Chip can wake-up by WDT only if WDT clock source select RC10K" "0: Disable Watchdog timer wake-up chip function,1: Enable the Wake-up function that Watchdog.."
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bitfld.long 0x00 3. "WTIF,Watchdog Timer Interrupt Flag\nWhen watchdog timeout the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred" "0: Watchdog timer interrupt did not occur,1: Watchdog timer interrupt occurs"
bitfld.long 0x00 2. "WTRF,Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset the hardware will set this bit" "0: Watchdog timer reset did not occur,1: Watchdog timer reset occurs"
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bitfld.long 0x00 1. "WTRE,Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog timer reset function.\n" "0: Disable Watchdog timer reset function,1: Enable Watchdog timer reset function"
bitfld.long 0x00 0. "WTR,Clear Watchdog Timer (write-protection bit)\nSet this bit will clear the Watchdog timer.\nNote: This bit will be auto cleared by hardware" "0: Writing 0 to this bit has no effect,1: Reset the contents of the Watchdog timer"
tree.end
tree "WWDT (WWDT Register Map)"
base ad:0x40004100
wgroup.long 0x00++0x03
line.long 0x00 "WWDTRLD,Window Watchdog Timer Reload Counter Register"
hexmask.long 0x00 0.--31. 1. "WWDTRLD,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F"
group.long 0x04++0x03
line.long 0x00 "WWDTCR,Window Watchdog Timer Control Register"
bitfld.long 0x00 31. "DBGACK_WWDT,ICE debug mode acknowledge Disable\n" "0: WWDT counter stopped if system is in Debug mode,1: WWDT still counted even system is in Debug mode"
bitfld.long 0x00 16.--21. "WINCMP,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PERIODSEL,WWDT Pre-scale Period Select\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. "WWDTIE,WWDT Interrupt Enable\nSetting this bit to enable the Window Watchdog Timer time-out interrupt function.\n" "0: WWDT time-out interrupt function Disabled if..,1: WWDT time-out interrupt function Enabled if.."
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable\nSet this bit to enable Window Watchdog Timer counter counting.\n" "0: Window Watchdog Timer counter is stopped,1: Window Watchdog Timer counter is starting.."
group.long 0x08++0x03
line.long 0x00 "WWDTSR,Window Watchdog Timer Status Register"
bitfld.long 0x00 1. "WWDTRF,WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during current WWDT counter value larger than WINCMP chip will be reset and this bit is set to 1" "0,1"
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nWhen current WWDT counter value matches to WWCMP this bit is set to 1" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "WWDTCVR,Window Watchdog Timer Counter Value Register"
bitfld.long 0x00 0.--5. "WWDTCVAL,WWDT Counter Value\nThis register reflects the current WWDT counter value and this register is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
tree.end
autoindent.off
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