7586 lines
969 KiB
Plaintext
7586 lines
969 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: M0564 On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2022-03-02 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: SVD generated, based on: M0564AE_v1.svd (Ver. 1.0)
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; @Core: Cortex-M0
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; @Chip: M0564LE4AE, M0564LG4AE, M0564SE4AE, M0564SG4AE, M0564VG4AE
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perm0564.per 14432 2022-03-02 17:06:45Z kwisniewski $
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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tree.end
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width 6.
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tree "Interrupt Priority Registers"
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group.long 0x400++0x1F
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line.long 0x00 "INT0,Interrupt Priority Register"
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bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
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bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
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bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
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bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
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line.long 0x04 "INT1,Interrupt Priority Register"
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bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
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bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
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bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
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bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
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line.long 0x08 "INT2,Interrupt Priority Register"
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bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
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bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
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bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
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bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
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line.long 0x0C "INT3,Interrupt Priority Register"
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bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
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bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
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bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
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bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
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line.long 0x10 "INT4,Interrupt Priority Register"
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bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
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bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
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bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
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bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
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line.long 0x14 "INT5,Interrupt Priority Register"
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bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
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bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
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bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
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bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
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line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
autoindent.on center tree
|
|
tree "ACMP"
|
|
base ad:0x400D0000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register"
|
|
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected"
|
|
bitfld.long 0x00 17. "WLATEN,Window Latch Function Enable Bit" "0: Window Latch Function Disabled,1: Window Latch Function Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs"
|
|
newline
|
|
bitfld.long 0x00 12. "OUTSEL,Comparator Output Selection" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.."
|
|
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP0_P0,1: Input from ACMP0_P1,2: Input from ACMP0_P2,3: Input from ACMP0_P3"
|
|
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP0_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled"
|
|
bitfld.long 0x00 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 0 hysteresis Disabled,1: Comparator 0 hysteresis Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled"
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register"
|
|
bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window compare mode Disabled,1: Window compare mode is Selected"
|
|
bitfld.long 0x00 17. "WLATEN,Window Latch Function Enable Bit" "0: Window Latch function Disabled,1: Window Latch function Enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs"
|
|
newline
|
|
bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.."
|
|
bitfld.long 0x00 8.--9. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF1 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "POSSEL,Comparator Positive Input Selection" "0: Input from ACMP1_P0,1: Input from ACMP1_P1,2: Input from ACMP1_P2,3: Input from ACMP1_P3"
|
|
bitfld.long 0x00 4.--5. "NEGSEL,Comparator Negative Input Selection" "0: ACMP1_N pin,1: Internal comparator reference voltage (CRV),2: Band-gap voltage,3: Ground"
|
|
newline
|
|
bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled"
|
|
bitfld.long 0x00 2. "HYSEN,Comparator Hysteresis Enable Bit" "0: Comparator 1 hysteresis Disabled,1: Comparator 1 hysteresis Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled"
|
|
bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register"
|
|
bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positvie input voltage is outside the..,1: The positive input voltage is in the window"
|
|
bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
newline
|
|
bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred"
|
|
bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1"
|
|
bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output" "0,1"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register"
|
|
bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD is selected as CRV voltage source,1: The reference voltage defined by SYS_VREFCTL.."
|
|
bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "ADC"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC_ADDR0,ADC Data Register 0"
|
|
bitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC_ADDR1,ADC Data Register 1"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC_ADDR2,ADC Data Register 2"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC_ADDR3,ADC Data Register 3"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ADC_ADDR4,ADC Data Register 4"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "ADC_ADDR5,ADC Data Register 5"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADC_ADDR6,ADC Data Register 6"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ADC_ADDR7,ADC Data Register 7"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ADC_ADDR8,ADC Data Register 8"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ADC_ADDR9,ADC Data Register 9"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "ADC_ADDR10,ADC Data Register 10"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ADC_ADDR11,ADC Data Register 11"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "ADC_ADDR12,ADC Data Register 12"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ADC_ADDR13,ADC Data Register 13"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "ADC_ADDR14,ADC Data Register 14"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "ADC_ADDR15,ADC Data Register 15"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ADC_ADDR16,ADC Data Register 16"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "ADC_ADDR17,ADC Data Register 17"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "ADC_ADDR18,ADC Data Register 18"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC_ADDR19,ADC Data Register 19"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "ADC_ADDR29,ADC Data Register 29"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "ADC_ADDR30,ADC Data Register 30"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "ADC_ADDR31,ADC Data Register 31"
|
|
rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "ADC_ADCR,ADC Control Register"
|
|
bitfld.long 0x00 31. "DMOF,Differential Input Mode Output Format\nIf user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.."
|
|
bitfld.long 0x00 16.--18. "SMPTSEL,ADC Internal Sampling Time Selection" "0: 4 ADC clock for sampling 16 ADC clock for..,1: 5 ADC clock for sampling 17 ADC clock for..,2: 6 ADC clock for sampling 18 ADC clock for..,3: 7 ADC clock for sampling 19 ADC clock for..,4: 8 ADC clock for sampling 20 ADC clock for..,5: 9 ADC clock for sampling 21 ADC clock for..,6: 10 ADC clock for sampling 22 ADC clock for..,7: 11 ADC clock for sampling 23 ADC clock for.."
|
|
newline
|
|
bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger" "0: Conversion stops and A/D converter enters..,1: Conversion starts"
|
|
bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control\nNote: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADCHER register" "0: Single-end analog input mode,1: Differential analog input mode"
|
|
newline
|
|
bitfld.long 0x00 9. "PTEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADDR0~19 ADDR29~ADDR31" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR0~19 ADDR29~ADDR31.."
|
|
bitfld.long 0x00 8. "TRGEN,External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin PWM trigger and Timer trigger" "0: External trigger Disabled,1: External trigger Enabled"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge"
|
|
bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits" "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer3 overflow pulse trigger,2: Reserved,3: A/D conversion is started by PWM trigger"
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|
newline
|
|
bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode Control\nNote1: When changing the operation mode software should clear ADST bit first.\nNote2: In Burst mode the A/D result data is always at ADC Data Register 0" "0: Single conversion,1: Burst conversion,2: Single-cycle Scan,3: Continuous Scan"
|
|
bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "ADC_ADCHER,ADC Channel Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHEN,Analog Input Channel Enable Control\nSet ADCHER[19:0] bits to enable the corresponding analog input channel 19 ~ 0"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "ADC_ADCMPR0,ADC Compare Register 0"
|
|
hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)"
|
|
bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register" "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
|
|
newline
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bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: Channel 12 conversion result is selected to..,13: Channel 13 conversion result is selected to..,14: Channel 14 conversion result is selected to..,15: Channel 15 conversion result is selected to..,16: Channel 16 conversion result is selected to..,17: Channel 17 conversion result is selected to..,18: Channel 18 conversion result is selected to..,19: Channel 19 conversion result is selected to..,?,?,?,?,?,?,?,?,?,29: Band-gap voltage conversion result is..,30: Temperature sensor conversion result is..,31: Battery power conversion result is selected.."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
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group.long 0x8C++0x03
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line.long 0x00 "ADC_ADCMPR1,ADC Compare Register 1"
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hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)"
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bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register" "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3.--7. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: Channel 12 conversion result is selected to..,13: Channel 13 conversion result is selected to..,14: Channel 14 conversion result is selected to..,15: Channel 15 conversion result is selected to..,16: Channel 16 conversion result is selected to..,17: Channel 17 conversion result is selected to..,18: Channel 18 conversion result is selected to..,19: Channel 19 conversion result is selected to..,?,?,?,?,?,?,?,?,?,29: Band-gap voltage conversion result is..,30: Temperature sensor conversion result is..,31: Battery power conversion result is selected.."
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bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.."
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bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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bitfld.long 0x00 0. "CMPEN,Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled"
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group.long 0x90++0x03
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line.long 0x00 "ADC_ADSR0,ADC Status Register0"
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rbitfld.long 0x00 27.--31. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1" "0,1"
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rbitfld.long 0x00 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1" "0,1"
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rbitfld.long 0x00 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register" "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x00 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting"
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bitfld.long 0x00 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting"
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bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion" "0,1"
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rgroup.long 0x94++0x03
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line.long 0x00 "ADC_ADSR1,ADC Status Register1"
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hexmask.long 0x00 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[31:29 19:0] are the mirror of the VALID bits in ADDR31[17] ~ ADDR29[17] ADDR19[17]~ ADDR0[17]"
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rgroup.long 0x98++0x03
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line.long 0x00 "ADC_ADSR2,ADC Status Register2"
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hexmask.long 0x00 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[31:29 19:0] are the mirror of the OVERRUN bit in ADDR31[16] ~ADDR29[16] ADDR19[16] ~ ADDR0[16]"
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group.long 0x9C++0x03
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line.long 0x00 "ADC_ADTDCR,ADC Trigger Delay Control Register"
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hexmask.long.byte 0x00 0.--7. 1. "PTDT,PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock"
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rgroup.long 0x100++0x03
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line.long 0x00 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR19 and ADDR29 ~ ADDR31 registers"
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tree.end
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tree "CLK"
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base ad:0x50000200
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group.long 0x00++0x03
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line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
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bitfld.long 0x00 13. "HIRC48EN,HIRC48 Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 12. "HXTSELTYP,HXT Crystal Type Select Bit (Write Protect)\nThis is a protected register" "0: Select INV type,1: Select GM type"
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bitfld.long 0x00 10.--11. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally" "0: HXT frequency is lower than from 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,2: HXT frequency is from 12 MHz to 16 MHz,3: HXT frequency is higher than 16 MHz"
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bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then.."
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bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if the EINT0~5 GPIO UART0~2 WDT ACMP01 BOD VDET RTC TMR0~3 I2C0~1 or USCI0~2 wake-up occurred.\nNote1:.." "0,1"
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bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled"
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bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
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bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\nNote: This bit is write protected" "0: 32.768 KHz External Low Speed Crystal (LXT)..,1: 32.768 KHz External Low Speed Crystal (LXT).."
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bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CONFIG0 [26:24]" "0: 4~24 MHz External High Speed Crystal (HXT)..,1: 4~24 MHz External High Speed Crystal (HXT).."
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group.long 0x04++0x03
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line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
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bitfld.long 0x00 21. "GPIOFCKEN,General Purpose I/O PF Group Clock Enable Bit" "0: GPIO PF group clock Disabled,1: GPIO PF group clock Enabled"
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bitfld.long 0x00 20. "GPIOECKEN,General Purpose I/O PE Group Clock Enable Bit" "0: GPIO PE group clock Disabled,1: GPIO PE group clock Enabled"
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bitfld.long 0x00 19. "GPIODCKEN,General Purpose I/O PD Group Clock Enable Bit" "0: GPIO PD group clock Disabled,1: GPIO PD group clock Enabled"
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bitfld.long 0x00 18. "GPIOCCKEN,General Purpose I/O PC Group Clock Enable Bit" "0: GPIO PC group clock Disabled,1: GPIO PC group clock Enabled"
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bitfld.long 0x00 17. "GPIOBCKEN,General Purpose I/O PB Group Clock Enable Bit" "0: GPIO PB group clock Disabled,1: GPIO PB group clock Enabled"
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bitfld.long 0x00 16. "GPIOACKEN,General Purpose I/O PA Group Clock Enable Bit" "0: GPIO PA group clock Disabled,1: GPIO PA group clock Enabled"
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bitfld.long 0x00 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC peripheral clock Disabled when chip..,1: FMC peripheral clock Enabled when chip.."
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bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
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bitfld.long 0x00 4. "HDIVCKEN,Hardware Divider Controller Clock Enable Bit" "0: Hardware divider peripheral clock Disabled,1: Hardware divider peripheral clock Enabled"
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bitfld.long 0x00 3. "EBICKEN,EBI Controller Clock Enable Bit" "0: EBI peripheral clock Disabled,1: EBI peripheral clock Enabled"
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bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
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group.long 0x08++0x03
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line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x00 30. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog Comparator 0/1 clock Disabled,1: Analog Comparator 0/1 clock Enabled"
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bitfld.long 0x00 28. "ADCCKEN,Analog-digital-converter (ADC) Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled"
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bitfld.long 0x00 21. "PWM1CKEN,PWM1 Clock Enable Bit" "0: PWM1 clock Disabled,1: PWM1 clock Enabled"
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bitfld.long 0x00 20. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled"
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bitfld.long 0x00 18. "UART2CKEN,UART2 Clock Enable Bit" "0: UART2 clock Disabled,1: UART2 clock Enabled"
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bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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bitfld.long 0x00 13. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled"
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bitfld.long 0x00 12. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled"
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bitfld.long 0x00 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled"
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bitfld.long 0x00 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled"
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bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO Clock Disabled,1: CLKO Clock Enabled"
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bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled"
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bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled"
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bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled"
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bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled"
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bitfld.long 0x00 1. "RTCCKEN,Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only" "0: RTC Clock Disabled,1: RTC Clock Enabled"
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bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled"
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rgroup.long 0x0C++0x03
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line.long 0x00 "CLK_STATUS,Clock Status Monitor Register"
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bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x00 5. "HIRC48STB,HIRC48 Clock Source Stable Flag (Read Only)" "0: 48 MHz internal high speed RC oscillator..,1: 48 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: 22.1184 MHz internal high speed RC oscillator..,1: 22.1184 MHz internal high speed RC oscillator.."
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bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator..,1: 10 kHz internal low speed RC oscillator.."
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bitfld.long 0x00 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
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bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
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group.long 0x10++0x03
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line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x00 7. "PCLK1SEL,PCLK1 Clock Source Selection (Write Protect)\nNote: This bit is write protected" "0: APB1 BUS clock source from HCLK,1: APB1 BUS clock source from HCLK/2"
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bitfld.long 0x00 6. "PCLK0SEL,PCLK0 Clock Source Selection (Write Protect)\nNote: This bit is write protected" "0: APB0 BUS clock source from HCLK,1: APB0 BUS clock source from HCLK/2"
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bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote2: These bits are write protected" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2"
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bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\nThe default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration.." "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from PLL clock,3: Clock source from LIRC,4: Clock source from HIRC48,?,?,7: Clock source from HIRC clock"
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group.long 0x14++0x03
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line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1"
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bitfld.long 0x00 29. "PWM1SEL,PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL" "0: Clock source from PLL clock,1: Clock source from PCLK1"
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bitfld.long 0x00 28. "PWM0SEL,PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL" "0: Clock source from PLL clock,1: Clock source from PCLK0"
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bitfld.long 0x00 24.--25. "UARTSEL,UART Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from 32.768 kHz external low..,3: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock T3 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK1,3: Clock source from external clock T2 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock T1 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from PCLK0,3: Clock source from external clock T0 pin,?,5: Clock source from 10 kHz internal low speed..,?,7: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 2.--3. "ADCSEL,ADC Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL,2: Clock source from PCLK0,3: Clock source from 22.1184 MHz internal high.."
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bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected" "0: Reserved,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK/2048 clock,3: Clock source from 10 kHz internal low speed.."
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group.long 0x18++0x03
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line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0"
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hexmask.long.byte 0x00 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source"
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bitfld.long 0x00 8.--11. "UARTDIV,UART Clock Divide Number From UART Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x1C++0x03
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line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2"
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bitfld.long 0x00 26.--27. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from PCLK0,3: Clock source from 48 MHz internal high speed.."
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bitfld.long 0x00 24.--25. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from PCLK0,3: Clock source from 48 MHz internal high speed.."
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bitfld.long 0x00 18. "RTCSEL,RTC Clock Source Selection" "0: Clock source from 32.768 kHz external low..,1: Clock source from 10 kHz internal low speed.."
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bitfld.long 0x00 16.--17. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "?,?,2: Clock source from HCLK/2048 clock,3: Clock source from 10 kHz internal low speed.."
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newline
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bitfld.long 0x00 2.--4. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from 32.768 kHz external low..,2: Clock source from HCLK,3: Clock source from 22.1184 MHz internal high..,?,5: Clock source from 48 MHz internal high speed..,?..."
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group.long 0x20++0x03
|
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line.long 0x00 "CLK_PLLCTL,PLL Control Register"
|
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bitfld.long 0x00 23. "STBSEL,PLL Stable Counter Selection" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 12288 PLL source clock.."
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bitfld.long 0x00 19. "PLLSRC,PLL Source Clock Selection" "0: PLL source clock from external 4~24 MHz..,1: PLL source clock from internal 22.1184 MHz.."
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newline
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bitfld.long 0x00 18. "OE,PLL OE (FOUT Enable) Control" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
|
|
bitfld.long 0x00 17. "BP,PLL Bypass Control" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
|
|
newline
|
|
bitfld.long 0x00 16. "PD,Power-down Mode \nIf set PDEN(CLK_PWRCTL[7]) bit to 1 the PLL will enter Power-down mode too" "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
|
|
bitfld.long 0x00 14.--15. "OUTDIV,PLL Output Divider Control \nRefer to the formulas below the table" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 9.--13. "INDIV,PLL Input Divider Control \nRefer to the formulas below the table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--8. 1. "FBDIV,PLL Feedback Divider Control \nRefer to the formulas below the table"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register"
|
|
bitfld.long 0x00 6. "CLK1HZEN,Clock Output 1Hz Enable Bit" "0: 1 Hz clock output for 32.768 kHz external low..,1: 1 Hz clock output for 32.768 kHz external low.."
|
|
bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
|
|
newline
|
|
bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
|
|
bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
|
|
bitfld.long 0x00 10. "USCI2CKEN,USCI2 Clock Enable Bit" "0: USCI2 clock Disabled,1: USCI2 clock Enabled"
|
|
bitfld.long 0x00 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled"
|
|
bitfld.long 0x00 1. "SC1CKEN,SC1 Clock Enable Bit" "0: SC1 clock Disabled,1: SC1 clock Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SC0CKEN,SC0 Clock Enable Bit" "0: SC0 Clock Disabled,1: SC0 Clock Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CLK_CLKSEL3,Clock Source Select Control Register 3"
|
|
bitfld.long 0x00 2.--3. "SC1SEL,SC1 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from PCLK1,3: Clock source from 22.1184 MHz internal high.."
|
|
bitfld.long 0x00 0.--1. "SC0SEL,SC0 Clock Source Selection" "0: Clock source from 4~24 MHz external high..,1: Clock source from PLL clock,2: Clock source from PCLK1,3: Clock source from 22.1184 MHz internal high.."
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CLK_CLKDIV1,Clock Divider Number Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "SC1DIV,SC1 Clock Divide Number From SC1 Clock Source"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SC0DIV,SC0 Clock Divide Number From SC0 Clock Source"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CLK_BODCLK,Clock Source Select for BOD Control Register"
|
|
bitfld.long 0x00 0. "VDETCKSEL,Clock Source Selection for Voltage Detector\nThe Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL.\nNote1: If LIRC is selected LIRCEN (CLK_PWRCTL[3]) must be enabled.\nNote2: If LXT is selected LXTEN.." "0: Clock source is from 10 kHz internal low..,1: Clock source is from 32.768 kHz external low.."
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register"
|
|
bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
newline
|
|
bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
|
bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register"
|
|
bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'.\nNote2: This bit is write protected" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'" "0: 32.768 kHz external low speed crystal..,1: 32.768 kHz external low speed crystal.."
|
|
newline
|
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bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote1: This bit can be cleared to 0 by software writing '1'.\nNote2: This bit is write protected" "0: 4~24 MHz external high speed crystal..,1: 4~24 MHz external high speed crystal.."
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will set to 1"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CLK_CDLOWB,Clock Frequency Detector Low Boundary Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Low Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will set to 1"
|
|
tree.end
|
|
tree "CRC"
|
|
base ad:0x50018000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode"
|
|
bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the valid write data length of DATA (CRC_DAT[31:0]).\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..."
|
|
newline
|
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bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0])" "0: 1's complement for CRC CHECKSUM Disabled,1: 1's complement for CRC CHECKSUM Enabled"
|
|
bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0])" "0: 1's complement for CRC DATA Disabled,1: 1's complement for CRC DATA Enabled"
|
|
newline
|
|
bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse result for CRC checksum is.." "0: Bit order reverse for CRC CHECKSUM Disabled,1: Bit order reverse for CRC CHECKSUM Enabled"
|
|
bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC DATA Disabled,1: Bit order reversed for CRC DATA Enabled (per.."
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|
newline
|
|
bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nSet this bit will auto reolad SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.\nNote: This bit will be cleared automatically" "0: No effect,1: Reolad SEED value to CHECKSUM as CRC.."
|
|
bitfld.long 0x00 0. "CRCEN,CRC Generator Enable Bit\nSet this bit 1 to enable CRC generator for CRC operation" "0: No effect,1: CRC generator is active"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CRC_DAT,CRC Write Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.\nNote2: The valid bits of CRC_SEED[31:0] is correlated to.."
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register"
|
|
hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result.\nNote: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30])"
|
|
tree.end
|
|
tree "EBI"
|
|
base ad:0x50010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EBI_CTL0,External Bus Interface Bank0 Control Register"
|
|
bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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|
newline
|
|
bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
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|
bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse" "0: Chip select pin (EBI_nCSx) is active low,1: Chip select pin (EBI_nCSx) is active high"
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|
newline
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bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
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|
bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EBI_TCTL0,External Bus Interface Bank0 Timing Control Register"
|
|
bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
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|
newline
|
|
bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
|
|
bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
newline
|
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bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD define data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC define data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EBI_CTL1,External Bus Interface Bank1 Control Register"
|
|
bitfld.long 0x00 16.--18. "TALE,Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x00 8.--10. "MCLKDIV,External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow" "0: HCLK/1,1: HCLK/2,2: HCLK/4,3: HCLK/8,4: HCLK/16,5: HCLK/32,6: HCLK/64,7: HCLK/128"
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|
newline
|
|
bitfld.long 0x00 4. "CACCESS,Continuous Data Access Mode\nWhen continuous access mode enabled the tASU tALE and tLHD cycles are bypass for continuous data transfer request" "0: Continuous data access mode Disabled,1: Continuous data access mode Enabled"
|
|
bitfld.long 0x00 2. "CSPOLINV,Chip Select Pin Polar Inverse" "0: Chip select pin (EBI_nCSx) is active low,1: Chip select pin (EBI_nCSx) is active high"
|
|
newline
|
|
bitfld.long 0x00 1. "DW16,EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit" "0: EBI data width is 8-bit,1: EBI data width is 16-bit"
|
|
bitfld.long 0x00 0. "EN,EBI Enable Bit\nThis bit is the functional enable bit for EBI" "0: EBI function Disabled,1: EBI function Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EBI_TCTL1,External Bus Interface Bank1 Timing Control Register"
|
|
bitfld.long 0x00 24.--27. "R2R,Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "WAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
|
|
newline
|
|
bitfld.long 0x00 22. "RAHDOFF,Access Hold Time Disable Control When" "0: Data Access Hold Time (tAHD) during EBI..,1: Data Access Hold Time (tAHD) during EBI.."
|
|
bitfld.long 0x00 12.--15. "W2X,Idle Cycle After Write\nThis field defines the number of W2X idle cycle" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TAHD,EBI Data Access Hold Time\nTAHD define data access hold time (tAHD)" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3.--7. "TACC,EBI Data Access Time\nTACC define data access time (tACC)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "FMC"
|
|
base ad:0x5000C000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FMC_ISPCTL,ISP Control Register"
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself.." "0,1"
|
|
bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected" "0: LDROM cannot be updated,1: LDROM can be updated"
|
|
newline
|
|
bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: CONFIG cannot be updated,1: CONFIG can be updated"
|
|
bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.."
|
|
newline
|
|
bitfld.long 0x00 2. "SPUEN,SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: SPROM cannot be updated,1: SPROM can be updated"
|
|
bitfld.long 0x00 1. "BS,Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Booting from APROM,1: Booting from LDROM"
|
|
newline
|
|
bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nISP function enable bit" "0: ISP function Disabled,1: ISP function Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "FMC_ISPADDR,ISP Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe NuMicro M0564 series is equipped with embedded flash"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "FMC_ISPDAT,ISP Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FMC_ISPCMD,ISP CMD Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register"
|
|
bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write-protected" "0: ISP operation is finished,1: ISP is progressed"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "FMC_DFBA,Data Flash Base Address"
|
|
hexmask.long 0x00 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FMC_FTCTL,Flash Access Time Control Register"
|
|
bitfld.long 0x00 7. "CACHEOFF,Flash Cache Disable Bit (Write Protect)\nNote: This bit is write-protected" "0: Flash Cache function Enabled (default),1: Flash Cache function Disabled"
|
|
bitfld.long 0x00 4.--6. "FOM,Frequency Optimization Mode (Write Protect)\nThe M0564 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote: This bit is write-protected" "?,1: Frequency 24MHz.\nFrequency 72MHz,?..."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "FMC_ISPSTS,ISP Status Register"
|
|
bitfld.long 0x00 31. "SCODE,Security Code Active Flag\nThis bit is set by hardware when detecting SPROM secured code is active at flash initiation or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation" "0: Secured code is inactive,1: Secured code is active"
|
|
hexmask.long.tbyte 0x00 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM.\nVECMAP [18:12] should be 0"
|
|
newline
|
|
bitfld.long 0x00 7. "ALLONE,Flash All-one Verification Flag \nThis bit is set by hardware if all of flash bits are 1 and clear if flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of flash bits are 1 after 'Run Flash.."
|
|
bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
|
|
newline
|
|
rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode"
|
|
rbitfld.long 0x00 0. "ISPBUSY,ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0])" "0: ISP operation is finished,1: ISP is progressed"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FMC_MPDAT0,ISP Data0 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT0,ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "FMC_MPDAT1,ISP Data1 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT1,ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FMC_MPDAT2,ISP Data2 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT2,ISP Data 2\nThis register is the third 32-bit data for multi-word programming"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "FMC_MPDAT3,ISP Data3 Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISPDAT3,ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming"
|
|
rgroup.long 0xC0++0x03
|
|
line.long 0x00 "FMC_MPSTS,ISP Multi-program Status Register"
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bitfld.long 0x00 7. "D3,ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete" "0: FMC_MPDAT3 register is empty or program to..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x00 6. "D2,ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete" "0: FMC_MPDAT2 register is empty or program to..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x00 5. "D1,ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete" "0: FMC_MPDAT1 register is empty or program to..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x00 4. "D0,ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete" "0: FMC_MPDAT0 register is empty or program to..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x00 2. "ISPFF,ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1"
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bitfld.long 0x00 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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bitfld.long 0x00 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
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rgroup.long 0xC4++0x03
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line.long 0x00 "FMC_MPADDR,ISP Multi-program Address Register"
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hexmask.long 0x00 0.--31. 1. "MPADDR,ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete"
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tree.end
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tree "GPIO"
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base ad:0x50004000
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group.long 0x00++0x03
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line.long 0x00 "PA_MODE,PA I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x04++0x03
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line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x08++0x03
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line.long 0x00 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x0C++0x03
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line.long 0x00 "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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rgroup.long 0x10++0x03
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line.long 0x00 "PA_PIN,PA Pin Value"
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bitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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bitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x14++0x03
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line.long 0x00 "PA_DBEN,PA De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x18++0x03
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line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x1C++0x03
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line.long 0x00 "PA_INTEN,PA Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x20++0x03
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line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x24++0x03
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line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x28++0x03
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line.long 0x00 "PA_SLEWCTL,PA High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x40++0x03
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line.long 0x00 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x44++0x03
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line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x48++0x03
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line.long 0x00 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x4C++0x03
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line.long 0x00 "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x50++0x03
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line.long 0x00 "PB_PIN,PB Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x54++0x03
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line.long 0x00 "PB_DBEN,PB De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x5C++0x03
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line.long 0x00 "PB_INTEN,PB Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x60++0x03
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line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x64++0x03
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line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x68++0x03
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line.long 0x00 "PB_SLEWCTL,PB High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x80++0x03
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line.long 0x00 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x84++0x03
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line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x88++0x03
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line.long 0x00 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x8C++0x03
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line.long 0x00 "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x90++0x03
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line.long 0x00 "PC_PIN,PC Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x94++0x03
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line.long 0x00 "PC_DBEN,PC De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x98++0x03
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line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x9C++0x03
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line.long 0x00 "PC_INTEN,PC Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0xA0++0x03
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line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0xA4++0x03
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line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xA8++0x03
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line.long 0x00 "PC_SLEWCTL,PC High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0xC0++0x03
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line.long 0x00 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0xC4++0x03
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line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0xC8++0x03
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line.long 0x00 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0xCC++0x03
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line.long 0x00 "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0xD0++0x03
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line.long 0x00 "PD_PIN,PD Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0xD4++0x03
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line.long 0x00 "PD_DBEN,PD De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0xDC++0x03
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line.long 0x00 "PD_INTEN,PD Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0xE0++0x03
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line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0xE4++0x03
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line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0xE8++0x03
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line.long 0x00 "PD_SLEWCTL,PD High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x100++0x03
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line.long 0x00 "PE_MODE,PE I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x104++0x03
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line.long 0x00 "PE_DINOFF,PE Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x108++0x03
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line.long 0x00 "PE_DOUT,PE Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x10C++0x03
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line.long 0x00 "PE_DATMSK,PE Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x110++0x03
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line.long 0x00 "PE_PIN,PE Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x114++0x03
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line.long 0x00 "PE_DBEN,PE De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x118++0x03
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line.long 0x00 "PE_INTTYPE,PE Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x11C++0x03
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line.long 0x00 "PE_INTEN,PE Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x120++0x03
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line.long 0x00 "PE_INTSRC,PE Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x124++0x03
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line.long 0x00 "PE_SMTEN,PE Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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group.long 0x128++0x03
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line.long 0x00 "PE_SLEWCTL,PE High Slew Rate Control"
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bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x12C++0x03
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line.long 0x00 "PE_DRVCTL,PE High Drive Strength Control"
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bitfld.long 0x00 13. "HDRVEN13,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x00 12. "HDRVEN12,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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newline
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bitfld.long 0x00 11. "HDRVEN11,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x00 10. "HDRVEN10,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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newline
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bitfld.long 0x00 9. "HDRVEN9,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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bitfld.long 0x00 8. "HDRVEN8,Port E Pin[n] Driving Strength Control" "0: Px.n output with basic driving strength,1: Px.n output with high driving strength"
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group.long 0x140++0x03
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line.long 0x00 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x00 30.--31. "MODE15,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 28.--29. "MODE14,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 26.--27. "MODE13,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 24.--25. "MODE12,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 22.--23. "MODE11,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 20.--21. "MODE10,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 18.--19. "MODE9,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 16.--17. "MODE8,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 14.--15. "MODE7,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 12.--13. "MODE6,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 10.--11. "MODE5,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 8.--9. "MODE4,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 6.--7. "MODE3,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 4.--5. "MODE2,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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newline
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bitfld.long 0x00 2.--3. "MODE1,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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bitfld.long 0x00 0.--1. "MODE0,Port A-f I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote3: The PE.14/PE.15 pin is ignored" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode"
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group.long 0x144++0x03
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line.long 0x00 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x00 31. "DINOFF15,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 30. "DINOFF14,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 29. "DINOFF13,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 28. "DINOFF12,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 27. "DINOFF11,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 26. "DINOFF10,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 25. "DINOFF9,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 24. "DINOFF8,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 23. "DINOFF7,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 22. "DINOFF6,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 21. "DINOFF5,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 20. "DINOFF4,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 19. "DINOFF3,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 18. "DINOFF2,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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newline
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bitfld.long 0x00 17. "DINOFF1,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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bitfld.long 0x00 16. "DINOFF0,Port A-f Pin[n] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.."
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group.long 0x148++0x03
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line.long 0x00 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x00 15. "DOUT15,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 14. "DOUT14,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 13. "DOUT13,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 12. "DOUT12,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 11. "DOUT11,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 10. "DOUT10,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 9. "DOUT9,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 8. "DOUT8,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 7. "DOUT7,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 6. "DOUT6,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 5. "DOUT5,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 4. "DOUT4,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 3. "DOUT3,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 2. "DOUT2,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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newline
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bitfld.long 0x00 1. "DOUT1,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x00 0. "DOUT0,Port A-f Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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group.long 0x14C++0x03
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line.long 0x00 "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0x00 15. "DATMSK15,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 14. "DATMSK14,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 13. "DATMSK13,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 12. "DATMSK12,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 11. "DATMSK11,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 10. "DATMSK10,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 9. "DATMSK9,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 8. "DATMSK8,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 7. "DATMSK7,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 6. "DATMSK6,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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newline
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bitfld.long 0x00 5. "DATMSK5,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 4. "DATMSK4,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 3. "DATMSK3,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 2. "DATMSK2,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 1. "DATMSK1,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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bitfld.long 0x00 0. "DATMSK0,Port A-f Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected"
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group.long 0x150++0x03
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line.long 0x00 "PF_PIN,PF Pin Value"
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rbitfld.long 0x00 15. "PIN15,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 14. "PIN14,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 13. "PIN13,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 12. "PIN12,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 11. "PIN11,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 10. "PIN10,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 9. "PIN9,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 8. "PIN8,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 7. "PIN7,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 6. "PIN6,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 5. "PIN5,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 4. "PIN4,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 3. "PIN3,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 2. "PIN2,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 1. "PIN1,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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rbitfld.long 0x00 0. "PIN0,Port A-f Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
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group.long 0x154++0x03
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line.long 0x00 "PF_DBEN,PF De-bounce Enable Control"
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bitfld.long 0x00 15. "DBEN15,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 14. "DBEN14,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 13. "DBEN13,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 12. "DBEN12,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 11. "DBEN11,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 10. "DBEN10,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 9. "DBEN9,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 8. "DBEN8,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 7. "DBEN7,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 6. "DBEN6,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 5. "DBEN5,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 4. "DBEN4,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 3. "DBEN3,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 2. "DBEN2,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 1. "DBEN1,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x00 0. "DBEN0,Port A-f Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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group.long 0x158++0x03
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line.long 0x00 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x00 15. "TYPE15,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 14. "TYPE14,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 13. "TYPE13,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 12. "TYPE12,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 11. "TYPE11,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 10. "TYPE10,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 9. "TYPE9,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 8. "TYPE8,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 7. "TYPE7,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 6. "TYPE6,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 5. "TYPE5,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 4. "TYPE4,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 3. "TYPE3,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 2. "TYPE2,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 1. "TYPE1,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x00 0. "TYPE0,Port A-f Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt"
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group.long 0x15C++0x03
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line.long 0x00 "PF_INTEN,PF Interrupt Enable Control"
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bitfld.long 0x00 31. "RHIEN15,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 30. "RHIEN14,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 29. "RHIEN13,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 28. "RHIEN12,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 27. "RHIEN11,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 26. "RHIEN10,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 25. "RHIEN9,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 24. "RHIEN8,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 23. "RHIEN7,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 22. "RHIEN6,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 21. "RHIEN5,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 20. "RHIEN4,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 19. "RHIEN3,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 18. "RHIEN2,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 17. "RHIEN1,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 16. "RHIEN0,Port 0-5 Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.."
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bitfld.long 0x00 15. "FLIEN15,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 14. "FLIEN14,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 13. "FLIEN13,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 12. "FLIEN12,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 11. "FLIEN11,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 10. "FLIEN10,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 9. "FLIEN9,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 8. "FLIEN8,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 7. "FLIEN7,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 6. "FLIEN6,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 5. "FLIEN5,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 4. "FLIEN4,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 3. "FLIEN3,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 2. "FLIEN2,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 1. "FLIEN1,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x00 0. "FLIEN0,Port A-f Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled"
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group.long 0x160++0x03
|
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line.long 0x00 "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0x00 15. "INTSRC15,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 14. "INTSRC14,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 13. "INTSRC13,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 12. "INTSRC12,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 11. "INTSRC11,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 10. "INTSRC10,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
|
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bitfld.long 0x00 9. "INTSRC9,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 8. "INTSRC8,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
|
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bitfld.long 0x00 7. "INTSRC7,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 6. "INTSRC6,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 5. "INTSRC5,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 4. "INTSRC4,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
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bitfld.long 0x00 3. "INTSRC3,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 2. "INTSRC2,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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newline
|
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bitfld.long 0x00 1. "INTSRC1,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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bitfld.long 0x00 0. "INTSRC0,Port A-f Pin[n] Interrupt Source Flag\nWrite Operation:\nNote2: The PE.14/PE.15 pin is ignored" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.."
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group.long 0x164++0x03
|
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line.long 0x00 "PF_SMTEN,PF Input Schmitt Trigger Enable"
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bitfld.long 0x00 15. "SMTEN15,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 14. "SMTEN14,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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|
newline
|
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bitfld.long 0x00 13. "SMTEN13,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 12. "SMTEN12,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 11. "SMTEN11,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 10. "SMTEN10,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 9. "SMTEN9,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 8. "SMTEN8,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 7. "SMTEN7,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 6. "SMTEN6,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 5. "SMTEN5,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 4. "SMTEN4,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 3. "SMTEN3,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 2. "SMTEN2,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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newline
|
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bitfld.long 0x00 1. "SMTEN1,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x00 0. "SMTEN0,Port A-f Pin[n] Input Schmitt Trigger Enable Bit\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
|
|
group.long 0x168++0x03
|
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line.long 0x00 "PF_SLEWCTL,PF High Slew Rate Control"
|
|
bitfld.long 0x00 15. "HSREN15,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 14. "HSREN14,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 13. "HSREN13,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 12. "HSREN12,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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|
newline
|
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bitfld.long 0x00 11. "HSREN11,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 10. "HSREN10,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 9. "HSREN9,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 8. "HSREN8,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 7. "HSREN7,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 6. "HSREN6,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 5. "HSREN5,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 4. "HSREN4,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 3. "HSREN3,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 2. "HSREN2,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
|
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bitfld.long 0x00 1. "HSREN1,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x00 0. "HSREN0,Port A-f Pin[n] High Slew Rate Control\nNote2: The PE.14/PE.15 pin is ignored" "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x180++0x03
|
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line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control"
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bitfld.long 0x00 5. "ICLKON,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the.."
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newline
|
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bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks"
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group.long 0x200++0x03
|
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line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x204++0x03
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line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x208++0x03
|
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line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x20C++0x03
|
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line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x210++0x03
|
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line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x214++0x03
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line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x218++0x03
|
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line.long 0x00 "PA6_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x21C++0x03
|
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line.long 0x00 "PA7_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x220++0x03
|
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line.long 0x00 "PA8_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x224++0x03
|
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line.long 0x00 "PA9_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x228++0x03
|
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line.long 0x00 "PA10_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x22C++0x03
|
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line.long 0x00 "PA11_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x230++0x03
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line.long 0x00 "PA12_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x234++0x03
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line.long 0x00 "PA13_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x238++0x03
|
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line.long 0x00 "PA14_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x23C++0x03
|
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line.long 0x00 "PA15_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x240++0x03
|
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line.long 0x00 "PB0_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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group.long 0x244++0x03
|
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line.long 0x00 "PB1_PDIO,GPIO PB.n Pin Data Input/Output"
|
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group.long 0x248++0x03
|
|
line.long 0x00 "PB2_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "PB3_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output"
|
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group.long 0x25C++0x03
|
|
line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output"
|
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group.long 0x260++0x03
|
|
line.long 0x00 "PB8_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "PB9_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "PB10_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "PB11_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "PB12_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "PB13_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "PB14_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "PB15_PDIO,GPIO PB.n Pin Data Input/Output"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
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|
group.long 0x284++0x03
|
|
line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "PC8_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "PC9_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "PC10_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "PC11_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "PC12_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "PC13_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "PC14_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "PC15_PDIO,GPIO PC.n Pin Data Input/Output"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "PD8_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "PD9_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "PD10_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "PD11_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "PD12_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "PD13_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "PD14_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "PD15_PDIO,GPIO PD.n Pin Data Input/Output"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PE0_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "PE1_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "PE2_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "PE3_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "PE4_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "PE5_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "PE6_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "PE7_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "PE8_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "PE9_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "PE10_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x32C++0x03
|
|
line.long 0x00 "PE11_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "PE12_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x334++0x03
|
|
line.long 0x00 "PE13_PDIO,GPIO PE.n Pin Data Input/Output"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "PF0_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
bitfld.long 0x00 0. "PDIO,GPIO Px.N Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nNote3: The PE.14/PE.15 pin is ignored" "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high"
|
|
group.long 0x344++0x03
|
|
line.long 0x00 "PF1_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "PF2_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x34C++0x03
|
|
line.long 0x00 "PF3_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "PF4_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x354++0x03
|
|
line.long 0x00 "PF5_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x358++0x03
|
|
line.long 0x00 "PF6_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
group.long 0x35C++0x03
|
|
line.long 0x00 "PF7_PDIO,GPIO PF.n Pin Data Input/Output"
|
|
tree.end
|
|
tree "HDIV"
|
|
base ad:0x50014000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "HDIV_DIVIDEND,Dividend Source Register"
|
|
hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation starting"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "HDIV_DIVISOR,Divisor Source Resister"
|
|
hexmask.long.word 0x00 0.--15. 1. "DIVISOR,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculate"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "HDIV_DIVQUO,Quotient Result Resister"
|
|
hexmask.long 0x00 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation complete"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "HDIV_DIVREM,Remainder Result Register"
|
|
hexmask.long 0x00 0.--31. 1. "REMAINDER,Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) which holds the remainder result of divider after calculation complete"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "HDIV_DIVSTS,Divider Status Register"
|
|
bitfld.long 0x00 1. "DIV0,Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written" "0: The divisor is not 0,1: The divisor is 0"
|
|
bitfld.long 0x00 0. "FINISH,Division Finish Flag\nThe flag will become low when the divider is in calculation" "0: Under Calculation,1: Calculation finished"
|
|
tree.end
|
|
tree "I2C"
|
|
repeat 2. (list 0. 1.) (list ad:0x40020000 ad:0x40120000)
|
|
tree "I2C$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C_CTL,I2C Control Register 0"
|
|
bitfld.long 0x00 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
|
|
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Bit" "0: I2C serial function Disabled,1: I2C serial function Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware" "0,1"
|
|
bitfld.long 0x00 2. "AA,Assert Acknowledge Control" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Bit\nWhen Enabled the 14-bit time-out counter will start counting when SI is clear" "0: Time-out counter Disabled,1: Time-out counter Enabled"
|
|
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nWhen Enabled The time-out period is extend 4 times" "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C_ADDR1,I2C Slave Address Register1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "I2C_ADDR2,I2C Slave Address Register2"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "I2C_ADDR3,I2C Slave Address Register3"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address \nThe content of this register is irrelevant when I2C is in Master mode"
|
|
bitfld.long 0x00 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
|
|
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
|
|
bitfld.long 0x00 7. "NHDBUSEN,I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear it may cause error data transmitted or received" "0: I2C don't hold bus after wake-up disable,1: I2C don't hold bus after wake-up enable"
|
|
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
|
|
bitfld.long 0x00 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
|
|
newline
|
|
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C this bit is set to 1" "0,1"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "I2C_CTL1,I2C Control Register 1"
|
|
bitfld.long 0x00 8. "PDMASTR,PDMA Stretch Bit" "0: I2C sends STOP automatically after PDMA..,1: I2C SCL bus is stretched by hardware after.."
|
|
bitfld.long 0x00 7. "NSTRETCH,No Stretch on the I2C Bus" "0: I2C SCL bus is stretched by hardware if the..,1: I2C SCL bus is not stretched by hardware if.."
|
|
newline
|
|
bitfld.long 0x00 6. "TWOBUFRST,Two-level Buffer Reset" "0: No effect,1: Reset the related counters two-level buffer.."
|
|
bitfld.long 0x00 5. "TWOBUFEN,Two-level Buffer Enable Bit" "0: Two-level buffer Disabled,1: Two-level buffer Enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "UDRIEN,I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer" "0,1"
|
|
bitfld.long 0x00 3. "OVRIEN,I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic"
|
|
bitfld.long 0x00 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "I2C_STATUS1,I2C Status Register 1"
|
|
bitfld.long 0x00 8. "ONBUSY,on Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 7. "UDR,I2C Under Run Status Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "OVR,I2C over Run Status Bit" "0,1"
|
|
bitfld.long 0x00 5. "EMPTY,Two-level Buffer Empty\nThis bit is set when POINTER is equal to 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "FULL,Two-level Buffer Full\nThis bit is set when POINTER is equal to 2" "0,1"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "I2C_TMCTL,I2C Timing Configure Control Register"
|
|
bitfld.long 0x00 6.--11. "HTCTL,Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "STCTL,Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "INT"
|
|
base ad:0x50000300
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "IRQ0_SRC,IRQ0 (BOD) Interrupt Source Identity"
|
|
bitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "IRQ1_SRC,IRQ1 (WDT) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IRQ2_SRC,IRQ2 (EINT0/2/4) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IRQ3_SRC,IRQ3 (EINT1/3/5) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IRQ4_SRC,IRQ4 (GPA/B) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IRQ5_SRC,IRQ5 (GPC/D/E/F) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IRQ6_SRC,IRQ6 (PWM0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IRQ7_SRC,IRQ7 (PWM1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IRQ8_SRC,IRQ8 (TMR0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IRQ9_SRC,IRQ9 (TMR1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IRQ10_SRC,IRQ10 (TMR2) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IRQ11_SRC,IRQ11 (TMR3) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IRQ12_SRC,IRQ12 (UART0/2) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IRQ13_SRC,IRQ13 (UART1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IRQ14_SRC,IRQ14 (SPI0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IRQ15_SRC,IRQ15 (SPI1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IRQ16_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IRQ17_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IRQ18_SRC,IRQ18 (I2C0) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IRQ19_SRC,IRQ19 (I2C1) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IRQ20_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IRQ21_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IRQ22_SRC,IRQ22 (USCI0/1/2) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IRQ23_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IRQ24_SRC,IRQ24 (SC0/1) Interrupt Source Identify"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "IRQ25_SRC,IRQ25 (ACMP) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IRQ26_SRC,IRQ26 (PDMA) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IRQ27_SRC,Reserved"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IRQ28_SRC,IRQ28 (PWRWU) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "IRQ29_SRC,IRQ29 (ADC) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "IRQ30_SRC,IRQ30 (IRC/CLKD) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IRQ31_SRC,IRQ31 (RTC) Interrupt Source Identity"
|
|
rbitfld.long 0x00 0.--3. "INT_SRC,Interrupt Source\nDefine the interrupt sources for interrupt event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NMI_SEL,NMI Source Interrupt Select Control Register"
|
|
bitfld.long 0x00 8. "NMI_EN,NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: NMI interrupt Disabled,1: NMI interrupt Enabled"
|
|
bitfld.long 0x00 0.--4. "NMI_SEL,NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "PDMA"
|
|
base ad:0x50008000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel 0"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size" "?,?,?,3: No Increment (Fixed Address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel 0"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PDMA_DSCT0_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel 1"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size" "?,?,?,3: No Increment (Fixed Address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel 1"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PDMA_DSCT1_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel 2"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size" "?,?,?,3: No Increment (Fixed Address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel 2"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PDMA_DSCT2_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel 3"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size" "?,?,?,3: No Increment (Fixed Address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel 3"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PDMA_DSCT3_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel 4"
|
|
hexmask.long.word 0x00 16.--29. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.."
|
|
bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size" "?,?,?,3: No increment (fixed address)"
|
|
bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size" "?,?,?,3: No Increment (Fixed Address)"
|
|
newline
|
|
bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers"
|
|
newline
|
|
bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel 4"
|
|
hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel 4"
|
|
hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address Register\nThis field indicates a 32-bit destination address of PDMA controller"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PDMA_DSCT4_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address in system memory"
|
|
hexmask.long.word 0x00 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset\nThis field indicates the offset of the first descriptor table address in system memory"
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rgroup.long 0x50++0x03
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line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel 0"
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hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
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group.long 0x54++0x03
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line.long 0x00 "PDMA_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel 1"
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hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
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group.long 0x58++0x03
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line.long 0x00 "PDMA_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel 2"
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hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
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group.long 0x5C++0x03
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line.long 0x00 "PDMA_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel 3"
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hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
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group.long 0x60++0x03
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line.long 0x00 "PDMA_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel 4"
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hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
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group.long 0x400++0x03
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line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register"
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bitfld.long 0x00 4. "CHEN4,PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 3. "CHEN3,PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 2. "CHEN2,PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 1. "CHEN1,PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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bitfld.long 0x00 0. "CHEN0,PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
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wgroup.long 0x404++0x03
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line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register"
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bitfld.long 0x00 4. "PAUSE4,PDMA Channel N Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 3. "PAUSE3,PDMA Channel N Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 2. "PAUSE2,PDMA Channel N Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 1. "PAUSE1,PDMA Channel N Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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bitfld.long 0x00 0. "PAUSE0,PDMA Channel N Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
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wgroup.long 0x408++0x03
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line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register"
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bitfld.long 0x00 4. "SWREQ4,PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 3. "SWREQ3,PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 2. "SWREQ2,PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 1. "SWREQ1,PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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bitfld.long 0x00 0. "SWREQ0,PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active" "0: No effect,1: Generate a software request"
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rgroup.long 0x40C++0x03
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line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register"
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bitfld.long 0x00 4. "REQSTS4,PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 3. "REQSTS3,PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 2. "REQSTS2,PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 1. "REQSTS1,PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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bitfld.long 0x00 0. "REQSTS0,PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
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group.long 0x410++0x03
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line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
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bitfld.long 0x00 4. "FPRISET4,PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 3. "FPRISET3,PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 2. "FPRISET2,PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 1. "FPRISET1,PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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bitfld.long 0x00 0. "FPRISET0,PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.."
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wgroup.long 0x414++0x03
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line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
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bitfld.long 0x00 4. "FPRICLR4,PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 3. "FPRICLR3,PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 2. "FPRICLR2,PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 1. "FPRICLR1,PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x00 0. "FPRICLR0,PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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group.long 0x418++0x03
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line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register"
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bitfld.long 0x00 4. "INTEN4,PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 3. "INTEN3,PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 2. "INTEN2,PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 1. "INTEN1,PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x00 0. "INTEN0,PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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group.long 0x41C++0x03
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line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register"
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bitfld.long 0x00 9. "REQTOF1,PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits" "0: No request time-out,1: Peripheral request time-out"
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bitfld.long 0x00 8. "REQTOF0,PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits" "0: No request time-out,1: Peripheral request time-out"
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rbitfld.long 0x00 2. "TEIF,Table Empty Interrupt Flag (Read Only)\nThis bit indicates PDMA channel scatter-gather table is empty" "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty"
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rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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group.long 0x420++0x03
|
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line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x00 4. "ABTIF4,PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 3. "ABTIF3,PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 2. "ABTIF2,PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 1. "ABTIF1,PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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bitfld.long 0x00 0. "ABTIF0,PDMA Channel N Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.."
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group.long 0x424++0x03
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line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0x00 4. "TDIF4,PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 3. "TDIF3,PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 2. "TDIF2,PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 1. "TDIF1,PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0x00 0. "TDIF0,PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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group.long 0x428++0x03
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line.long 0x00 "PDMA_SCATSTS,PDMA Scatter-gather Table Empty Status Register"
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bitfld.long 0x00 4. "TEMPTYF4,Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty.."
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bitfld.long 0x00 3. "TEMPTYF3,Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty.."
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bitfld.long 0x00 2. "TEMPTYF2,Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty.."
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bitfld.long 0x00 1. "TEMPTYF1,Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty.."
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bitfld.long 0x00 0. "TEMPTYF0,Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty.."
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rgroup.long 0x42C++0x03
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line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x00 4. "TXACTF4,PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 3. "TXACTF3,PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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newline
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bitfld.long 0x00 2. "TXACTF2,PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x00 1. "TXACTF1,PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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newline
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bitfld.long 0x00 0. "TXACTF0,PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is not finished,1: PDMA channel is active"
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group.long 0x430++0x03
|
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line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register"
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bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.."
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bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.."
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group.long 0x434++0x03
|
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line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register"
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bitfld.long 0x00 1. "TOUTEN1,PDMA Channel N Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x00 0. "TOUTEN0,PDMA Channel N Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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group.long 0x438++0x03
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line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register"
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bitfld.long 0x00 1. "TOUTIEN1,PDMA Channel N Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x00 0. "TOUTIEN0,PDMA Channel N Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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group.long 0x43C++0x03
|
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line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode this is the base address for calculating the next link - list address"
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group.long 0x440++0x03
|
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line.long 0x00 "PDMA_TOC0_1,PDMA Channel 0 and Channel 1 Time-out Counter Register"
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hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1"
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hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0"
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group.long 0x460++0x03
|
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line.long 0x00 "PDMA_RESET,PDMA Channel Reset Control Register"
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bitfld.long 0x00 4. "RESET4,PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process" "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x00 3. "RESET3,PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process" "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x00 2. "RESET2,PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process" "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x00 1. "RESET1,PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process" "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x00 0. "RESET0,PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process" "0: No effect,1: Reset PDMA channel n"
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group.long 0x480++0x03
|
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line.long 0x00 "PDMA_REQSEL0_3,PDMA Channel 0 to Channel 3 Request Source Select Register"
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bitfld.long 0x00 24.--29. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0: Disable PDMA,?,?,?,4: Channel connects to UART0_TX,5: Channel connects to UART0_RX,6: Channel connects to UART1_TX,7: Channel connects to UART1_RX,8: Channel connects to UART2_TX,9: Channel connects to UART2_RX,?,?,?,?,?,?,16: Channel connects to SPI0_TX,17: Channel connects to SPI0_RX,18: Channel connects to SPI1_TX,19: Channel connects to SPI1_RX,20: Channel connects to ADC_RX,21: Channel connects to PWM0_P1_RX,22: Channel connects to PWM0_P2_RX,23: Channel connects to PWM0_P3_RX,24: Channel connects to PWM1_P1_RX,25: Channel connects to PWM1_P2_RX,26: Channel connects to PWM1_P3_RX,?,28: Channel connects to I2C0_TX,29: Channel connects to I2C0_RX,30: Channel connects to I2C1_TX,31: Channel connects to I2C1_RX,32: Channel connects to TMR0,33: Channel connects to TMR1,34: Channel connects to TMR2,35: Channel connects to TMR3,?..."
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group.long 0x484++0x03
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line.long 0x00 "PDMA_REQSEL4,PDMA Channel 4 Request Source Select Register"
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bitfld.long 0x00 0.--5. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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tree "PWM"
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repeat 2. (list 0. 1.) (list ad:0x40040000 ad:0x40140000)
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tree "PWM$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "PWM_CTL0,PWM Control Register 0"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x00 24. "GROUPEN,Group Function Enable Bit" "0: The output waveform of each PWM channel are..,1: Unify the PWMx_CH2 and PWMx_CH4 to output the.."
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bitfld.long 0x00 21. "IMMLDEN5,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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newline
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bitfld.long 0x00 20. "IMMLDEN4,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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bitfld.long 0x00 19. "IMMLDEN3,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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newline
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bitfld.long 0x00 18. "IMMLDEN2,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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bitfld.long 0x00 17. "IMMLDEN1,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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newline
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bitfld.long 0x00 16. "IMMLDEN0,Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled WINLDENn bit and CTRLDn bits will be invalid" "0: PERIODn register will load to PBUFn register..,1: PERIODn/CMPDATn registers will load to PBUFn.."
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bitfld.long 0x00 13. "WINLDEN5,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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newline
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bitfld.long 0x00 12. "WINLDEN4,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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bitfld.long 0x00 11. "WINLDEN3,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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newline
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bitfld.long 0x00 10. "WINLDEN2,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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bitfld.long 0x00 9. "WINLDEN1,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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newline
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bitfld.long 0x00 8. "WINLDEN0,Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PERIODn register will load to PBUFn register..,1: PERIODn register will load to PBUFn and.."
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bitfld.long 0x00 5. "CTRLD5,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 4. "CTRLD4,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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bitfld.long 0x00 3. "CTRLD3,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 2. "CTRLD2,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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bitfld.long 0x00 1. "CTRLD1,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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newline
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bitfld.long 0x00 0. "CTRLD0,Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type PERIODn register will load to PBUFn register at the end point of each period" "0,1"
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group.long 0x04++0x03
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line.long 0x00 "PWM_CTL1,PWM Control Register 1"
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bitfld.long 0x00 26. "OUTMODE4,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 25. "OUTMODE2,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode"
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newline
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bitfld.long 0x00 24. "OUTMODE0,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 21. "CNTMODE5,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 20. "CNTMODE4,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 19. "CNTMODE3,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 18. "CNTMODE2,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 17. "CNTMODE1,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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newline
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bitfld.long 0x00 16. "CNTMODE0,PWM Counter Mode\nEach bit n controls the corresponding PWM channel n" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 10.--11. "CNTTYPE5,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 8.--9. "CNTTYPE4,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 6.--7. "CNTTYPE3,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 4.--5. "CNTTYPE2,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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bitfld.long 0x00 2.--3. "CNTTYPE1,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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newline
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bitfld.long 0x00 0.--1. "CNTTYPE0,PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved"
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group.long 0x08++0x03
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line.long 0x00 "PWM_SYNC,PWM Synchronization Register"
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bitfld.long 0x00 26. "PHSDIR4,PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n" "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.."
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bitfld.long 0x00 25. "PHSDIR2,PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n" "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.."
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newline
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bitfld.long 0x00 24. "PHSDIR0,PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n" "0: Control PWM counter count decrement after..,1: Control PWM counter count increment after.."
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bitfld.long 0x00 23. "SINPINV,SYNC Input Pin Inverse" "0: The state of PWM0_SYNC_IN pin is passed to..,1: The inversed state of PWM0_SYNC_IN pin is.."
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newline
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bitfld.long 0x00 20.--22. "SFLTCNT,SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "SFLTCSEL,SYNC Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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newline
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bitfld.long 0x00 16. "SNFLTEN,PWM0_SYNC_IN Noise Filter Enable Bit" "0: Noise filter of input PWM0_SYNC_IN pin Disabled,1: Noise filter of input PWM0_SYNC_IN pin Enabled"
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bitfld.long 0x00 12.--13. "SINSRC4,PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to PWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT signal will not be generated"
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newline
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bitfld.long 0x00 10.--11. "SINSRC2,PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to PWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT signal will not be generated"
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bitfld.long 0x00 8.--9. "SINSRC0,PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n" "0: Synchronize source from SYNC_IN or SWSYNC,1: Counter equal to 0,2: Counter equal to PWM_CMPDATm m denotes 1 3 5,3: SYNC_OUT signal will not be generated"
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newline
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bitfld.long 0x00 2. "PHSEN4,SYNC Phase Enable Bits\nn denotes PWM channel 0 2 4 and m denotes channel 1 3 5" "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.."
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bitfld.long 0x00 1. "PHSEN2,SYNC Phase Enable Bits\nn denotes PWM channel 0 2 4 and m denotes channel 1 3 5" "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.."
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newline
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bitfld.long 0x00 0. "PHSEN0,SYNC Phase Enable Bits\nn denotes PWM channel 0 2 4 and m denotes channel 1 3 5" "0: PWM counter disable to load value of..,1: PWM counter enable to load value of.."
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group.long 0x0C++0x03
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line.long 0x00 "PWM_SWSYNC,PWM Software Control Synchronization Register"
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bitfld.long 0x00 2. "SWSYNC4,Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit" "0,1"
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bitfld.long 0x00 1. "SWSYNC2,Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit" "0,1"
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newline
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bitfld.long 0x00 0. "SWSYNC0,Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0 SYNC_OUT source is come from SYNC_IN or this bit" "0,1"
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group.long 0x10++0x03
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line.long 0x00 "PWM_CLKSRC,PWM Clock Source Register"
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bitfld.long 0x00 16.--18. "ECLKSRC4,PWMx_CH4/5 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,2: TIMER1 time-out event,3: TIMER2 time-out event,4: TIMER3 time-out event,?..."
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bitfld.long 0x00 8.--10. "ECLKSRC2,PWMx_CH2/3 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,2: TIMER1 time-out event,3: TIMER2 time-out event,4: TIMER3 time-out event,?..."
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newline
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bitfld.long 0x00 0.--2. "ECLKSRC0,PWMx_CH0/1 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 time-out event,2: TIMER1 time-out event,3: TIMER2 time-out event,4: TIMER3 time-out event,?..."
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group.long 0x14++0x03
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line.long 0x00 "PWM_CLKPSC0_1,PWM Clock Pre-scale Register 0/1"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler"
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group.long 0x18++0x03
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line.long 0x00 "PWM_CLKPSC2_3,PWM Clock Pre-scale Register 2/3"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler"
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group.long 0x1C++0x03
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line.long 0x00 "PWM_CLKPSC4_5,PWM Clock Pre-scale Register 4/5"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler"
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group.long 0x20++0x03
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line.long 0x00 "PWM_CNTEN,PWM Counter Enable Register"
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bitfld.long 0x00 5. "CNTEN5,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x00 4. "CNTEN4,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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newline
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bitfld.long 0x00 3. "CNTEN3,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x00 2. "CNTEN2,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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newline
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bitfld.long 0x00 1. "CNTEN1,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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bitfld.long 0x00 0. "CNTEN0,PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running"
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group.long 0x24++0x03
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line.long 0x00 "PWM_CNTCLR,PWM Clear Counter Register"
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bitfld.long 0x00 5. "CNTCLR5,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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bitfld.long 0x00 4. "CNTCLR4,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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newline
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bitfld.long 0x00 3. "CNTCLR3,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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bitfld.long 0x00 2. "CNTCLR2,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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newline
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bitfld.long 0x00 1. "CNTCLR1,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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bitfld.long 0x00 0. "CNTCLR0,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to.."
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group.long 0x28++0x03
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line.long 0x00 "PWM_LOAD,PWM Load Register"
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bitfld.long 0x00 5. "LOAD5,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 4. "LOAD4,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x00 3. "LOAD3,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 2. "LOAD2,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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newline
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bitfld.long 0x00 1. "LOAD1,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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bitfld.long 0x00 0. "LOAD0,Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write and hardware clear when current PWM period end" "0: No effect.\nNo load window is set,1: Set load window of window loading mode.\nLoad.."
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group.long 0x30++0x03
|
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line.long 0x00 "PWM_PERIOD0,PWM Period Register 0"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x34++0x03
|
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line.long 0x00 "PWM_PERIOD1,PWM Period Register 1"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x38++0x03
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line.long 0x00 "PWM_PERIOD2,PWM Period Register 2"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x3C++0x03
|
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line.long 0x00 "PWM_PERIOD3,PWM Period Register 3"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x40++0x03
|
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line.long 0x00 "PWM_PERIOD4,PWM Period Register 4"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x44++0x03
|
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line.long 0x00 "PWM_PERIOD5,PWM Period Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: \nIn this mode PWM counter counts from 0 to PERIOD and restarts from 0"
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group.long 0x50++0x03
|
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line.long 0x00 "PWM_CMPDAT0,PWM Comparator Register 0"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x54++0x03
|
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line.long 0x00 "PWM_CMPDAT1,PWM Comparator Register 1"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x58++0x03
|
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line.long 0x00 "PWM_CMPDAT2,PWM Comparator Register 2"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x5C++0x03
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line.long 0x00 "PWM_CMPDAT3,PWM Comparator Register 3"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x60++0x03
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line.long 0x00 "PWM_CMPDAT4,PWM Comparator Register 4"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x64++0x03
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line.long 0x00 "PWM_CMPDAT5,PWM Comparator Register 5"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform interrupt and trigger ADC.\nIn independent mode CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode.."
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group.long 0x70++0x03
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line.long 0x00 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
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group.long 0x74++0x03
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line.long 0x00 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
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group.long 0x78++0x03
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line.long 0x00 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from PWMx_CLK without..,1: Dead-time clock source from prescaler output.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (PWMx_CH0 PWMx_CH1) (PWMx_CH2 PWMx_CH3) (PWMx_CH4 PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected"
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group.long 0x80++0x03
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line.long 0x00 "PWM_PHS0_1,PWM Counter Phase Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value"
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group.long 0x84++0x03
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line.long 0x00 "PWM_PHS2_3,PWM Counter Phase Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value"
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group.long 0x88++0x03
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line.long 0x00 "PWM_PHS4_5,PWM Counter Phase Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "PHS,PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value"
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rgroup.long 0x90++0x03
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line.long 0x00 "PWM_CNT0,PWM Counter Register 0"
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bitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x94++0x03
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line.long 0x00 "PWM_CNT1,PWM Counter Register 1"
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rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x98++0x03
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line.long 0x00 "PWM_CNT2,PWM Counter Register 2"
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rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0x9C++0x03
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line.long 0x00 "PWM_CNT3,PWM Counter Register 3"
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rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA0++0x03
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line.long 0x00 "PWM_CNT4,PWM Counter Register 4"
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rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xA4++0x03
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line.long 0x00 "PWM_CNT5,PWM Counter Register 5"
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rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is Down count,1: Counter is UP count"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter"
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group.long 0xB0++0x03
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line.long 0x00 "PWM_WGCTL0,PWM Generation Register 0"
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bitfld.long 0x00 26.--27. "PRDPCTL5,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 24.--25. "PRDPCTL4,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 22.--23. "PRDPCTL3,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 20.--21. "PRDPCTL2,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 18.--19. "PRDPCTL1,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 16.--17. "PRDPCTL0,PWM Period (Center) Point Control\nPWM can control output level on period(center) point event" "0: Do nothing,1: PWM period (center) point output Low,2: PWM period (center) point output High,3: PWM period (center) point output Toggle"
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bitfld.long 0x00 10.--11. "ZPCTL5,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 8.--9. "ZPCTL4,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 6.--7. "ZPCTL3,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 4.--5. "ZPCTL2,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 2.--3. "ZPCTL1,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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bitfld.long 0x00 0.--1. "ZPCTL0,PWM Zero Point Control\nPWM can control output level on zero point event" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle"
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group.long 0xB4++0x03
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line.long 0x00 "PWM_WGCTL1,PWM Generation Register 1"
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bitfld.long 0x00 26.--27. "CMPDCTL5,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 24.--25. "CMPDCTL4,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 22.--23. "CMPDCTL3,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 20.--21. "CMPDCTL2,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 18.--19. "CMPDCTL1,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 16.--17. "CMPDCTL0,PWM Compare Down Point Control\nPWM can control output level on compare down point event" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle"
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bitfld.long 0x00 10.--11. "CMPUCTL5,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 8.--9. "CMPUCTL4,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 6.--7. "CMPUCTL3,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 4.--5. "CMPUCTL2,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 2.--3. "CMPUCTL1,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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bitfld.long 0x00 0.--1. "CMPUCTL0,PWM Compare Up Point Control\nPWM can control output level on compare up point event" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle"
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group.long 0xB8++0x03
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line.long 0x00 "PWM_MSKEN,PWM Mask Enable Register"
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bitfld.long 0x00 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.."
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group.long 0xBC++0x03
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line.long 0x00 "PWM_MSK,PWM Mask Data Register"
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bitfld.long 0x00 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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bitfld.long 0x00 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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bitfld.long 0x00 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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bitfld.long 0x00 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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bitfld.long 0x00 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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bitfld.long 0x00 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin if corresponding mask function is enabled" "0: Output logic low to PWMx_CHn,1: Output logic high to PWMx_CHn"
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group.long 0xC0++0x03
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line.long 0x00 "PWM_BNF,PWM Brake Noise Filter Register"
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bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting" "0: Brake 1 pin source come from..,1: Brake 1 pin source come from.."
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bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting" "0: Brake 0 pin source come from..,1: Brake 0 pin source come from.."
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bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled"
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bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: Brake pin event will be detected if..,1: Brake pin event will be detected if.."
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bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128"
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bitfld.long 0x00 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled"
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group.long 0xC4++0x03
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line.long 0x00 "PWM_FAILBRK,PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by Core lockup event..,1: Brake Function triggered by Core lockup event.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0xC8++0x03
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line.long 0x00 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1"
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bitfld.long 0x00 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx..,2: PWM odd channel output low level when PWMx..,3: PWM odd channel output high level when PWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect even..,1: PWM even channel output tri-state when PWMx..,2: PWM even channel output low level when PWMx..,3: PWM even channel output high level when PWMx.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xCC++0x03
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line.long 0x00 "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3"
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bitfld.long 0x00 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx..,2: PWM odd channel output low level when PWMx..,3: PWM odd channel output high level when PWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect even..,1: PWM even channel output tri-state when PWMx..,2: PWM even channel output low level when PWMx..,3: PWM even channel output high level when PWMx.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD0++0x03
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line.long 0x00 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5"
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bitfld.long 0x00 28. "ADCLBEN,Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as level-detect brake source Disabled,1: ADCRM as level-detect brake source Enabled"
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bitfld.long 0x00 20. "ADCEBEN,Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ADCRM as edge-detect brake source Disabled,1: ADCRM as edge-detect brake source Enabled"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect odd channels..,1: PWM odd channel output tri-state when PWMx..,2: PWM odd channel output low level when PWMx..,3: PWM odd channel output high level when PWMx.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected" "0: PWMx brake event will not affect even..,1: PWM even channel output tri-state when PWMx..,2: PWM even channel output low level when PWMx..,3: PWM even channel output high level when PWMx.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.."
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bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.."
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bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled"
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bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled"
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.."
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bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE1 pin as edge-detect brake source..,1: PWMx_BRAKE1 pin as edge-detect brake source.."
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bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: PWMx_BRAKE0 pin as edge-detect brake source..,1: PWMx_BRAKE0 pin as edge-detect brake source.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled"
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bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled"
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group.long 0xD4++0x03
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line.long 0x00 "PWM_POLCTL,PWM Pin Polar Inverse Register"
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bitfld.long 0x00 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin" "0: PWMx_CHn output pin polar inverse Disabled,1: PWMx_CHn output pin polar inverse Enabled"
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group.long 0xD8++0x03
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line.long 0x00 "PWM_POEN,PWM Output Enable Register"
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bitfld.long 0x00 5. "POEN5,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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bitfld.long 0x00 4. "POEN4,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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bitfld.long 0x00 3. "POEN3,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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bitfld.long 0x00 2. "POEN2,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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bitfld.long 0x00 1. "POEN1,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWMx_CHn pin at tri-state,1: PWMx_CHn pin in output mode"
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wgroup.long 0xDC++0x03
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line.long 0x00 "PWM_SWBRK,PWM Software Brake Control Register"
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bitfld.long 0x00 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn bits to 1 in PWM_INTSTS1 register" "0,1"
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group.long 0xE0++0x03
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line.long 0x00 "PWM_INTEN0,PWM Interrupt Enable Register 0"
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bitfld.long 0x00 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 23. "IFAIEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 15. "IFAIEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 13. "PIEN5,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 12. "PIEN4,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 11. "PIEN3,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 10. "PIEN2,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 9. "PIEN1,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 8. "PIEN0,PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 7. "IFAIEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit" "0: Interrupt Flag accumulator interrupt Disabled,1: Interrupt Flag accumulator interrupt Enabled"
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bitfld.long 0x00 5. "ZIEN5,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 4. "ZIEN4,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 3. "ZIEN3,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 2. "ZIEN2,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 1. "ZIEN1,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN0,PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE4++0x03
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line.long 0x00 "PWM_INTEN1,PWM Interrupt Enable Register 1"
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bitfld.long 0x00 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.."
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bitfld.long 0x00 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.."
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bitfld.long 0x00 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.."
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bitfld.long 0x00 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.."
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group.long 0xE8++0x03
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line.long 0x00 "PWM_INTSTS0,PWM Interrupt Flag Register 0"
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bitfld.long 0x00 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 23. "IFAIF4_5,PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 21. "CMPUIF5,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 20. "CMPUIF4,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 19. "CMPUIF3,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 18. "CMPUIF2,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 17. "CMPUIF1,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 16. "CMPUIF0,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]) software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 15. "IFAIF2_3,PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 13. "PIF5,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 12. "PIF4,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 11. "PIF3,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 10. "PIF2,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 9. "PIF1,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 8. "PIF0,PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]) software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 7. "IFAIF0_1,PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register software can clear this bit by writing 1 to it" "0,1"
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bitfld.long 0x00 5. "ZIF5,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 4. "ZIF4,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 3. "ZIF3,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 2. "ZIF2,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 1. "ZIF1,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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bitfld.long 0x00 0. "ZIF0,PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero software can write 1 to clear this bit to zero" "0,1"
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group.long 0xEC++0x03
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line.long 0x00 "PWM_INTSTS1,PWM Interrupt Flag Register 1"
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rbitfld.long 0x00 29. "BRKLSTS5,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 28. "BRKLSTS4,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 27. "BRKLSTS3,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 26. "BRKLSTS2,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 25. "BRKLSTS1,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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rbitfld.long 0x00 24. "BRKLSTS0,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.."
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bitfld.long 0x00 21. "BRKESTS5,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 20. "BRKESTS4,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 19. "BRKESTS3,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 18. "BRKESTS2,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 17. "BRKESTS1,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 16. "BRKESTS0,PWM Channel N Edge-detect Brake Status" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.."
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bitfld.long 0x00 8. "BRKLIFn,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.."
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bitfld.long 0x00 5. "BRKEIF5,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 4. "BRKEIF4,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 3. "BRKEIF3,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 2. "BRKEIF2,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 1. "BRKEIF1,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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bitfld.long 0x00 0. "BRKEIF0,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.."
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group.long 0xF0++0x03
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line.long 0x00 "PWM_IFA,PWM Interrupt Flag Accumulator Register"
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bitfld.long 0x00 23. "IFAEN4_5,PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 4/5 interrupt flag accumulator..,1: PWM Channel 4/5 interrupt flag accumulator.."
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bitfld.long 0x00 20.--22. "IFSEL4_5,PWM Channel 4/5 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 4,1: CNT equal to PERIOD in channel 4,2: CNT equal to CMPU in channel 4,3: CNT equal to CMPD in channel 4,4: CNT equal to Zero in channel 5,5: CNT equal to PERIOD in channel 5,6: CNT equal to CMPU in channel 5,7: CNT equal to CMPD in channel 5"
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bitfld.long 0x00 16.--19. "IFCNT4_5,PWM Channel 4/5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "IFAEN2_3,PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 2/3 interrupt flag accumulator..,1: PWM Channel 2/3 interrupt flag accumulator.."
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bitfld.long 0x00 12.--14. "IFSEL2_3,PWM Channel 2/3 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 2,1: CNT equal to PERIOD in channel 2,2: CNT equal to CMPU in channel 2,3: CNT equal to CMPD in channel 2,4: CNT equal to Zero in channel 3,5: CNT equal to PERIOD in channel 3,6: CNT equal to CMPU in channel 3,7: CNT equal to CMPD in channel 3"
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bitfld.long 0x00 8.--11. "IFCNT2_3,PWM Channel 2/3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "IFAEN0_1,PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit" "0: PWM Channel 0/1 interrupt flag accumulator..,1: PWM Channel 0/1 interrupt flag accumulator.."
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bitfld.long 0x00 4.--6. "IFSEL0_1,PWM Channel 0/1 Interrupt Flag Accumulator Source Select" "0: CNT equal to Zero in channel 0,1: CNT equal to PERIOD in channel 0,2: CNT equal to CMPU in channel 0,3: CNT equal to CMPD in channel 0,4: CNT equal to Zero in channel 1,5: CNT equal to PERIOD in channel 1,6: CNT equal to CMPU in channel 1,7: CNT equal to CMPD in channel 1"
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bitfld.long 0x00 0.--3. "IFCNT0_1,PWM Channel 0/1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xF8++0x03
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line.long 0x00 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0"
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bitfld.long 0x00 31. "TRGEN3,PWM_CH3 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 24.--27. "TRGSEL3,PWM_CH3 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count compared point,4: PWM_CH2 down-count compared point,5: PWM_CH3 zero point,6: PWM_CH3 period point,7: PWM_CH3 zero or period point,8: PWM_CH3 up-count compared point,9: PWM_CH3 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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bitfld.long 0x00 23. "TRGEN2,PWM_CH2 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 16.--19. "TRGSEL2,PWM_CH2 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count compared point,4: PWM_CH2 down-count compared point,5: PWM_CH3 zero point,6: PWM_CH3 period point,7: PWM_CH3 zero or period point,8: PWM_CH3 up-count compared point,9: PWM_CH3 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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bitfld.long 0x00 15. "TRGEN1,PWM_CH1 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL1,PWM_CH1 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count compared point,4: PWM_CH0 down-count compared point,5: PWM_CH1 zero point,6: PWM_CH1 period point,7: PWM_CH1 zero or period point,8: PWM_CH1 up-count compared point,9: PWM_CH1 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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bitfld.long 0x00 7. "TRGEN0,PWM_CH0 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL0,PWM_CH0 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count compared point,4: PWM_CH0 down-count compared point,5: PWM_CH1 zero point,6: PWM_CH1 period point,7: PWM_CH1 zero or period point,8: PWM_CH1 up-count compared point,9: PWM_CH1 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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group.long 0xFC++0x03
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line.long 0x00 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1"
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bitfld.long 0x00 15. "TRGEN5,PWM_CH5 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 8.--11. "TRGSEL5,PWM_CH5 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count compared point,4: PWM_CH4 down-count compared point,5: PWM_CH5 zero point,6: PWM_CH5 period point,7: PWM_CH5 zero or period point,8: PWM_CH5 up-count compared point,9: PWM_CH5 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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bitfld.long 0x00 7. "TRGEN4,PWM_CH4 Trigger ADC enable bit" "0,1"
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bitfld.long 0x00 0.--3. "TRGSEL4,PWM_CH4 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count compared point,4: PWM_CH4 down-count compared point,5: PWM_CH5 zero point,6: PWM_CH5 period point,7: PWM_CH5 zero or period point,8: PWM_CH5 up-count compared point,9: PWM_CH5 down-count compared point,10: PWM_CH0 up-count free trigger compared point,11: PWM_CH0 down-count free trigger compared point,12: PWM_CH2 up-count free trigger compared point,13: PWM_CH2 down-count free trigger compared point,14: PWM_CH4 up-count free trigger compared point,15: PWM_CH4 down-count free trigger compared point"
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group.long 0x100++0x03
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line.long 0x00 "PWM_FTCMPDAT0_1,PWM Free Trigger Compare Register 0/1"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register"
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group.long 0x104++0x03
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line.long 0x00 "PWM_FTCMPDAT2_3,PWM Free Trigger Compare Register 2/3"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register"
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group.long 0x108++0x03
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line.long 0x00 "PWM_FTCMPDAT4_5,PWM Free Trigger Compare Register 4/5"
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hexmask.long.word 0x00 0.--15. 1. "FTCMP,PWM Free Trigger Compare Register"
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group.long 0x110++0x03
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line.long 0x00 "PWM_SSCTL,PWM Synchronous Start Control Register"
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bitfld.long 0x00 8. "SSRC,PWM Synchronous Start Source Select Bit" "0: Synchronous start source come from PWM0,1: Synchronous start source come from PWM1"
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bitfld.long 0x00 5. "SSEN5,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 4. "SSEN4,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 3. "SSEN3,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 2. "SSEN2,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 1. "SSEN1,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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bitfld.long 0x00 0. "SSEN0,PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled"
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wgroup.long 0x114++0x03
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line.long 0x00 "PWM_SSTRG,PWM Synchronous Start Trigger Register"
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bitfld.long 0x00 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn n.." "0,1"
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group.long 0x118++0x03
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line.long 0x00 "PWM_LEBCTL,PWM Leading Edge Blanking Control Register"
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bitfld.long 0x00 16.--17. "TRGTYPE,PWM Leading Edge Blanking Trigger Type" "0: When detect leading edge blanking source..,1: When detect leading edge blanking source..,2: When detect leading edge blanking source..,3: Reserved"
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bitfld.long 0x00 10. "SRCEN4,PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit" "0: PWM Leading Edge Blanking Source from..,1: PWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 9. "SRCEN2,PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit" "0: PWM Leading Edge Blanking Source from..,1: PWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 8. "SRCEN0,PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit" "0: PWM Leading Edge Blanking Source from..,1: PWM Leading Edge Blanking Source from.."
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bitfld.long 0x00 0. "LEBEN,PWM Leading Edge Blanking Enable Bit" "0: PWM Leading Edge Blanking Disabled,1: PWM Leading Edge Blanking Enabled"
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group.long 0x11C++0x03
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line.long 0x00 "PWM_LEBCNT,PWM Leading Edge Blanking Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "LEBCNT,PWM Leading Edge Blanking Counter\nThis counter value decides leading edge blanking window size"
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group.long 0x120++0x03
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line.long 0x00 "PWM_STATUS,PWM Status Register"
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bitfld.long 0x00 21. "ADCTRGF5,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 20. "ADCTRGF4,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 19. "ADCTRGF3,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 18. "ADCTRGF2,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 17. "ADCTRGF1,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 16. "ADCTRGF0,ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no ADC start of conversion trigger..,1: Indicates an ADC start of conversion trigger.."
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bitfld.long 0x00 10. "SYNCINF4,Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred.."
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bitfld.long 0x00 9. "SYNCINF2,Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred.."
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bitfld.long 0x00 8. "SYNCINF0,Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: Indicates no SYNC_IN event has occurred,1: Indicates an SYNC_IN event has occurred.."
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bitfld.long 0x00 5. "CNTMAXF5,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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bitfld.long 0x00 4. "CNTMAXF4,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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bitfld.long 0x00 3. "CNTMAXF3,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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bitfld.long 0x00 2. "CNTMAXF2,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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bitfld.long 0x00 1. "CNTMAXF1,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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bitfld.long 0x00 0. "CNTMAXF0,Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n" "0: indicates the time-base..,1: indicates the time-base.."
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group.long 0x200++0x03
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line.long 0x00 "PWM_CAPINEN,PWM Capture Input Enable Register"
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bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
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group.long 0x204++0x03
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line.long 0x00 "PWM_CAPCTL,PWM Capture Control Register"
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bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
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bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n" "0: Capture function Disabled,1: Capture function Enabled"
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rgroup.long 0x208++0x03
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line.long 0x00 "PWM_CAPSTS,PWM Capture Status Register"
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bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1" "0,1"
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bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1" "0,1"
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rgroup.long 0x20C++0x03
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line.long 0x00 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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rgroup.long 0x210++0x03
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line.long 0x00 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x214++0x03
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line.long 0x00 "PWM_RCAPDAT1,PWM Rising Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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group.long 0x218++0x03
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line.long 0x00 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x21C++0x03
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line.long 0x00 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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group.long 0x220++0x03
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line.long 0x00 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x224++0x03
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line.long 0x00 "PWM_RCAPDAT3,PWM Rising Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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group.long 0x228++0x03
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line.long 0x00 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x22C++0x03
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line.long 0x00 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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group.long 0x230++0x03
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line.long 0x00 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x234++0x03
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line.long 0x00 "PWM_RCAPDAT5,PWM Rising Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register"
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group.long 0x238++0x03
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line.long 0x00 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5"
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hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register"
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group.long 0x23C++0x03
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line.long 0x00 "PWM_PDMACTL,PWM PDMA Control Register"
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bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer" "0: Channel4,1: Channel5"
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bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3" "0: PWM_FCAPDAT4/5 register is the first captured..,1: PWM_RCAPDAT4/5 register is the first captured.."
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bitfld.long 0x00 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer" "0: Reserved,1: PWM_RCAPDAT4/5 register,2: PWM_FCAPDAT4/5 register,3: Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.."
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bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.."
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bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer" "0: Channel2,1: Channel3"
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bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3" "0: PWM_FCAPDAT2/3 register is the first captured..,1: PWM_RCAPDAT2/3 register is the first captured.."
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bitfld.long 0x00 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer" "0: Reserved,1: PWM_RCAPDAT2/3 register,2: PWM_FCAPDAT2/3 register,3: Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.."
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bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.."
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bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer" "0: Channel0,1: Channel1"
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bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3" "0: PWM_FCAPDAT0/1 register is the first captured..,1: PWM_RCAPDAT0/1 register is the first captured.."
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bitfld.long 0x00 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer" "0: Reserved,1: PWM_RCAPDAT0/1 register,2: PWM_FCAPDAT0/1 register,3: Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.."
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bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.."
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rgroup.long 0x240++0x03
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line.long 0x00 "PWM_PDMACAP0_1,PWM Capture Channel 0/1 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA"
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group.long 0x244++0x03
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line.long 0x00 "PWM_PDMACAP2_3,PWM Capture Channel 2/3 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA"
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group.long 0x248++0x03
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line.long 0x00 "PWM_PDMACAP4_5,PWM Capture Channel 4/5 PDMA Register"
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hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA"
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group.long 0x250++0x03
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line.long 0x00 "PWM_CAPIEN,PWM Capture Interrupt Enable Register"
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bitfld.long 0x00 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPFIENn bit must be disabled" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled"
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bitfld.long 0x00 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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bitfld.long 0x00 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating corresponding channel CAPRIENn bit must be disabled" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled"
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group.long 0x254++0x03
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line.long 0x00 "PWM_CAPIF,PWM Capture Interrupt Flag Register"
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bitfld.long 0x00 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x00 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x00 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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|
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bitfld.long 0x00 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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|
bitfld.long 0x00 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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|
rgroup.long 0x304++0x03
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|
line.long 0x00 "PWM_PBUF0,PWM PERIOD0 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
group.long 0x308++0x03
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|
line.long 0x00 "PWM_PBUF1,PWM PERIOD1 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
group.long 0x30C++0x03
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|
line.long 0x00 "PWM_PBUF2,PWM PERIOD2 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
group.long 0x310++0x03
|
|
line.long 0x00 "PWM_PBUF3,PWM PERIOD3 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
group.long 0x314++0x03
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|
line.long 0x00 "PWM_PBUF4,PWM PERIOD4 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
group.long 0x318++0x03
|
|
line.long 0x00 "PWM_PBUF5,PWM PERIOD5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register"
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|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "PWM_CMPBUF0,PWM CMPDAT0 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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|
group.long 0x320++0x03
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line.long 0x00 "PWM_CMPBUF1,PWM CMPDAT1 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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|
group.long 0x324++0x03
|
|
line.long 0x00 "PWM_CMPBUF2,PWM CMPDAT2 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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|
group.long 0x328++0x03
|
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line.long 0x00 "PWM_CMPBUF3,PWM CMPDAT3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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group.long 0x32C++0x03
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line.long 0x00 "PWM_CMPBUF4,PWM CMPDAT4 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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|
group.long 0x330++0x03
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line.long 0x00 "PWM_CMPBUF5,PWM CMPDAT5 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register"
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|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "PWM_CPSCBUF0_1,PWM CLKPSC0_1 Buffer"
|
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hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register"
|
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group.long 0x338++0x03
|
|
line.long 0x00 "PWM_CPSCBUF2_3,PWM CLKPSC2_3 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register"
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|
group.long 0x33C++0x03
|
|
line.long 0x00 "PWM_CPSCBUF4_5,PWM CLKPSC4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--11. 1. "CPSCBUF,PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register"
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rgroup.long 0x340++0x03
|
|
line.long 0x00 "PWM_FTCBUF0_1,PWM FTCMPDAT0_1 Buffer"
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|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x344++0x03
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line.long 0x00 "PWM_FTCBUF2_3,PWM FTCMPDAT2_3 Buffer"
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hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x348++0x03
|
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line.long 0x00 "PWM_FTCBUF4_5,PWM FTCMPDAT4_5 Buffer"
|
|
hexmask.long.word 0x00 0.--15. 1. "FTCMPBUF,PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register"
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group.long 0x34C++0x03
|
|
line.long 0x00 "PWM_FTCI,PWM FTCMPDAT Indicator Register"
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|
bitfld.long 0x00 10. "FTCMD4,PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit" "0,1"
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bitfld.long 0x00 9. "FTCMD2,PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit" "0,1"
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|
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bitfld.long 0x00 8. "FTCMD0,PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0 software can write 1 to clear this bit" "0,1"
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bitfld.long 0x00 2. "FTCMU4,PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit" "0,1"
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|
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bitfld.long 0x00 1. "FTCMU2,PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit" "0,1"
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bitfld.long 0x00 0. "FTCMU0,PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1 software can write 1 to clear this bit" "0,1"
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tree.end
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repeat.end
|
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tree.end
|
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tree "RTC"
|
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base ad:0x40008000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "RTC_INIT,RTC Initiation Register"
|
|
hexmask.long 0x00 1.--31. 1. "INIT,RTC Initiation\nWhen RTC block is first powered on RTC is at reset state"
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|
rbitfld.long 0x00 0. "INIT_ACTIVE,RTC Active Status (Read Only)" "0: RTC is at reset state,1: RTC is at normal active state"
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|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_RWEN,RTC Access Enable Register"
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|
bitfld.long 0x00 24. "RTCBUSY,RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not.\nNote: RTCBUSY falg will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles" "0: RTC register write Disabled,1: RTC register write Enabled"
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rbitfld.long 0x00 16. "RWENF,RTC Register Access Enable Bit (Read Only)\nNote1: This bit will be set after RWEN is load a 0xA965 and be cleared automatically after 1024 RTC clocks expired.\nNote2: RWENF will be mask to 0 during RTCBUSY is 1 and first turn on RTCCKEN.." "0: RTC register read/write Disabled,1: RTC register read/write Enabled"
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hexmask.long.word 0x00 0.--15. 1. "RWEN,RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this field will enable RTC register access period and keep 1024 RTC clocks.\nNote: Writing others vaule will clear RWENF and disable RTC register access function immediately"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
|
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hexmask.long.tbyte 0x00 0.--21. 1. "FREQADJ,Frequency Compensation Value\nUser has to get actual clock frequency of LXT LXT frequency.\nNote: This formula is suitable only when RTCSEL (CLK_CLKSEL2[18]) is 0 RTC clock source is from LXT"
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group.long 0x0C++0x03
|
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line.long 0x00 "RTC_TIME,RTC Time Loading Register"
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bitfld.long 0x00 20.--21. "TENHR,10-hour Time Digit (0~2)\nNote: When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication RTC_TIME[21] is 0 means AM hour and RTC_TIME[21] is 1 means PM hour" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x10++0x03
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line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit (0~1)" "0,1"
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bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x14++0x03
|
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line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
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bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM register are in 24-hour time scale or 12-hour time scale" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
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group.long 0x18++0x03
|
|
line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
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bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register \nNote: RTC will not check WEEKDAY setting with RTC_CAL is reasonable or not" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,7: Reserved"
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group.long 0x1C++0x03
|
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line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
|
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bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1 it indicates PM time message.)" "0,1,2,3"
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bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0~5)" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x20++0x03
|
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line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
|
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bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0~1)" "0,1"
|
|
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0~3)" "0,1,2,3"
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bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0~9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x24++0x03
|
|
line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indicaton Register"
|
|
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication Register (Read Only)" "0: This year is not a leap year,1: This year is leap year"
|
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group.long 0x28++0x03
|
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line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Bit" "0: RTC time tick interrupt Disabled,1: RTC time tick interrupt Enabled"
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bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Bit" "0: RTC alarm interrupt Disabled,1: RTC alarm interrupt Enabled"
|
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group.long 0x2C++0x03
|
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line.long 0x00 "RTC_INTSTS,RTC Interrupt Status Register"
|
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bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nWhen RTC time tick event happened TICKIF will be set to 1 and a time tick interrupt signal will be generated if TICKIEN (RTC_INTEN[1]) is enabled" "0: Tick condition did not occur,1: Tick condition occurred"
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bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nWhen current RTC counter in RTC_TIME and RTC_CAL are matched RTC alarm settings in RTC_TALM and RTC_CALM ALMIF will be set to 1 and an alarm interrupt signal will be generated if ALMIEN (RTC_INTEN[0]) is enabled" "0: Alarm condition is not matched,1: Alarm condition is matched"
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group.long 0x30++0x03
|
|
line.long 0x00 "RTC_TICK,RTC Time Tick Register"
|
|
bitfld.long 0x00 0.--2. "TICK,Time Tick Register\nThese bits are used to select RTC time tick period for periodic time tick interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/128 second"
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group.long 0x34++0x03
|
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line.long 0x00 "RTC_TAMSK,RTC Time Alarm Mask Register"
|
|
bitfld.long 0x00 5. "MTENHR,Mask 10-hour Time Digit of Alarm Setting (0~2)\nNote: MTENHR function is only for 24-hour time scale mode" "0,1"
|
|
bitfld.long 0x00 4. "MHR,Mask 1-hour Time Digit of Alarm Setting (0~9)\nNote: MHR function is only for 24-hour time scale mode" "0,1"
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|
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bitfld.long 0x00 3. "MTENMIN,Mask 10-Min Time Digit of alarm setting (0~5)" "0,1"
|
|
bitfld.long 0x00 2. "MMIN,Mask 1-Min Time Digit of alarm setting (0~9)" "0,1"
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newline
|
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bitfld.long 0x00 1. "MTENSEC,Mask 10-Sec Time Digit of alarm setting (0~5)" "0,1"
|
|
bitfld.long 0x00 0. "MSEC,Mask 1-Sec Time Digit of alarm setting (0~9)" "0,1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "RTC_CAMSK,RTC Calendar Alarm Mask Register"
|
|
bitfld.long 0x00 5. "MTENYEAR,Mask 10-Year Calendar Digit of alarm setting (0~9)" "0,1"
|
|
bitfld.long 0x00 4. "MYEAR,Mask 1-Year Calendar Digit of alarm setting (0~9)" "0,1"
|
|
newline
|
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bitfld.long 0x00 3. "MTENMON,Mask 10-Month Calendar Digit of alarm setting (0~1)" "0,1"
|
|
bitfld.long 0x00 2. "MMON,Mask 1-Month Calendar Digit of alarm setting (0~9)" "0,1"
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|
newline
|
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bitfld.long 0x00 1. "MTENDAY,Mask 10-Day Calendar Digit of alarm setting (0~3)" "0,1"
|
|
bitfld.long 0x00 0. "MDAY,Mask 1-Day Calendar Digit of alarm setting (0~9)" "0,1"
|
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group.long 0x100++0x03
|
|
line.long 0x00 "RTC_LXTCTL,RTC 32 KHz Oscillator Control Register"
|
|
bitfld.long 0x00 1.--3. "GAIN,Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range" "0: L0 mode,1: L1 mode,2: L2 mode,3: L3 mode,4: L4 mode,5: L5 mode,6: L6 mode,7: L7 mode (Default)"
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group.long 0x104++0x03
|
|
line.long 0x00 "RTC_LXTOCTL,RTC X32KO Pin Control Register"
|
|
bitfld.long 0x00 3. "CTLSEL,I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled X32KO pin can be used as GPIO PF.0 function" "0: X32KO (PF.0) pin I/O function is controlled..,1: X32KO (PF.0) pin I/O function is controlled.."
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|
bitfld.long 0x00 2. "DOUT,I/O Pin Output Data" "0: X32KO (PF.0) will drive low in output mode,1: X32KO (PF.0) will drive high in output mode"
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newline
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bitfld.long 0x00 0.--1. "OPMODE,I/O Pin Operation Mode" "0: X32KO (PF.0) is in Input mode without pull-up..,1: X32KO (PF.0) is in Push-pull output mode,2: X32KO (PF.0) is in Open-drain output mode,3: X32KO (PF.0) is in Input mode with pull-up.."
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "RTC_LXTICTL,RTC X32KI Pin Control Register"
|
|
bitfld.long 0x00 3. "CTLSEL,I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled X32KO pin can be used as GPIO PF.1 function" "0: X32KI (PF.1) pin I/O function is controlled..,1: X32KI (PF.1) pin I/O function is controlled.."
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|
bitfld.long 0x00 2. "DOUT,IO Pin Output Data" "0: X32KI (PF.1) will drive low in output mode,1: X32KI (PF.1) will drive high in output mode"
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newline
|
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bitfld.long 0x00 0.--1. "OPMODE,I/O Pin Operation Mode" "0: X32KI (PF.1) is in Input mode without pull-up..,1: X32KI (PF.1) is in Push-pull output mode,2: X32KI (PF.1) is in Open-drain output mode,3: X32KI (PF.1) is in Input mode with pull-up.."
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RTC_PF2CTL,RTC PF.2 Pin Control Register"
|
|
bitfld.long 0x00 3. "CTLSEL,I/O Pin State Backup Selection\nUser can program CTLSEL to decide GPIO PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when.." "0: GPIO PF.2 pin I/O function is controlled by..,1: GPIO PF.2 pin I/O function is controlled by.."
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|
bitfld.long 0x00 2. "DOUT,I/O Pin Output Data" "0: GPIO PF.2 will drive low in output mode,1: GPIO PF.2 will drive high in output mode"
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|
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|
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bitfld.long 0x00 0.--1. "OPMODE,I/O Pin Operation Mode" "0: PF.2 is in Input mode without pull-up resistor,1: PF.2 is in Push-pull output mode,2: PF.2 is in Open-drain output mode,3: PF.2 is in Input mode with pull-up resistor"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RTC_DSTCTL,RTC Daylight Saving Time Control Register"
|
|
bitfld.long 0x00 2. "DSBAK,Daylight Saving Back" "0: Daylight Saving Time function is not performed,1: Daylight Saving Time function is performed"
|
|
bitfld.long 0x00 1. "SUBHR,Subtract 1 Hour" "0: No effect,1: Indicates RTC hour digit has been subtracted.."
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bitfld.long 0x00 0. "ADDHR,Add 1 Hour" "0: No effect,1: Indicates RTC hour digit has been added one.."
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tree.end
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tree "SC"
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repeat 2. (list 0. 1.) (list ad:0x40190000 ad:0x40194000)
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tree "SC$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "SC_DAT,SC Receive/Transmit Holding Buffer Register"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT the SC will send out an 8-bit data.\nRead Operation:\nBy reading DAT the SC will return an 8-bit received data.\nNote: If SCEN (SC_CTL[0]) is not enabled DAT cannot be.."
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group.long 0x04++0x03
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line.long 0x00 "SC_CTL,SC Control Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit before writing a new value to RXRTY and TXRTY fields" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 26. "CDLV,Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled" "0: When hardware detects the card detect pin..,1: When hardware detects the card detect pin.."
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bitfld.long 0x00 24.--25. "CDDBSEL,Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved" "0: De-bounce sample card insert once per 384..,?..."
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bitfld.long 0x00 23. "TXRTYEN,TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred" "0: TX error retry function Disabled,1: TX error retry function Enabled"
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bitfld.long 0x00 20.--22. "TXRTY,TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. "RXRTYEN,RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit" "0: RX error retry function Disabled,1: RX error retry function Enabled"
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bitfld.long 0x00 16.--18. "RXRTY,RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1 so 8 is the maximum retry number.\nNote2: This field cannot be.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 15. "NSB,Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2" "0: The stop bit length is 2 ETU,1: The stop bit length is 1 ETU"
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bitfld.long 0x00 13.--14. "TMRSEL,Timer Channel Selection \nOther configurations are reserved" "0: All internal timer function Disabled,?,?,3: Internal 24-bit Timer0 and two 8-bit Timer0.."
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bitfld.long 0x00 8.--12. "BGT,Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 6.--7. "RXTRGLV,Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV the RDAIF (SC_INTSTS[0]) will be set" "0: Rx Buffer Trigger Level with 01 bytes,1: Rx Buffer Trigger Level with 02 bytes,2: Rx Buffer Trigger Level with 03 bytes,3: Reserved"
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bitfld.long 0x00 4.--5. "CONSEL,Convention Selection\nNote: If AUTOCEN (SC_CTL[3]) is enabled this field is ignored" "0: Direct convention,1: Reserved,2: Reserved,3: Inverse convention"
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bitfld.long 0x00 3. "AUTOCEN,Auto Convention Enable Bit\nThis bit is used to enable auto convention function.\nNote1: If user enables auto convention function the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F" "0: Auto-convention Disabled,1: Auto-convention Enabled"
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bitfld.long 0x00 2. "TXOFF,TX Transition Disable Bit\nThis bit is used to disable Tx transmit function" "0: The transceiver Enabled,1: The transceiver Disabled"
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bitfld.long 0x00 1. "RXOFF,RX Transition Disable Bit\nThis bit is used to disable Rx receive function.\nNote: If AUTOCEN (SC_CTL[3]) is enabled this field is ignored" "0: The receiver Enabled,1: The receiver Disabled"
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bitfld.long 0x00 0. "SCEN,SC Controller Enable Bit\nSet this bit to 1 to enable SC operation function.\nNote: SCEN must be set to 1 before filling in other SC registers or smart card will not work properly" "0: SC will force all transition to IDLE state,1: SC controller is enabled and all function can.."
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group.long 0x08++0x03
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line.long 0x00 "SC_ALTCTL,SC Alternate Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SC_ALTCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 15. "ACTSTS2,Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SC_TMRCTL2[7:0])" "0: Timer2 is not active,1: Timer2 is active"
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rbitfld.long 0x00 14. "ACTSTS1,Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SC_TMRCTL1[7:0])" "0: Timer1 is not active,1: Timer1 is active"
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rbitfld.long 0x00 13. "ACTSTS0,Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SC_TMRCTL0[23:0])" "0: Timer0 is not active,1: Timer0 is active"
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bitfld.long 0x00 12. "RXBGTEN,Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function" "0: Receiver block guard time function Disabled,1: Receiver block guard time function Enabled"
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bitfld.long 0x00 11. "ADACEN,Auto Deactivation When Card Removal\nThis bit is usde for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed hardware will stop any process and then do deactivation sequence if this bit is set" "0: Auto deactivation Disabled,1: Auto deactivation Enabled"
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bitfld.long 0x00 8.--9. "INITSEL,Initial Timing Selection\nThis fields indicates the initial timing of hardware activation warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Figure 6.154.\nWarm-reset:.." "0,1,2,3"
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bitfld.long 0x00 7. "CNTEN2,Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting" "0: Stop counting,1: Start counting"
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bitfld.long 0x00 6. "CNTEN1,Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting" "0: Stop counting,1: Start counting"
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bitfld.long 0x00 5. "CNTEN0,Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting" "0: Stop counting,1: Start counting"
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bitfld.long 0x00 4. "WARSTEN,Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set.." "0: No effect,1: Warm reset sequence generator Enabled"
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bitfld.long 0x00 3. "ACTEN,Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will be set.." "0: No effect,1: Activation sequence generator Enabled"
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bitfld.long 0x00 2. "DACTEN,Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed this bit will be cleared automatically and the INITIF (SC_INTSTS[8]) will.." "0: No effect,1: Deactivation sequence generator Enabled"
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bitfld.long 0x00 1. "RXRST,RX Software Reset\nWhen RXRST is set all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Rx internal state machine and.."
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bitfld.long 0x00 0. "TXRST,TX Software Reset\nWhen TXRST is set all the bytes in the transmit buffer and Tx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete" "0: No effect,1: Reset the Tx internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "SC_EGT,SC Extra Guard Time Register"
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hexmask.long.byte 0x00 0.--7. 1. "EGT,Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base"
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group.long 0x10++0x03
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line.long 0x00 "SC_RXTOUT,SC Receive Buffer Time-out Counter Register"
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hexmask.long.word 0x00 0.--8. 1. "RFTM,SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the Rx buffer received a new data"
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group.long 0x14++0x03
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line.long 0x00 "SC_ETUCTL,SC Element Time Unit Control Register"
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hexmask.long.word 0x00 0.--11. 1. "ETURDIV,ETU Rate Divider\nThe field is used for define ETU time unit.\nThe real ETU time unit is (ETURDIV + 1) * SC clock time.\nNote: User can configure this field but this field must be greater than 0x004"
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group.long 0x18++0x03
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line.long 0x00 "SC_INTEN,SC Interrupt Enable Control Register"
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bitfld.long 0x00 10. "ACERRIEN,Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt" "0: Auto-convention error interrupt Disabled,1: Auto-convention error interrupt Enabled"
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bitfld.long 0x00 9. "RXTOIEN,Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt" "0: Receiver buffer time-out interrupt Disabled,1: Receiver buffer time-out interrupt Enabled"
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bitfld.long 0x00 8. "INITIEN,Initial End Interrupt Enable Bit" "0: Initial end interrupt Disabled,1: Initial end interrupt Enabled"
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bitfld.long 0x00 7. "CDIEN,Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt" "0: Card detect interrupt Disabled,1: Card detect interrupt Enabled"
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bitfld.long 0x00 6. "BGTIEN,Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time" "0: Block guard time interrupt Disabled,1: Block guard time interrupt Enabled"
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bitfld.long 0x00 5. "TMR2IEN,Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function" "0: Timer2 interrupt Disabled,1: Timer2 interrupt Enabled"
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bitfld.long 0x00 4. "TMR1IEN,Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function" "0: Timer1 interrupt Disabled,1: Timer1 interrupt Enabled"
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bitfld.long 0x00 3. "TMR0IEN,Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function" "0: Timer0 interrupt Disabled,1: Timer0 interrupt Enabled"
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bitfld.long 0x00 2. "TERRIEN,Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt" "0: Transfer error interrupt Disabled,1: Transfer error interrupt Enabled"
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bitfld.long 0x00 1. "TXEIEN,Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt" "0: Transmit buffer empty interrupt Disabled,1: Transmit buffer empty interrupt Enabled"
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bitfld.long 0x00 0. "RDAIEN,Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt" "0: Received data bytes in Rx buffer reach..,1: Received data bytes in Rx buffer reach.."
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group.long 0x1C++0x03
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line.long 0x00 "SC_INTSTS,SC Interrupt Status Register"
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bitfld.long 0x00 10. "ACERRIF,Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it" "0: Received TS at ATR state is 0x3B or 0x3F,1: Received TS at ATR state is neither 0x3B nor.."
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rbitfld.long 0x00 9. "RXTOIF,Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only user must read all receive buffer remaining data by reading DAT (SC_DAT[7:0]).." "0: Receive buffer time-out interrupt did not occur,1: Receive buffer time-out interrupt occurred"
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bitfld.long 0x00 8. "INITIF,Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SC_ALTCTL[3])) deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1.." "0: Initial sequence is not complete,1: Initial sequence is completed"
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rbitfld.long 0x00 7. "CDIF,Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag" "0: Card detect event did not occur,1: Card detect event occurred"
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bitfld.long 0x00 6. "BGTIF," "0: Block guard time interrupt did not occur,1: Block guard time interrupt occurred"
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bitfld.long 0x00 5. "TMR2IF,Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer2 interrupt did not occur,1: Timer2 interrupt occurred"
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bitfld.long 0x00 4. "TMR1IF,Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer1 interrupt did not occur,1: Timer1 interrupt occurred"
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bitfld.long 0x00 3. "TMR0IF,Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it" "0: Timer0 interrupt did not occur,1: Timer0 interrupt occurred"
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bitfld.long 0x00 2. "TERRIF,Transfer Error Interrupt Status Flag\nThis field is used for indicate transfer error interrupt status flag" "0: Transfer error interrupt did not occur,1: Transfer error interrupt occurred"
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rbitfld.long 0x00 1. "TXEIF,Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data bytes in Rx buffer reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.\nNote: This bit is read only" "0: Number of receive buffer is less than RXTRGLV..,1: Number of receive buffer data equals the.."
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group.long 0x20++0x03
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line.long 0x00 "SC_STATUS,SC Transfer Status Register"
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rbitfld.long 0x00 31. "TXACT,Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status" "0: This bit is cleared automatically when Tx..,1: Transmit is active or the STOP bit of last.."
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bitfld.long 0x00 30. "TXOVERR,Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it" "0: Transmitter retries counts is not over than..,1: Transmitter retries counts over than TXRTY.."
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bitfld.long 0x00 29. "TXRTYERR,Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU" "0: No Tx retry transfer,1: Tx has any error and retries transfer"
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rbitfld.long 0x00 24.--26. "TXPOINT,Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RXACT,Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status" "0: This bit is cleared automatically when Rx..,1: This bit is set by hardware when Rx transfer.."
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bitfld.long 0x00 22. "RXOVERR,Receiver over Retry Error\nThis bit is used for indicate receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user enables receiver retries function by setting RXRTYEN.." "0: Receiver retries counts is not over than..,1: Receiver retries counts over than RXRTY.."
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bitfld.long 0x00 21. "RXRTYERR,Receiver Retry Error\nThis bit is used for indicate receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt signal to CPU.\nNote3: If user.." "0: No Rx retry transfer,1: Rx has any error and retries transfer"
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rbitfld.long 0x00 16.--18. "RXPOINT,Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 13. "CDPINSTS,Card Detect Pin Status (Read Only)\nThis bit is the pin status of SC_CD" "0: The SC_CD pin state at low,1: The SC_CD pin state at high"
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bitfld.long 0x00 12. "CINSERT,Card Insert Status of SC_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: The card detect function will start after SCEN (SC_CTL[0]) is set" "0: No effect,1: Card insert"
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bitfld.long 0x00 11. "CREMOVE,Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: Card detect function will start after SCEN (SC_CTL[0]) is set" "0: No effect,1: Card removed"
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rbitfld.long 0x00 10. "TXFULL,Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer is full or not" "0: Tx buffer count is less than 4,1: Tx buffer count equals to 4"
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rbitfld.long 0x00 9. "TXEMPTY,Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer is empty or not.\nNote: This bit will be cleared when writing data into DAT (SC_DAT[7:0])" "0: Tx buffer is not empty,1: Tx buffer is empty it means the last byte of.."
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bitfld.long 0x00 8. "TXOV,Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow" "0: Tx buffer is not overflow,1: Tx buffer is overflow it means an additional.."
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bitfld.long 0x00 6. "BEF,Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the 'spacing state' (logic 0) is longer than a full word transmission time (that is the total time of 'start bit' + 'data bits' + 'parity bit'.." "0: Receiver break error flag did not occur,1: Receiver break error flag occurred"
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bitfld.long 0x00 5. "FEF,Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0)" "0: Receiver frame error flag did not occur,1: Receiver frame error flag occurred"
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bitfld.long 0x00 4. "PEF,Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If user sets receiver retries function by setting RXRTYEN.." "0: Receiver parity error flag did not occur,1: Receiver parity error flag occurred"
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rbitfld.long 0x00 2. "RXFULL,Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer is full or not" "0: Rx buffer count is less than 4,1: Rx buffer count equals to 4"
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rbitfld.long 0x00 1. "RXEMPTY,Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer is empty or not" "0: Rx buffer is not empty,1: Rx buffer is empty it means the last byte in.."
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bitfld.long 0x00 0. "RXOV,Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it" "0: Rx buffer is not overflow,1: Rx buffer is overflow when the number of.."
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group.long 0x24++0x03
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line.long 0x00 "SC_PINCTL,SC Pin Control State Register"
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rbitfld.long 0x00 30. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SC_PINCTL register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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rbitfld.long 0x00 18. "RSTSTS,SC_RST Pin Status (Read Only)\nThis bit is the pin status of SC_RST" "0: SC_RST pin is low,1: SC_RST pin is high"
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rbitfld.long 0x00 17. "PWRSTS,SC_PWR Pin Status (Read Only)\nThis bit is the pin status of SC_PWR" "0: SC_PWR pin to low,1: SC_PWR pin to high"
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rbitfld.long 0x00 16. "DATSTS,SC_DATA Pin Status (Read Only)" "0: The SC_DATA pin status is low,1: The SC_DATA pin status is high"
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bitfld.long 0x00 11. "PWRINV,SC_PWR Pin Inverse\nThis bit is used for inverse the SC_PWR pin.\nThere are four kinds of combination for SC_PWR pin setting by PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0])" "0,1"
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bitfld.long 0x00 9. "SCDATA,SC_DATA Pin Signal \nThis bit is the signal status of SC_DATA but user can also drive SC_DATA pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When SC is at activation warm reset or deactivation mode this bit.." "0: Drive SC_DATA pin to low.\nSC_DATA signal..,1: Drive SC_DATA pin to high.\nSC_DATA signal.."
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bitfld.long 0x00 6. "CLKKEEP,SC Clock Enable Bit \nNote: When operating in activation warm reset or deactivation mode this bit will be changed automatically" "0: SC clock generation Disabled,1: SC clock always keeps free running"
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bitfld.long 0x00 1. "SCRST,SC_RST Pin Signal\nThis bit is the signal status of SC_RST but user can drive SC_RST pin to high or low by control this bit.\nWrite this bit can drive SC_RST pin.\nNote: When operating at activation warm reset or deactivation mode this bit will be.." "0: Drive SC_RST pin to low.\nSC_RST signal..,1: Drive SC_RST pin to high.\nSC_RST signal.."
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bitfld.long 0x00 0. "PWREN,SC_PWR Pin Signal\nUser can set PWRINV (SC_PINCTL[11]) and PWREN (SC_PINCTL[0]) to decide SC_PWR pin is in high or low level.\nWrite this bit can drive SC_PWR pin\nRefer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level" "0: SC_PWR signal status is low,1: SC_PWR signal status is high"
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group.long 0x28++0x03
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line.long 0x00 "SC_TMRCTL0,SC Timer0 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SC_TMRCTL0 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Table 6.1528 for programming Timer0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer 0 Counter Value\nThis field indicates the internal Timer0 counter values"
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group.long 0x2C++0x03
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line.long 0x00 "SC_TMRCTL1,SC Timer1 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SC_TMRCTL1 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Table 6.1528 for programming Timer1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values"
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|
group.long 0x30++0x03
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line.long 0x00 "SC_TMRCTL2,SC Timer2 Control Register"
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rbitfld.long 0x00 31. "SYNC,SYNC Flag Indicator (Read Only)\nDue to synchronization user should check this bit when writing a new value to SC_TMRCTL2 register" "0: Synchronizing is completion user can write..,1: Last value is synchronizing"
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bitfld.long 0x00 24.--27. "OPMODE,Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Table 6.1528 for programming Timer2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "CNT,Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values"
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|
group.long 0x34++0x03
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line.long 0x00 "SC_UARTCTL,SC UART Mode Control Register"
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bitfld.long 0x00 7. "OPE,Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0" "0: Even number of logic 1's are transmitted or..,1: Odd number of logic 1's are transmitted or.."
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bitfld.long 0x00 6. "PBOFF,Parity Bit Disable Control\nThis bit is used to disable parity check function.\nNote: In smart card mode this bit must be 0 (default setting is with parity bit)" "0: Parity bit is generated or checked between..,1: Parity bit is not generated (transmitting.."
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newline
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bitfld.long 0x00 4.--5. "WLS,Word Length Selection\nThis field is used to select UART data transfer length.\nNote: In smart card mode this field must be 00" "0: Word length is 8 bits,1: Word length is 7 bits,2: Word length is 6 bits,3: Word length is 5 bits"
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bitfld.long 0x00 0. "UARTEN,UART Mode Enable Bit\nSet this bit to enable UART mode function.\nNote3: When UART mode is enabled hardware will generate a reset SC event to reset FIFO and internal state machine" "0: Smart Card mode,1: UART mode"
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rgroup.long 0x38++0x03
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line.long 0x00 "SC_TMRDAT0,SC Timer0 Current Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT0,Timer0 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer0"
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rgroup.long 0x3C++0x03
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line.long 0x00 "SC_TMRDAT12,SC Timer1/2 Current Data Register"
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hexmask.long.byte 0x00 8.--15. 1. "CNT2,Timer2 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer2"
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hexmask.long.byte 0x00 0.--7. 1. "CNT1,Timer1 Current Data Value (Read Only)\nThis field indicates the current counter values of Timer1"
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group.long 0x4C++0x03
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line.long 0x00 "SC_ACTCTL,SC Activation Control Register"
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bitfld.long 0x00 0.--4. "T1EXT,T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nPlease refer to SC activation sequence in Figure 6.154.\nThe cycle scaling factor is 2048 and \nNote: Setting 0 to this.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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tree.end
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repeat.end
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tree.end
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tree "SPI"
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repeat 2. (list 0. 1.) (list ad:0x40030000 ad:0x40034000)
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tree "SPI$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x00 20. "DATDIR,Data Port Direction Control\nThis bit is used to select the data input/output direction in half-duplex transfer" "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Bit\nNote: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled"
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newline
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bitfld.long 0x00 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x00 15. "RXONLY,Receive-only Mode Enable Bit (Master Only)\nThis bit field is only available in Master mode" "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x00 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit\nThis bit is used to select full-duplex or half-duplex for SPI transfer" "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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newline
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bitfld.long 0x00 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
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bitfld.long 0x00 8.--12. "DWIDTH,Data Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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newline
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bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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newline
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bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
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bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nIn Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1" "0: Transfer control Disabled,1: Transfer control Enabled"
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group.long 0x04++0x03
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line.long 0x00 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider\nThe value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master"
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group.long 0x08++0x03
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line.long 0x00 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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newline
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bitfld.long 0x00 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Selection Function Enable Bit (Master Only)" "0: Automatic slave selection function Disabled,1: Automatic slave selection function Enabled"
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bitfld.long 0x00 2. "SSACTPOL,Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIx_SS)" "0: The slave selection signal SPIx_SS is active..,1: The slave selection signal SPIx_SS is active.."
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newline
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bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0" "0: set the SPIx_SS line to inactive state.\nKeep..,1: set the SPIx_SS line to active.."
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group.long 0x0C++0x03
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line.long 0x00 "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0x00 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0x00 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x00 0. "TXPDMAEN,Transmit PDMA Enable Bit\nNote: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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group.long 0x10++0x03
|
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line.long 0x00 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x00 28.--29. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0" "0,1,2,3"
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bitfld.long 0x00 24.--25. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0" "0,1,2,3"
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newline
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bitfld.long 0x00 9. "TXFBCLR,Transmit FIFO Buffer Clear\nNote: The TX shift register will not be cleared" "0: No effect,1: Clear transmit FIFO pointer"
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bitfld.long 0x00 8. "RXFBCLR,Receive FIFO Buffer Clear\nNote: The RX shift register will not be cleared" "0: No effect,1: Clear receive FIFO pointer"
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newline
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bitfld.long 0x00 7. "TXUFIEN,TX Underflow Interrupt Enable Bit" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x00 6. "TXUFPOL,TX Underflow Data Polarity\nNote:\n1" "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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newline
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bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x00 1. "TXRST,Transmit Reset\nNote: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state" "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x00 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit"
|
|
group.long 0x14++0x03
|
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line.long 0x00 "SPIx_STATUS,SPI Status Register"
|
|
rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
|
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rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\nNote1: This bit will be cleared by writing 1 to it.\nNote2: If reset slave's transmission.." "0: No effect,1: No data in Transmit FIFO and TX shift.."
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newline
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
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rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
|
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bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
|
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rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
|
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rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
bitfld.long 0x00 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag\nIn Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0: No Slave TX under run event,1: Slave TX under run event occurs"
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newline
|
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bitfld.long 0x00 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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|
rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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|
newline
|
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bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select inactive interrupt was cleared..,1: Slave select inactive interrupt event occurred"
|
|
bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Flag\nNote: Only available in Slave mode" "0: Slave select active interrupt was cleared or..,1: Slave select active interrupt event occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
|
|
rbitfld.long 0x00 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "SPIx_TX,SPI Data Transmit Register"
|
|
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "SPIx_RX,SPI Data Receive Register"
|
|
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThere are 4-level FIFO buffers in this controller"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SPIx_I2SCTL,I2S Control Register"
|
|
bitfld.long 0x00 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,2: PCM mode A,3: PCM mode B"
|
|
bitfld.long 0x00 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero cross event occurs" "0: Interrupt Disabled,1: Interrupt Enabled"
|
|
bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
|
|
newline
|
|
bitfld.long 0x00 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1" "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
|
|
bitfld.long 0x00 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1" "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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|
newline
|
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bitfld.long 0x00 15. "MCLKEN,Master Clock Enable Bit\nIf MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices" "0: Master clock Disabled,1: Master clock Enabled"
|
|
bitfld.long 0x00 8. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
|
|
newline
|
|
bitfld.long 0x00 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
|
|
bitfld.long 0x00 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
|
|
newline
|
|
bitfld.long 0x00 4.--5. "WDWIDTH,Word Width" "0: data size is 8-bit,1: data size is 16-bit,2: data size is 24-bit,3: data size is 32-bit"
|
|
bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
|
|
newline
|
|
bitfld.long 0x00 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
|
|
bitfld.long 0x00 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Bit\nNote:\n1" "0: I2S mode Disabled,1: I2S mode Enabled"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "SPIx_I2SCLK,I2S Clock Divider Control Register"
|
|
hexmask.long.word 0x00 8.--16. 1. "BCLKDIV,Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode"
|
|
bitfld.long 0x00 0.--5. "MCLKDIV,Master Clock Divider\nIf MCLKEN is set to 1 I2S controller will generate master clock for external audio devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "SPIx_I2SSTS,I2S Status Register"
|
|
rbitfld.long 0x00 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 24.--26. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x00 23. "TXRXRST,TX or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles" "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
|
|
bitfld.long 0x00 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
|
|
newline
|
|
bitfld.long 0x00 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
|
|
bitfld.long 0x00 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag\nWhen the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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|
newline
|
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rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
newline
|
|
rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
rbitfld.long 0x00 15. "I2SENSTS,I2S Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock" "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
|
|
bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it" "0,1"
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|
newline
|
|
rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
|
|
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
|
|
rbitfld.long 0x00 4. "RIGHT,Right Channel (Read Only)\nThis bit indicates the current transmit data is belong to which channel" "0: Left channel,1: Right channel"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
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tree "SYS"
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base ad:0x50000000
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rgroup.long 0x00++0x03
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line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
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group.long 0x04++0x03
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line.long 0x00 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\nThe CPU lockup reset flag is set by hardware If Cortex-M0 lockup happened.\nNote: This bit can be cleared by software writing '1'" "0: No reset from CPU lockup happened,1: The Cortex-M0 lockup happened and chip is reset"
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bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: This bit can be cleared by software writing '1'" "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by.."
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newline
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bitfld.long 0x00 5. "MCURF,MCU Reset Flag\nThe MCU reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'" "0: No reset from Cortex-M0,1: The Cortex-M0 had issued the reset signal to.."
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bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.."
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newline
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bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'" "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: This bit can be cleared by software writing '1'.\nNote2: Watchdog Timer register.." "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.."
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newline
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bitfld.long 0x00 1. "PINRF,nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.."
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bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.."
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group.long 0x08++0x03
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line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x00 4. "HDIVRST,HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the HDIV controller" "0: HDIV controller normal operation,1: HDIV controller reset"
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newline
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bitfld.long 0x00 3. "EBIRST,EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI" "0: EBI controller normal operation,1: EBI controller reset"
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bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset"
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newline
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bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset"
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group.long 0x0C++0x03
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line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x00 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset"
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bitfld.long 0x00 22. "ACMP01RST,ACMP01 Controller Reset" "0: ACMP01 controller normal operation,1: ACMP01 controller reset"
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newline
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bitfld.long 0x00 21. "PWM1RST,PWM1 Controller Reset" "0: PWM1 controller normal operation,1: PWM1 controller reset"
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bitfld.long 0x00 20. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset"
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newline
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bitfld.long 0x00 18. "UART2RST,UART2 Controller Reset" "0: UART2 controller normal operation,1: UART2 controller reset"
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bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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newline
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bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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bitfld.long 0x00 13. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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newline
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bitfld.long 0x00 12. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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newline
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bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
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newline
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bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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newline
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bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
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group.long 0x10++0x03
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line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2"
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bitfld.long 0x00 10. "USCI2RST,USCI2 Controller Reset" "0: USCI2 controller normal operation,1: USCI2 controller reset"
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bitfld.long 0x00 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset"
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newline
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bitfld.long 0x00 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset"
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bitfld.long 0x00 1. "SC1RST,SC1 Controller Reset" "0: SC1 controller normal operation,1: SC1 controller reset"
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newline
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bitfld.long 0x00 0. "SC0RST,SC0 Controller Reset" "0: SC0 controller normal operation,1: SC0 controller reset"
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group.long 0x18++0x03
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line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register"
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bitfld.long 0x00 25.--27. "VDETDGSEL,Voltage Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: VDET output is sampled by VDET clock,1: 16 system clock (HCLK),2: 32 system clock (HCLK),3: 64 system clock (HCLK),4: 128 system clock (HCLK),5: 256 system clock (HCLK),6: 512 system clock (HCLK),7: 1024 system clock (HCLK)"
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bitfld.long 0x00 24. "VDETOUT,Voltage Detector Output Status\nIt means the detected voltage is lower than Bandgap" "0: VDET output status is 0,1: VDET output status is 1"
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newline
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bitfld.long 0x00 19. "VDETIF,Voltage Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'" "0: VDET does not detect any voltage draft at..,1: When VDET detects the external pin is dropped.."
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bitfld.long 0x00 18. "VDETIEN,Voltage Detector Interrupt Enable Bit" "0: VDET interrupt Disabled,1: VDET interrupt Enabled"
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newline
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bitfld.long 0x00 17. "VDETPINSEL,Voltage Detector External Input Voltage Pin Selection\nNote1: If VDET_P0 is selected multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0]).\nNote2: If VDET_P1 is selected multi-function pin must be selected correctly in.." "0: The input voltage is from VDET_P0 (PB.0),1: The input voltage is from VDET_P1 (PB.1)"
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bitfld.long 0x00 16. "VDETEN,Voltage Detector Enable Bit\nNote1: This function is still active in whole chip power-down mode.\nNote2: This function need use LIRC or LXT as VDET clock source which is selected in VDETCKSEL (CLK_BODCLK[0]).\nNote2: The input pin for VDET detect.." "0: VDET detect external input voltage function..,1: VDET detect external input voltage function.."
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newline
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bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),2: 8 system clock (HCLK),3: 16 system clock (HCLK),4: 32 system clock (HCLK),5: 64 system clock (HCLK),6: 128 system clock (HCLK),7: 256 system clock (HCLK)"
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newline
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bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled"
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bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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newline
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bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled"
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bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.."
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newline
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bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote1: \nWhile the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x00 1.--2. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected" "0: Brown-Out Detector threshold voltage is 2.2V,1: Brown-Out Detector threshold voltage is 2.7V,2: Brown-Out Detector threshold voltage is 3.7V,3: Brown-Out Detector threshold voltage is 4.5V"
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newline
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bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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group.long 0x1C++0x03
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line.long 0x00 "SYS_IVSCTL,Internal Voltage Source Control Register"
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bitfld.long 0x00 1. "VBATUGEN,VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1 the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result" "0: VBAT unity gain buffer function Disabled..,1: VBAT unity gain buffer function Enabled"
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bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x03
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line.long 0x00 "SYS_PORCTL,Power-on Reset Controller Register"
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hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again"
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group.long 0x28++0x03
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line.long 0x00 "SYS_VREFCTL,VREF Control Register"
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bitfld.long 0x00 0.--4. "VREFCTL,Int_VREF Control Bits (Write Protect)\nNote: These bit are write protected" "0: From VREF pin,?,?,3: VREF is internal 2.56V,?,?,?,7: VREF is internal 2.048V,?,?,?,11: VREF is internal 3.072V,?,?,?,15: VREF is internal 4.096V,16: VREF is from AVDD,?..."
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group.long 0x30++0x03
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line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x34++0x03
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line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x38++0x03
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line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x3C++0x03
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line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x40++0x03
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line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 12.--15. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 4.--7. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x44++0x03
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line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PC15MFP,PC15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PC14MFP,PC14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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newline
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bitfld.long 0x00 20.--23. "PC13MFP,PC13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PC12MFP,PC12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PC11MFP,PC11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PC10MFP,PC10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PC9MFP,PC9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PC8MFP,PC8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x48++0x03
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line.long 0x00 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PD7MFP,PD.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PD6MFP,PD.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PD5MFP,PD.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PD4MFP,PD.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PD3MFP,PD.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PD2MFP,PD.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PD1MFP,PD.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PD0MFP,PD.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x4C++0x03
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line.long 0x00 "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PD15MFP,PD.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PD14MFP,PD.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PD13MFP,PD.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PD12MFP,PD.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PD11MFP,PD.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PD10MFP,PD.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PD9MFP,PD.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PD8MFP,PD.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x50++0x03
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line.long 0x00 "SYS_GPE_MFPL,GPIOE Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PE7MFP,PE.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PE6MFP,PE.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PE5MFP,PE.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PE4MFP,PE.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PE3MFP,PE.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PE2MFP,PE.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PE1MFP,PE.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PE0MFP,PE.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x54++0x03
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line.long 0x00 "SYS_GPE_MFPH,GPIOE High Byte Multiple Function Control Register"
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bitfld.long 0x00 20.--23. "PE13MFP,PE.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PE12MFP,PE.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PE11MFP,PE.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PE10MFP,PE.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PE9MFP,PE.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PE8MFP,PE.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x58++0x03
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line.long 0x00 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
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bitfld.long 0x00 28.--31. "PF7MFP,PF.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PF6MFP,PF.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PF5MFP,PF.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PF4MFP,PF.4 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit" "0: PF.4 pin is configured as GPIO pins,1: PF.4 pin is configured as external 4~24 MHz..,?..."
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bitfld.long 0x00 12.--15. "PF3MFP,PF.3 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit" "0: PF.3 pin is configured as GPIO pins,1: PF.3 pin is configured as external 4~24 MHz..,?..."
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bitfld.long 0x00 8.--11. "PF2MFP,PF.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PF1MFP,PF.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PF0MFP,PF.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x80++0x03
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line.long 0x00 "SYS_IRCTCTL0,HIRC0 Trim Control Register"
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768..,1: Reserved"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz LXT).\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 0 (HIRC0) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN(SYS_IRCTCTL0[8]) is set to 1 or trim retry limitation.." "0: Disable HIRC0 auto trim function,1: Enable HIRC0 auto trim function and trim HIRC..,2: Reserved,3: Reserved"
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group.long 0x84++0x03
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line.long 0x00 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x00 10. "CLKEIEN1,HIRC1 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC1 clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation an.." "0: Disable CLKERRIF(SYS_IRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS[2]) status to.."
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bitfld.long 0x00 9. "TFAILIEN1,HIRC1 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0]).\nIf.." "0: Disable TFAILIF(SYS_IRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS[1]) status to.."
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bitfld.long 0x00 2. "CLKEIEN,HIRC0 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC0 clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_IRCTSTS0[2]) is set during auto trim operation an.." "0: Disable CLKERRIF(SYS_IRCTSTS0[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS0[2]) status to.."
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bitfld.long 0x00 1. "TFAILIEN,HIRC0 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL0[1:0]).\nIf.." "0: Disable TFAILIF(SYS_IRCTSTS0[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS0[1]) status to.."
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group.long 0x88++0x03
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line.long 0x00 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x00 10. "CLKERRIF1,HIRC1 Clock Error Interrupt Status\nWhen 48 MHz internal high speed RC oscillator 1 (HIRC1) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1 the auto.." "0: HIRC1 Clock frequency is accuracy,1: HIRC1 Clock frequency is inaccuracy"
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bitfld.long 0x00 9. "TFAILIF1,HIRC1 Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked" "0: HIRC1 trim value update limitation count does..,1: HIRC1 trim value update limitation count.."
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bitfld.long 0x00 8. "FREQLOCK1,HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt" "0: The internal high-speed RC oscillator 1..,1: The internal high-speed RC oscillator 1.."
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bitfld.long 0x00 2. "CLKERRIF,Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator 0 (HIRC0) is shift larger to unreasonable value this bit will be set and to be an.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy"
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bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.."
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bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt" "0: The internal high-speed RC oscillator 0..,1: The internal high-speed RC oscillator 0.."
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group.long 0x90++0x03
|
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line.long 0x00 "SYS_IRCTCTL1,HIRC1 Trim Control Register"
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bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768..,1: Reserved"
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bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops"
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bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.."
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bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 1 (HIRC 1) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry.." "0: Disable HIRC1 auto trim function,1: Reserved,2: Enable HIRC1 auto trim function and trim HIRC..,3: Reserved"
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group.long 0xC0++0x03
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line.long 0x00 "SYS_MODCTL,Modulation Control Register"
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bitfld.long 0x00 4.--6. "MODPWMSEL,PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART1_TXD.\nNote: This bit is valid while MODEN (SYS_MODCTL[0]) is set to 1" "0: PWM0 channel 0 modulate with UART1_TXD,1: PWM0 channel 1 modulate with UART1_TXD,2: PWM0 channel 2 modulate with UART1_TXD,3: PWM0 channel 3 modulete with UART1_TXD,?..."
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bitfld.long 0x00 1. "MODH,Modulation at Data High\nSelect modulation pulse(PWM) at UART1_TXD high or low" "0: Modulation pulse at UART1_TXD low,1: Modulation pulse at UART1_TXD high"
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bitfld.long 0x00 0. "MODEN,Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM channel output and UART1_TXD" "0: Modulation Function Disabled,1: Modulation Function Enabled"
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group.long 0x100++0x03
|
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line.long 0x00 "SYS_REGLCTL,Register Lock Control Register"
|
|
hexmask.long.byte 0x00 1.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function"
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rbitfld.long 0x00 0. "REGLCTL0,Register Lock Control Disable Index (Read Only)\nThe Protected registers are:\nSYS_IPRST0: address 0x5000_0008\nSYS_BODCTL: address 0x5000_0018\nSYS_PORCTL: address 0x5000_0024\nSYS_VREFCTL: address 0x5000_0028\nCLK_PWRCTL[13]: address.." "0: Write-protection Enabled for writing..,1: Write-protection Disabled for writing.."
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rgroup.long 0x114++0x03
|
|
line.long 0x00 "SYS_TSOFFSET,Temperature Sensor Offset Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "VTEMP,Temperature Sensor Offset Value \nThis field reflects temperature sensor output voltage offset at 25oC from flash"
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tree.end
|
|
tree "SYST_NVIC_SCS"
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base ad:0xE000E000
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
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bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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|
bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "NVIC_ISER,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Enable Register\nEnable one or more interrupts"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "NVIC_ICER,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Disable Bits\nDisable one or more interrupts"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "NVIC_ISPR,IRQ0 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Set Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "NVIC_ICPR,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Clear Interrupt Pending Bits\nWrite Operation:\nNote: Read value indicates the current pending status"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "NVIC_IPR0,IRQ0 ~ IRQ3 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_3,Priority of IRQ3\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_2,Priority of IRQ2\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_1,Priority of IRQ1\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_0,Priority of IRQ0\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "NVIC_IPR1,IRQ4 ~ IRQ7 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_7,Priority of IRQ7\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_6,Priority of IRQ6\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_5,Priority of IRQ5\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_4,Priority of IRQ4\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "NVIC_IPR2,IRQ8 ~ IRQ11 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of IRQ11\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_10,Priority of IRQ10\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x00 14.--15. "PRI_9,Priority of IRQ9\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
bitfld.long 0x00 6.--7. "PRI_8,Priority of IRQ8\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "NVIC_IPR3,IRQ12 ~ IRQ15 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of IRQ15\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of IRQ14\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
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bitfld.long 0x00 14.--15. "PRI_13,Priority of IRQ13\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_12,Priority of IRQ12\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "NVIC_IPR4,IRQ16 ~ IRQ19 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_19,Priority of IRQ19\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_18,Priority of IRQ18\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
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bitfld.long 0x00 14.--15. "PRI_17,Priority of IRQ17\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_16,Priority of IRQ16\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "NVIC_IPR5,IRQ20 ~ IRQ23 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_23,Priority of IRQ23\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_22,Priority of IRQ22\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
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bitfld.long 0x00 14.--15. "PRI_21,Priority of IRQ21\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_20,Priority of IRQ20\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "NVIC_IPR6,IRQ24 ~ IRQ27 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_27,Priority of IRQ27\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_26,Priority of IRQ26\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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|
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bitfld.long 0x00 14.--15. "PRI_25,Priority of IRQ25\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_24,Priority of IRQ24\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "NVIC_IPR7,IRQ28 ~ IRQ31 Priority Control Register"
|
|
bitfld.long 0x00 30.--31. "PRI_31,Priority of IRQ31\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_30,Priority of IRQ30\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
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bitfld.long 0x00 14.--15. "PRI_29,Priority of IRQ29\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. "PRI_28,Priority of IRQ28\n'0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer Code Assigned by ARM"
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|
bitfld.long 0x00 16.--19. "PART,Architecture of the Processor\nRead as 0xC for ARMv6-M parts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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hexmask.long.word 0x00 4.--15. 1. "PARTNO,Part Number of the Processor\nRead as 0xC20"
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|
bitfld.long 0x00 0.--3. "REVISION,Revision Number\nRead as 0x0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nBecause NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception not pending,1: Changes NMI exception state to pending.\nNMI.."
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|
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
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|
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bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
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|
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.."
|
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bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nThis is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
|
|
bitfld.long 0x00 23. "ISRPREEMPT,If Set a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only" "0,1"
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|
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bitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults:\nThis bit is read only" "0: Interrupt not pending,1: Interrupt pending"
|
|
bitfld.long 0x00 12.--17. "VECTPENDING,Indicates the Exception Number of the Highest Priority Pending Enabled Exception" "0: No pending exceptions,?..."
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|
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bitfld.long 0x00 0.--5. "VECTACTIVE,Contains the Active Exception Number" "0: Thread mode,?..."
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWrite Operation:\nWhen writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored"
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|
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence" "0,1"
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|
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bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nReserved for debug use" "0,1"
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending Bit\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
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|
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode" "0: Sleep mode,1: Deep Sleep mode"
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|
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bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.."
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3"
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3"
|
|
tree.end
|
|
tree "TIMER"
|
|
tree "TMR01"
|
|
base ad:0x40010000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TIMER0_CTL,Timer0 Control Register"
|
|
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not" "0: Stop/Suspend counting,1: Start counting"
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|
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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|
bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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|
bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf the updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode..,1: The behavior selection in periodic mode Enabled"
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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|
hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
|
|
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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|
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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|
group.long 0x0C++0x03
|
|
line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
|
|
rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation:\nRead this register to get CNT value"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
|
|
bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x=..,1: Reserved"
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|
bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit" "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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|
bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt..,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
|
|
bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function" "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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newline
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
|
|
bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TIMER0_TRGCTL,Timer0 Trigger Control Register"
|
|
bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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|
bitfld.long 0x00 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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|
newline
|
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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|
bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TIMER0_ALTCTL,Timer0 Alternative Control Register"
|
|
bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TIMER0_PWMCTL,Timer0 PWM Control Register"
|
|
bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
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|
bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
|
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
|
|
bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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|
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|
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
|
|
bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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|
newline
|
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
|
|
bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIMER0_PWMCLKSRC,Timer0 PWM Counter Clock Source Register"
|
|
bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TIMER0_PWMCLKPSC,Timer0 PWM Counter Clock Pre-scale Register"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TIMER0_PWMCNTCLR,Timer0 PWM Clear Counter Register"
|
|
bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIMER0_PWMPERIOD,Timer0 PWM Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TIMER0_PWMCMPDAT,Timer0 PWM Comparator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TIMER0_PWMDTCTL,Timer0 PWM Dead-time Control Register"
|
|
bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
|
|
bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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|
newline
|
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "TIMER0_PWMCNT,Timer0 PWM Counter Register"
|
|
bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TIMER0_PWMMSKEN,Timer0 PWM Output Mask Enable Register"
|
|
bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER0_PWMMSK,Timer0 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER0_PWMBNF,Timer0 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,2: Brake pin source comes from TM_BRAKE2,3: Brake pin source comes from TM_BRAKE3"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER0_PWMFAILBRK,Timer0 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER0_PWMBRKCTL,Timer0 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH1 output tri-state when TIMERx_PWM..,2: PWMx_CH1 output low level when TIMERx_PWM..,3: PWMx_CH1 output high level when TIMERx_PWM.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH0 output tri-state when TIMERx_PWM..,2: PWMx_CH0 output low level when TIMERx_PWM..,3: PWMx_CH0 output high level when TIMERx_PWM.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as level-detect brake..,1: TM_BRAKEx pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as edge-detect brake..,1: TM_BRAKEx pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER0_PWMPOLCTL,Timer0 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER0_PWMPOEN,Timer0 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER0_PWMSWBRK,Timer0 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER0_PWMINTEN0,Timer0 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER0_PWMINTEN1,Timer0 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER0_PWMINTSTS0,Timer0 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER0_PWMINTSTS1,Timer0 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 level-detect brake event did not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 level-detect brake event did not..,1: PWMx_CH0 level-detect brake event happened"
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER0_PWMADCTS,Timer0 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),2: Trigger ADC conversion at zero or period..,3: Trigger ADC conversion at compare up count..,4: Trigger ADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER0_PWMSCTL,Timer0 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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wgroup.long 0x98++0x03
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line.long 0x00 "TIMER0_PWMSTRG,Timer0 PWM Synchronous Trigger Register"
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bitfld.long 0x00 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER0_PWMSTATUS,Timer0 PWM Status Register"
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bitfld.long 0x00 16. "ADCTRGF,Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger ADC start..,1: PWM counter event trigger ADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value"
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER0_PWMPBUF,Timer0 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER0_PWMCMPBUF,Timer0 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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group.long 0x100++0x03
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line.long 0x00 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not" "0: Stop/Suspend counting,1: Start counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf the updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode..,1: The behavior selection in periodic mode Enabled"
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x108++0x03
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line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation:\nRead this register to get CNT value"
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group.long 0x110++0x03
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line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x114++0x03
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line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x=..,1: Reserved"
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit" "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt..,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function" "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
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line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x11C++0x03
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line.long 0x00 "TIMER1_TRGCTL,Timer1 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x120++0x03
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line.long 0x00 "TIMER1_ALTCTL,Timer1 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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group.long 0x140++0x03
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line.long 0x00 "TIMER1_PWMCTL,Timer1 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x144++0x03
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line.long 0x00 "TIMER1_PWMCLKSRC,Timer1 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x148++0x03
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line.long 0x00 "TIMER1_PWMCLKPSC,Timer1 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x14C++0x03
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line.long 0x00 "TIMER1_PWMCNTCLR,Timer1 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x150++0x03
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line.long 0x00 "TIMER1_PWMPERIOD,Timer1 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x154++0x03
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line.long 0x00 "TIMER1_PWMCMPDAT,Timer1 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x158++0x03
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line.long 0x00 "TIMER1_PWMDTCTL,Timer1 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected"
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group.long 0x15C++0x03
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line.long 0x00 "TIMER1_PWMCNT,Timer1 PWM Counter Register"
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rbitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x160++0x03
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line.long 0x00 "TIMER1_PWMMSKEN,Timer1 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x164++0x03
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line.long 0x00 "TIMER1_PWMMSK,Timer1 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x168++0x03
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line.long 0x00 "TIMER1_PWMBNF,Timer1 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,2: Brake pin source comes from TM_BRAKE2,3: Brake pin source comes from TM_BRAKE3"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled"
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group.long 0x16C++0x03
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line.long 0x00 "TIMER1_PWMFAILBRK,Timer1 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x170++0x03
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line.long 0x00 "TIMER1_PWMBRKCTL,Timer1 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH1 output tri-state when TIMERx_PWM..,2: PWMx_CH1 output low level when TIMERx_PWM..,3: PWMx_CH1 output high level when TIMERx_PWM.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH0 output tri-state when TIMERx_PWM..,2: PWMx_CH0 output low level when TIMERx_PWM..,3: PWMx_CH0 output high level when TIMERx_PWM.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as level-detect brake..,1: TM_BRAKEx pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as edge-detect brake..,1: TM_BRAKEx pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x174++0x03
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line.long 0x00 "TIMER1_PWMPOLCTL,Timer1 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x178++0x03
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line.long 0x00 "TIMER1_PWMPOEN,Timer1 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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group.long 0x17C++0x03
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line.long 0x00 "TIMER1_PWMSWBRK,Timer1 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x180++0x03
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line.long 0x00 "TIMER1_PWMINTEN0,Timer1 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x184++0x03
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line.long 0x00 "TIMER1_PWMINTEN1,Timer1 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x188++0x03
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line.long 0x00 "TIMER1_PWMINTSTS0,Timer1 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is.." "0,1"
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newline
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x18C++0x03
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line.long 0x00 "TIMER1_PWMINTSTS1,Timer1 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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newline
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 level-detect brake event did not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 level-detect brake event did not..,1: PWMx_CH0 level-detect brake event happened"
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newline
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x190++0x03
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line.long 0x00 "TIMER1_PWMADCTS,Timer1 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),2: Trigger ADC conversion at zero or period..,3: Trigger ADC conversion at compare up count..,4: Trigger ADC conversion at compare down count..,?..."
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group.long 0x194++0x03
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line.long 0x00 "TIMER1_PWMSCTL,Timer1 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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group.long 0x19C++0x03
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line.long 0x00 "TIMER1_PWMSTATUS,Timer1 PWM Status Register"
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bitfld.long 0x00 16. "ADCTRGF,Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger ADC start..,1: PWM counter event trigger ADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value"
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group.long 0x1A0++0x03
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line.long 0x00 "TIMER1_PWMPBUF,Timer1 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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group.long 0x1A4++0x03
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line.long 0x00 "TIMER1_PWMCMPBUF,Timer1 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree "TMR23"
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base ad:0x40110000
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group.long 0x00++0x03
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line.long 0x00 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not" "0: Stop/Suspend counting,1: Start counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf the updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode..,1: The behavior selection in periodic mode Enabled"
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x04++0x03
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line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x08++0x03
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line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x0C++0x03
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line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation:\nRead this register to get CNT value"
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rgroup.long 0x10++0x03
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line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x14++0x03
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line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x=..,1: Reserved"
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit" "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt..,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function" "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x18++0x03
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line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x1C++0x03
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line.long 0x00 "TIMER2_TRGCTL,Timer2 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x20++0x03
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line.long 0x00 "TIMER2_ALTCTL,Timer2 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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group.long 0x40++0x03
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line.long 0x00 "TIMER2_PWMCTL,Timer2 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x44++0x03
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line.long 0x00 "TIMER2_PWMCLKSRC,Timer2 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x48++0x03
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line.long 0x00 "TIMER2_PWMCLKPSC,Timer2 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x4C++0x03
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line.long 0x00 "TIMER2_PWMCNTCLR,Timer2 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x50++0x03
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line.long 0x00 "TIMER2_PWMPERIOD,Timer2 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x54++0x03
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line.long 0x00 "TIMER2_PWMCMPDAT,Timer2 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x58++0x03
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line.long 0x00 "TIMER2_PWMDTCTL,Timer2 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected"
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rgroup.long 0x5C++0x03
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line.long 0x00 "TIMER2_PWMCNT,Timer2 PWM Counter Register"
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bitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x60++0x03
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line.long 0x00 "TIMER2_PWMMSKEN,Timer2 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x64++0x03
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line.long 0x00 "TIMER2_PWMMSK,Timer2 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x68++0x03
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line.long 0x00 "TIMER2_PWMBNF,Timer2 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,2: Brake pin source comes from TM_BRAKE2,3: Brake pin source comes from TM_BRAKE3"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled"
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group.long 0x6C++0x03
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line.long 0x00 "TIMER2_PWMFAILBRK,Timer2 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x70++0x03
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line.long 0x00 "TIMER2_PWMBRKCTL,Timer2 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH1 output tri-state when TIMERx_PWM..,2: PWMx_CH1 output low level when TIMERx_PWM..,3: PWMx_CH1 output high level when TIMERx_PWM.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH0 output tri-state when TIMERx_PWM..,2: PWMx_CH0 output low level when TIMERx_PWM..,3: PWMx_CH0 output high level when TIMERx_PWM.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as level-detect brake..,1: TM_BRAKEx pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as edge-detect brake..,1: TM_BRAKEx pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x74++0x03
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line.long 0x00 "TIMER2_PWMPOLCTL,Timer2 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x78++0x03
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line.long 0x00 "TIMER2_PWMPOEN,Timer2 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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wgroup.long 0x7C++0x03
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line.long 0x00 "TIMER2_PWMSWBRK,Timer2 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x80++0x03
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line.long 0x00 "TIMER2_PWMINTEN0,Timer2 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x84++0x03
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line.long 0x00 "TIMER2_PWMINTEN1,Timer2 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x88++0x03
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line.long 0x00 "TIMER2_PWMINTSTS0,Timer2 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x8C++0x03
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line.long 0x00 "TIMER2_PWMINTSTS1,Timer2 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 level-detect brake event did not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 level-detect brake event did not..,1: PWMx_CH0 level-detect brake event happened"
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x90++0x03
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line.long 0x00 "TIMER2_PWMADCTS,Timer2 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),2: Trigger ADC conversion at zero or period..,3: Trigger ADC conversion at compare up count..,4: Trigger ADC conversion at compare down count..,?..."
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group.long 0x94++0x03
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line.long 0x00 "TIMER2_PWMSCTL,Timer2 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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wgroup.long 0x98++0x03
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line.long 0x00 "TIMER2_PWMSTRG,Timer2 PWM Synchronous Trigger Register"
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bitfld.long 0x00 0. "STRGEN,PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to.." "0,1"
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group.long 0x9C++0x03
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line.long 0x00 "TIMER2_PWMSTATUS,Timer2 PWM Status Register"
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bitfld.long 0x00 16. "ADCTRGF,Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger ADC start..,1: PWM counter event trigger ADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value"
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rgroup.long 0xA0++0x03
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line.long 0x00 "TIMER2_PWMPBUF,Timer2 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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rgroup.long 0xA4++0x03
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line.long 0x00 "TIMER2_PWMCMPBUF,Timer2 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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group.long 0x100++0x03
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line.long 0x00 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not" "0: Stop/Suspend counting,1: Start counting"
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bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The Timer controller is operated in One-shot..,1: The Timer controller is operated in Periodic..,2: The Timer controller is operated in..,3: The Timer controller is operated in.."
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rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x00 22. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from Tx_EXT (x=..,1: Capture Function source is from internal ACMP.."
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bitfld.long 0x00 21. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.."
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bitfld.long 0x00 20. "PERIOSEL,Periodic Mode Behavior Selection Enable Bit\nIf the updated CMPDAT value CNT CNT will be reset to default value" "0: The behavior selection in periodic mode..,1: The behavior selection in periodic mode Enabled"
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bitfld.long 0x00 19. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger Capture mode Disabled,1: Inter-Timer Trigger Capture mode Enabled"
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hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value"
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group.long 0x104++0x03
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line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register"
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group.long 0x108++0x03
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line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value"
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group.long 0x10C++0x03
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line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
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rbitfld.long 0x00 31. "RSTACT,Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter" "0: Reset operation is done,1: Reset operation triggered by writing.."
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hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead operation:\nRead this register to get CNT value"
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group.long 0x110++0x03
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line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current.."
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group.long 0x114++0x03
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line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from Tx (x=..,1: Reserved"
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bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.."
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bitfld.long 0x00 8. "ACMPSSEL,ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal.."
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bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx pin is detected with de-bounce circuit" "0: Tx (x= 0~3) pin de-bounce Disabled,1: Tx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit" "0: Tx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: Tx_EXT (x= 0~3) pin de-bounce or ACMP output.."
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bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: Tx_EXT (x= 0~3) pin detection Interrupt..,1: Tx_EXT (x= 0~3) pin detection Interrupt Enabled"
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bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled"
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bitfld.long 0x00 3. "CAPEN,Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function" "0: Tx_EXT (x= 0~3) pin Disabled,1: Tx_EXT (x= 0~3) pin Enabled"
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bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
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group.long 0x118++0x03
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line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status" "0: Tx_EXT (x= 0~3) pin interrupt did not occur,1: Tx_EXT (x= 0~3) pin interrupt occurred"
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group.long 0x11C++0x03
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line.long 0x00 "TIMER3_TRGCTL,Timer3 Trigger Control Register"
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bitfld.long 0x00 4. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered PDMA transfer" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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bitfld.long 0x00 2. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be triggered ADC conversion" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x00 1. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 each timer time-out event or capture event can be as PWM counter clock source" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled"
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bitfld.long 0x00 0. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal" "0: Time-out interrupt signal is used to internal..,1: Capture interrupt signal is used to internal.."
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group.long 0x120++0x03
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line.long 0x00 "TIMER3_ALTCTL,Timer3 Alternative Control Register"
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bitfld.long 0x00 0. "FUNCSEL,Function Selection\nNote: When timer is used as PWM the clock source of time controller will be forced to PCLKx automatically" "0: Timer controller is used as timer function,1: Timer controller is used as PWM function"
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group.long 0x140++0x03
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line.long 0x00 "TIMER3_PWMCTL,Timer3 PWM Control Register"
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bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled PWM counter will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x00 16. "OUTMODE,PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel" "0: PWM independent mode,1: PWM complementary mode"
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bitfld.long 0x00 9. "IMMLDEN,Immediately Load Enable Bit\nNote: If IMMLDEN is enabled CTRLD will be invalid" "0: PERIOD will load to PBUF when current PWM..,1: PERIOD/CMP will load to PBUF/CMPBUF.."
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bitfld.long 0x00 8. "CTRLD,Center Re-load\nIn up-down count type PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period" "0,1"
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bitfld.long 0x00 3. "CNTMODE,PWM Counter Mode" "0: Auto-reload mode,1: One-shot mode"
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bitfld.long 0x00 1.--2. "CNTTYPE,PWM Counter Behavior Type" "0: Up count type,1: Down count type,2: Up-down count type,3: Reserved"
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bitfld.long 0x00 0. "CNTEN,PWM Counter Enable Bit" "0: PWM counter and clock prescale Stop Running,1: PWM counter and clock prescale Start Running"
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group.long 0x144++0x03
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line.long 0x00 "TIMER3_PWMCLKSRC,Timer3 PWM Counter Clock Source Register"
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bitfld.long 0x00 0.--2. "CLKSRC,PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled the PWM counter clock source can be selected from TMR0_CLK TIMER1.." "0: TMRx_CLK,1: Internal TIMER0 time-out or capture event,2: Internal TIMER1 time-out or capture event,3: Internal TIMER2 time-out or capture event,4: Internal TIMER3 time-out or capture event,?..."
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group.long 0x148++0x03
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line.long 0x00 "TIMER3_PWMCLKPSC,Timer3 PWM Counter Clock Pre-scale Register"
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hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1)"
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group.long 0x14C++0x03
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line.long 0x00 "TIMER3_PWMCNTCLR,Timer3 PWM Clear Counter Register"
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bitfld.long 0x00 0. "CNTCLR,Clear PWM Counter Control Bit\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0x10000 in up and.."
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group.long 0x150++0x03
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line.long 0x00 "TIMER3_PWMPERIOD,Timer3 PWM Period Register"
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hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0 and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD then.."
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group.long 0x154++0x03
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line.long 0x00 "TIMER3_PWMCMPDAT,Timer3 PWM Comparator Register"
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hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform interrupt events and trigger ADC to start convert"
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group.long 0x158++0x03
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line.long 0x00 "TIMER3_PWMDTCTL,Timer3 PWM Dead-time Control Register"
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bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This register is write protected" "0: Dead-time clock source from TMRx_PWMCLK..,1: Dead-time clock source from TMRx_PWMCLK with.."
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bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair"
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hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected"
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group.long 0x15C++0x03
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line.long 0x00 "TIMER3_PWMCNT,Timer3 PWM Counter Register"
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rbitfld.long 0x00 16. "DIRF,PWM Counter Direction Indicator Flag (Read Only)" "0: Counter is active in down counting,1: Counter is active in up counting"
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hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter"
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group.long 0x160++0x03
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line.long 0x00 "TIMER3_PWMMSKEN,Timer3 PWM Output Mask Enable Register"
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bitfld.long 0x00 1. "MSKEN1,PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled" "0: PWMx_CH1 output signal is non-masked,1: PWMx_CH1 output signal is masked and output.."
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bitfld.long 0x00 0. "MSKEN0,PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled" "0: PWMx_CH0 output signal is non-masked,1: PWMx_CH0 output signal is masked and output.."
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group.long 0x164++0x03
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line.long 0x00 "TIMER3_PWMMSK,Timer3 PWM Output Mask Data Control Register"
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bitfld.long 0x00 1. "MSKDAT1,PWMx_CH1 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH1,1: Output logic High to PWMx_CH1"
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bitfld.long 0x00 0. "MSKDAT0,PWMx_CH0 Output Mask Data Control Bit" "0: Output logic Low to PWMx_CH0,1: Output logic High to PWMx_CH0"
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group.long 0x168++0x03
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line.long 0x00 "TIMER3_PWMBNF,Timer3 PWM Brake Pin Noise Filter Register"
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bitfld.long 0x00 16.--17. "BKPINSRC,Brake Pin Source Select" "0: Brake pin source comes from TM_BRAKE0,1: Brake pin source comes from TM_BRAKE1,2: Brake pin source comes from TM_BRAKE2,3: Brake pin source comes from TM_BRAKE3"
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bitfld.long 0x00 7. "BRKPINV,Brake Pin Detection Control Bit" "0: Brake pin event will be detected if TM_BRAKEx..,1: Brake pin event will be detected if TM_BRAKEx.."
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bitfld.long 0x00 4.--6. "BRKFCNT,Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 1.--3. "BRKNFSEL,Brake Pin Noise Filter Clock Selection" "0: Noise filter clock is PCLKx,1: Noise filter clock is PCLKx/2,2: Noise filter clock is PCLKx/4,3: Noise filter clock is PCLKx/8,4: Noise filter clock is PCLKx/16,5: Noise filter clock is PCLKx/32,6: Noise filter clock is PCLKx/64,7: Noise filter clock is PCLKx/128"
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bitfld.long 0x00 0. "BRKNFEN,Brake Pin Noise Filter Enable Bit" "0: Pin noise filter detect of TM_BRAKEx Disabled,1: Pin noise filter detect of TM_BRAKEx Enabled"
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group.long 0x16C++0x03
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line.long 0x00 "TIMER3_PWMFAILBRK,Timer3 PWM System Fail Brake Control Register"
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bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by core lockup event..,1: Brake Function triggered by core lockup event.."
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bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by BOD event Disabled,1: Brake Function triggered by BOD event Enabled"
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bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function Enable Bit" "0: Brake Function triggered by clock fail..,1: Brake Function triggered by clock fail.."
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group.long 0x170++0x03
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line.long 0x00 "TIMER3_PWMBRKCTL,Timer3 PWM Brake Control Register"
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bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH1 output tri-state when TIMERx_PWM..,2: PWMx_CH1 output low level when TIMERx_PWM..,3: PWMx_CH1 output high level when TIMERx_PWM.."
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bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected" "0: TIMERx_PWM brake event will not affect..,1: PWMx_CH0 output tri-state when TIMERx_PWM..,2: PWMx_CH0 output low level when TIMERx_PWM..,3: PWMx_CH0 output high level when TIMERx_PWM.."
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bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as level-detect brake..,1: System fail condition as level-detect brake.."
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bitfld.long 0x00 12. "BRKPLEN,Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as level-detect brake..,1: TM_BRAKEx pin event as level-detect brake.."
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bitfld.long 0x00 9. "CPO1LBEN,Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected" "0: Internal ACMP1_O signal as level-detect brake..,1: Internal ACMP1_O signal as level-detect brake.."
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bitfld.long 0x00 8. "CPO0LBEN,Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as level-detect brake..,1: Internal ACMP0_O signal as level-detect brake.."
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bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: System fail condition as edge-detect brake..,1: System fail condition as edge-detect brake.."
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bitfld.long 0x00 4. "BRKPEEN,Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: TM_BRAKEx pin event as edge-detect brake..,1: TM_BRAKEx pin event as edge-detect brake.."
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bitfld.long 0x00 1. "CPO1EBEN,Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP1_O signal as edge-detect brake..,1: Internal ACMP1_O signal as edge-detect brake.."
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bitfld.long 0x00 0. "CPO0EBEN,Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected" "0: Internal ACMP0_O signal as edge-detect brake..,1: Internal ACMP0_O signal as edge-detect brake.."
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group.long 0x174++0x03
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line.long 0x00 "TIMER3_PWMPOLCTL,Timer3 PWM Pin Output Polar Control Register"
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bitfld.long 0x00 1. "PINV1,PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin" "0: PWMx_CH1 output pin polar inverse Disabled,1: PWMx_CH1 output pin polar inverse Enabled"
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bitfld.long 0x00 0. "PINV0,PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin" "0: PWMx_CH0 output pin polar inverse Disabled,1: PWMx_CH0 output pin polar inverse Enabled"
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group.long 0x178++0x03
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line.long 0x00 "TIMER3_PWMPOEN,Timer3 PWM Pin Output Enable Register"
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bitfld.long 0x00 1. "POEN1,PWMx_CH1 Output Pin Enable Bit" "0: PWMx_CH1 pin at tri-state mode,1: PWMx_CH1 pin in output mode"
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bitfld.long 0x00 0. "POEN0,PWMx_CH0 Output Pin Enable Bit" "0: PWMx_CH0 pin at tri-state mode,1: PWMx_CH0 pin in output mode"
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group.long 0x17C++0x03
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line.long 0x00 "TIMER3_PWMSWBRK,Timer3 PWM Software Trigger Brake Control Register"
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bitfld.long 0x00 8. "BRKLTRG,Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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bitfld.long 0x00 0. "BRKETRG,Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register" "0,1"
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group.long 0x180++0x03
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line.long 0x00 "TIMER3_PWMINTEN0,Timer3 PWM Interrupt Enable Register 0"
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bitfld.long 0x00 3. "CMPDIEN,PWM Compare Down Count Interrupt Enable Bit" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x00 2. "CMPUIEN,PWM Compare Up Count Interrupt Enable Bit" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x00 1. "PIEN,PWM Period Point Interrupt Enable Bit\nNote: In up-down count type period point means the center point of current PWM period" "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x00 0. "ZIEN,PWM Zero Point Interrupt Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0x184++0x03
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line.long 0x00 "TIMER3_PWMINTEN1,Timer3 PWM Interrupt Enable Register 1"
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bitfld.long 0x00 8. "BRKLIEN,PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM level-detect brake interrupt Disabled,1: PWM level-detect brake interrupt Enabled"
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bitfld.long 0x00 0. "BRKEIEN,PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected" "0: PWM edge-detect brake interrupt Disabled,1: PWM edge-detect brake interrupt Enabled"
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group.long 0x188++0x03
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line.long 0x00 "TIMER3_PWMINTSTS0,Timer3 PWM Interrupt Status Register 0"
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bitfld.long 0x00 3. "CMPDIF,PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing.." "0,1"
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bitfld.long 0x00 2. "CMPUIF,PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is.." "0,1"
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bitfld.long 0x00 1. "PIF,PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it" "0,1"
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bitfld.long 0x00 0. "ZIF,PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it" "0,1"
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group.long 0x18C++0x03
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line.long 0x00 "TIMER3_PWMINTSTS1,Timer3 PWM Interrupt Status Register 1"
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rbitfld.long 0x00 25. "BRKLSTS1,Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH1 level-detect brake state is released,1: PWMx_CH1 at level-detect brake state"
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rbitfld.long 0x00 24. "BRKLSTS0,Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform.." "0: PWMx_CH0 level-detect brake state is released,1: PWMx_CH0 at level-detect brake state"
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rbitfld.long 0x00 17. "BRKESTS1,Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period" "0: PWMx_CH1 edge-detect brake state is released,1: PWMx_CH1 at edge-detect brake state"
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rbitfld.long 0x00 16. "BRKESTS0,Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period" "0: PWMx_CH0 edge-detect brake state is released,1: PWMx_CH0 at edge-detect brake state"
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bitfld.long 0x00 9. "BRKLIF1,Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 level-detect brake event did not..,1: PWMx_CH1 level-detect brake event happened"
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bitfld.long 0x00 8. "BRKLIF0,Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 level-detect brake event did not..,1: PWMx_CH0 level-detect brake event happened"
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bitfld.long 0x00 1. "BRKEIF1,Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH1 edge-detect brake event did not happen,1: PWMx_CH1 edge-detect brake event happened"
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bitfld.long 0x00 0. "BRKEIF0,Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected" "0: PWMx_CH0 edge-detect brake event did not happen,1: PWMx_CH0 edge-detect brake event happened"
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group.long 0x190++0x03
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line.long 0x00 "TIMER3_PWMADCTS,Timer3 PWM ADC Trigger Source Select Register"
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bitfld.long 0x00 7. "TRGEN,PWM Counter Event Trigger ADC Conversion Enable Bit" "0: PWM counter event trigger ADC conversion..,1: PWM counter event trigger ADC conversion.."
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bitfld.long 0x00 0.--2. "TRGSEL,PWM Counter Event Source Select to Trigger ADC Conversion" "0: Trigger ADC conversion at zero point (ZIF),1: Trigger ADC conversion at period point (PIF),2: Trigger ADC conversion at zero or period..,3: Trigger ADC conversion at compare up count..,4: Trigger ADC conversion at compare down count..,?..."
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group.long 0x194++0x03
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line.long 0x00 "TIMER3_PWMSCTL,Timer3 PWM Synchronous Control Register"
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bitfld.long 0x00 8. "SYNCSRC,PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0 TIME0_PWMSCTL[8] TIME1_PWMSCTL[8] TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter.." "0: Counter synchronous start/clear by trigger..,1: Counter synchronous start/clear by trigger.."
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bitfld.long 0x00 0.--1. "SYNCMODE,PWM Synchronous Mode Enable Select" "0: PWM synchronous function Disabled,1: PWM synchronous counter start function Enabled,2: Reserved,3: PWM synchronous counter clear function Enabled"
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group.long 0x19C++0x03
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line.long 0x00 "TIMER3_PWMSTATUS,Timer3 PWM Status Register"
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bitfld.long 0x00 16. "ADCTRGF,Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter event trigger ADC start..,1: PWM counter event trigger ADC start.."
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bitfld.long 0x00 0. "CNTMAXF,PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it" "0: PWM counter value never reached its maximum..,1: PWM counter value has reached its maximum value"
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group.long 0x1A0++0x03
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line.long 0x00 "TIMER3_PWMPBUF,Timer3 PWM Period Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register"
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group.long 0x1A4++0x03
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line.long 0x00 "TIMER3_PWMCMPBUF,Timer3 PWM Comparator Buffer Register"
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hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register"
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tree.end
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tree.end
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tree "UART"
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tree "UART0"
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base ad:0x40050000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.."
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART1"
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base ad:0x40150000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote: This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.."
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree "UART2"
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base ad:0x40154000
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group.long 0x00++0x03
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line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1"
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hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
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group.long 0x04++0x03
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line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nThis bit can enable or disable TX PDMA service" "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
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bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
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bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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group.long 0x08++0x03
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line.long 0x00 "UART_FIFO,UART FIFO Control Register"
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bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
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bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..."
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bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.."
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bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.."
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group.long 0x0C++0x03
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line.long 0x00 "UART_LINE,UART Line Control Register"
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bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled"
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bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled"
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bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software"
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bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.."
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bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
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group.long 0x10++0x03
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line.long 0x00 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
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bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.2213 and Figure 6.2214 for UART function mode.\nNote2: Refer to Figure 6.2224 and Figure 6.2225 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
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bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive"
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group.long 0x14++0x03
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line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
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rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state"
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group.long 0x18++0x03
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line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active"
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rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle"
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rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
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rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
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rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
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bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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group.long 0x1C++0x03
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line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
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rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.."
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rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode"
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rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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rbitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only)\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated"
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rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.."
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rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.."
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rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
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rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF(UART_LINSTS[0]) BRKDETF(UART_LINSTS[8]) BITEF(UART_LINSTS[9]) SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing '1' to LINIF(UART_INTSTS[7])" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
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rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x03
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line.long 0x00 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
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hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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group.long 0x24++0x03
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line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
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bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
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bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
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group.long 0x28++0x03
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line.long 0x00 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal"
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bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
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bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit\nNote: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
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group.long 0x2C++0x03
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line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode"
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bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
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bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
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bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
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bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
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bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x30++0x03
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line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x00 0.--1. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function"
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group.long 0x34++0x03
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line.long 0x00 "UART_LINCTL,UART LIN Control Register (Only for UART0 and UART1)"
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hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID [29:24] ) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this.."
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bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved"
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bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
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bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled"
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bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled"
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bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled"
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bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
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bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
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bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.22.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
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bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
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bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
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bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
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bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled"
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group.long 0x38++0x03
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line.long 0x00 "UART_LINSTS,UART LIN Status Register (Only for UART0 and UART1)"
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bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected"
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bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected"
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bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
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bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct"
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bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
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bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
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group.long 0x3C++0x03
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line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not"
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group.long 0x40++0x03
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line.long 0x00 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1" "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode\nand ADDRDEN (UART_ALTCTL[15]) is set to 1" "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.."
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bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled when the.."
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group.long 0x44++0x03
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line.long 0x00 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.."
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bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.."
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bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.."
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group.long 0x48++0x03
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line.long 0x00 "UART_DWKCOMP,UART Imcoming Data Wake-up Compensation Register"
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hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.\nNote: It is valid only when WKDATEN.."
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tree.end
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tree.end
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tree "UI2C"
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repeat 2. (list 0. 1.) (list ad:0x40070000 ad:0x40170000)
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tree "UI2C$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "UI2C_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x08++0x03
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line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x2C++0x03
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line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 8-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote1: In I2C protocol only use RXDAT[7:0]"
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group.long 0x44++0x03
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line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
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hexmask.long.word 0x00 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address"
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group.long 0x48++0x03
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line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
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hexmask.long.word 0x00 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address"
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group.long 0x4C++0x03
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line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
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group.long 0x50++0x03
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line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
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hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
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group.long 0x54++0x03
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line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled"
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hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
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bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: Monitor mode Disabled,1: Monitor mode Enabled"
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bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
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newline
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bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
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bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled"
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bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
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bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
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newline
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bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
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bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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group.long 0x60++0x03
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line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled"
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bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt Disabled,1: The error interrupt Enabled"
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newline
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bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled"
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bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled"
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newline
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bitfld.long 0x00 2. "STORIEN,Stop Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a stop condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled"
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bitfld.long 0x00 1. "STARIEN,Start Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a start condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled"
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newline
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bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
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bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
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newline
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bitfld.long 0x00 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave read request has not been detected,1: A slave read request has been detected"
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newline
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bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nIt is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
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newline
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bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nIt is cleared by software writing 1 into this bit\nNote: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: An arbitration has not been lost,1: An arbitration has been lost"
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newline
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bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
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newline
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bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
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newline
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bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
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group.long 0x88++0x03
|
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line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
|
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bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status\nWhen address 1 is matched hardware will inform which address used" "0,1"
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|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status\nWhen address 0 is matched hardware will inform which address used" "0,1"
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group.long 0x8C++0x03
|
|
line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
bitfld.long 0x00 6.--11. "HTCTL,Hold Time Configure Control\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "STCTL,Setup Time Configure Control\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree.end
|
|
repeat.end
|
|
tree "UI2C2"
|
|
base ad:0x40074000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UI2C_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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|
group.long 0x08++0x03
|
|
line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled"
|
|
bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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|
newline
|
|
bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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|
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "UI2C_LINECTL,USCI Line Control Register"
|
|
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\n"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "UI2C_DEVADDR0,USCI Device Address Register 0"
|
|
hexmask.long.word 0x00 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "UI2C_DEVADDR1,USCI Device Address Register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK0,USCI Device Address Mask Register 0"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UI2C_ADDRMSK1,USCI Device Address Mask Register 1"
|
|
hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
|
|
bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol disable,1: I2C Protocol enable"
|
|
hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear"
|
|
newline
|
|
bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode is disabled,1: The monitor mode is enabled"
|
|
bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.."
|
|
newline
|
|
bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active"
|
|
bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function is disabled,1: Address match 10 bit function is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
|
|
bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1"
|
|
bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt is disabled,1: The acknowledge interrupt is enabled"
|
|
bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16]))" "0: The error interrupt is disabled,1: The error interrupt is enabled"
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|
newline
|
|
bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt is disabled,1: The arbitration lost interrupt is enabled"
|
|
bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master" "0: The non - acknowledge interrupt is disabled,1: The non - acknowledge interrupt is enabled"
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|
newline
|
|
bitfld.long 0x00 2. "STORIEN,Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected" "0: The stop condition interrupt is disabled,1: The stop condition interrupt is enabled"
|
|
bitfld.long 0x00 1. "STARIEN,Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected" "0: The start condition interrupt is disabled,1: The start condition interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Control\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt is disabled,1: The time-out interrupt is enabled"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register"
|
|
bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.."
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|
bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission"
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|
newline
|
|
bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.."
|
|
bitfld.long 0x00 16. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.."
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|
newline
|
|
bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave read request has not been detected,1: A slave read request has been detected"
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|
bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave"
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newline
|
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bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received"
|
|
bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode user must write one into STO register to the defined 'not addressed' slave mode" "0: An I2C error has not been detected,1: An I2C error has been detected"
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|
newline
|
|
bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost"
|
|
bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received"
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|
newline
|
|
bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit" "0: A stop condition has not yet been detected,1: A stop condition has been detected"
|
|
bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected"
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|
newline
|
|
bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy"
|
|
bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register"
|
|
bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1"
|
|
bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register"
|
|
bitfld.long 0x00 6.--11. "HTCTL,Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "STCTL,Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
tree.end
|
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tree.end
|
|
tree "USPI"
|
|
repeat 2. (list 0. 1.) (list ad:0x40070000 ad:0x40170000)
|
|
tree "USPI$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USPI_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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|
group.long 0x04++0x03
|
|
line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
|
|
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
|
|
bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: I2C function the minimum value of CLKDIV is 8"
|
|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
|
|
newline
|
|
bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled"
|
|
bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
|
|
newline
|
|
bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
|
|
bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
|
|
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
|
|
bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
|
|
bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol it is suggested this bit.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
|
|
bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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|
newline
|
|
bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
|
|
bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
|
|
bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
|
|
bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
|
|
bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
|
|
newline
|
|
bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
|
|
bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
|
|
bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
|
bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
|
|
bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
|
|
newline
|
|
bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
|
|
bitfld.long 0x00 3. "RXOVIF,Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
|
|
newline
|
|
bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
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|
newline
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
|
|
bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under-run..,1: The output data level is 1 if TX under-run.."
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|
newline
|
|
hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
|
|
bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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|
newline
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
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|
bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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|
newline
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
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|
group.long 0x60++0x03
|
|
line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])" "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
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|
bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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|
newline
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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|
bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
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|
group.long 0x64++0x03
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|
line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
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|
rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
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newline
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
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|
bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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|
newline
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
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bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event does not occur,1: Slave bit count error event occurs"
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newline
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bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: This bit is cleared by software writing 1 to it" "0: Slave time-out event did not occur,1: Slave time-out event occurred"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: Receive end event does not occur,1: Receive end event occurred"
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newline
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: Receive start event did not occur,1: Receive start event occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: Transmit end event did not occur,1: Transmit end event occurred"
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newline
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: This bit is cleared by software writing 1 to it" "0: Transmit start event did not occur,1: Transmit start event occurred"
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tree.end
|
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repeat.end
|
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tree "USPI2"
|
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base ad:0x40074000
|
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group.long 0x00++0x03
|
|
line.long 0x00 "USPI_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
|
|
line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register"
|
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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newline
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
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|
group.long 0x08++0x03
|
|
line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: I2C function the minimum value of CLKDIV is 8"
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|
bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK"
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newline
|
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bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter is Disabled,1: Time measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK"
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newline
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
|
|
line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol we suggest this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol we.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol we.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.\nNote: In SPI protocol we suggest this bit should be.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "USPI_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.."
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newline
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin" "0: Data output level is not inverted,1: Data output level is inverted"
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register"
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bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "USPI_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer"
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group.long 0x38++0x03
|
|
line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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newline
|
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared"
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Control" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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newline
|
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared"
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bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under-run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled"
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rgroup.long 0x3C++0x03
|
|
line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register"
|
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bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.."
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|
bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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newline
|
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bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.."
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Overrun Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.."
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newline
|
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bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
|
|
bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register"
|
|
bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
|
|
bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match"
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newline
|
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register"
|
|
bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register"
|
|
bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled"
|
|
bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level when no data is available for transferring" "0: The output data level is 0 if TX under-run..,1: The output data level is 1 if TX under-run.."
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|
newline
|
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hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period (Slave Only)\nIn Slave mode this bit field is used for Slave time-out period"
|
|
bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7"
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|
newline
|
|
bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3"
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|
newline
|
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bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.."
|
|
bitfld.long 0x00 2. "SS,Slave Select Control (Master Only)\nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol the internal.." "0,1"
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|
newline
|
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bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface"
|
|
bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Control\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH.." "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.."
|
|
bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Control\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled"
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|
newline
|
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bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.."
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|
bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Control\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.."
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register"
|
|
rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under-run event does not occur,1: Slave transmit under-run event occurs"
|
|
rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state"
|
|
newline
|
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rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1"
|
|
bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active"
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|
newline
|
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bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive"
|
|
bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit" "0: Slave bit count error event does not occur,1: Slave bit count error event occurs"
|
|
newline
|
|
bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software writes 1 to this bit" "0: Slave time-out event does not occur,1: Slave time-out event occurs"
|
|
bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive end event does not occur,1: Receive end event occurs"
|
|
newline
|
|
bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Receive start event does not occur,1: Receive start event occurs"
|
|
bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit end event does not occur,1: Transmit end event occurs"
|
|
newline
|
|
bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software writes 1 to this bit" "0: Transmit start event does not occur,1: Transmit start event occurs"
|
|
tree.end
|
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tree.end
|
|
tree "UUART"
|
|
repeat 2. (list 0. 1.) (list ad:0x40070000 ad:0x40170000)
|
|
tree "UUART$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UUART_CTL,USCI Control Register"
|
|
bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
|
|
bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled"
|
|
bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled"
|
|
bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter Disabled,1: Timing measurement counter Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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rgroup.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detail information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART will reassert nRTS signal.\nNote1: This bit is used for nRTS auto direction control for RS485.\nNote2: This bit.." "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit is used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit is used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit.\nNote2: Used for user to load next transmit data when there is no data in transmit buffer" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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repeat.end
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tree "UUART2"
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base ad:0x40074000
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group.long 0x00++0x03
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line.long 0x00 "UUART_CTL,USCI Control Register"
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bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..."
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group.long 0x04++0x03
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line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register"
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bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt is disabled,1: The receive end interrupt is enabled"
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bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt is disabled,1: The receive start interrupt is enabled"
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bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt is disabled,1: The transmit finish interrupt is enabled"
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bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt is disabled,1: The transmit start interrupt is enabled"
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group.long 0x08++0x03
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line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register"
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hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled"
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bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3"
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bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK"
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bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled"
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bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK"
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bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)"
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bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved"
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group.long 0x10++0x03
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line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0"
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bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.."
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x20++0x03
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line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0"
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bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.."
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x28++0x03
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line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register"
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bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.."
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group.long 0x2C++0x03
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line.long 0x00 "UUART_LINECTL,USCI Line Control Register"
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bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.."
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bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.."
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bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.."
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wgroup.long 0x30++0x03
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line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register"
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hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission"
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rgroup.long 0x34++0x03
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line.long 0x00 "UUART_RXDAT,USCI Receive Data Register"
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hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])"
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group.long 0x38++0x03
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line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register"
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bitfld.long 0x00 17. "RXRST,Receive Reset\n" "0: No effect,1: Reset the receive-related counters state.."
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bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.."
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bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.."
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bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Control" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled"
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bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.."
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rgroup.long 0x3C++0x03
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line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register"
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bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full"
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bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
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bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.."
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bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full"
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bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty"
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group.long 0x54++0x03
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line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register"
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bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.."
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bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled"
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group.long 0x58++0x03
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line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register"
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bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1"
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group.long 0x5C++0x03
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line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register"
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bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled"
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bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled"
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bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detail information" "0: Stick parity Disabled,1: Stick parity Enabled"
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hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits"
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bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled"
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bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled"
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bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART will reassert nRTS signal.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled"
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bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled"
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bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2"
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group.long 0x60++0x03
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line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register"
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bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled"
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bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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group.long 0x64++0x03
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line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register"
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rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
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rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high"
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bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun"
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rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY"
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bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done"
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bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus"
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bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by write '1'.." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by write '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred"
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bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred"
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bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing one into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred"
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bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred"
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tree.end
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tree.end
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tree "WDT"
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base ad:0x40004000
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group.long 0x00++0x03
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line.long 0x00 "WDT_CTL,WDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user execute enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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bitfld.long 0x00 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period after WDT starts counting.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK"
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bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\nNote1: This bit is write protected" "0: Set WDT counter stop and internal up counter..,1: Set WDT counter start"
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bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled when WDT time-out event occurs the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the WDT time-out event has triggered chip wake-up or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode.."
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bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will generate a.." "0: Trigger wake-up event function Disabled if..,1: Trigger wake-up event function Enabled if WDT.."
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bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt event did not occur,1: WDT time-out interrupt event occurred"
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bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset system event or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset system event did not occur,1: WDT time-out reset system event has been.."
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bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset system function Disabled,1: WDT time-out reset system function Enabled"
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group.long 0x04++0x03
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line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Period Selection (Write Protect)\nWhen WDT time-out event happened user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred" "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK"
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wgroup.long 0x08++0x03
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line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.\nNote: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active"
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tree.end
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tree "WWDT"
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base ad:0x40004100
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wgroup.long 0x00++0x03
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line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT.."
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group.long 0x04++0x03
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line.long 0x00 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nThe WWDT down counter will keep counting no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Value\nSet this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
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bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled when WWDTIF (WWDT_STATUS[0]) is set to 1 the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt disabled,1: WWDT counter compare match interrupt enabled"
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bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit\nSet this bit to start WWDT counter counting" "0: WWDT counter is stopped,1: WWDT counter is starting counting"
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group.long 0x08++0x03
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line.long 0x00 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset System Flag\nIf this bit is set to 1 it indicates that system has been reset by WWDT counter time-out reset system event.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset system event did not occur,1: WWDT time-out reset system event occurred"
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bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT CNTDAT matches the CMPDAT"
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rgroup.long 0x0C++0x03
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line.long 0x00 "WWDT_CNT,WWDT Counter Value Register"
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bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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tree.end
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autoindent.off
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